CN101138089A - 层叠型半导体装置及层叠型半导体装置的制造方法 - Google Patents

层叠型半导体装置及层叠型半导体装置的制造方法 Download PDF

Info

Publication number
CN101138089A
CN101138089A CNA200580048790XA CN200580048790A CN101138089A CN 101138089 A CN101138089 A CN 101138089A CN A200580048790X A CNA200580048790X A CN A200580048790XA CN 200580048790 A CN200580048790 A CN 200580048790A CN 101138089 A CN101138089 A CN 101138089A
Authority
CN
China
Prior art keywords
substrate
semiconductor device
electrode
laminated semiconductor
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA200580048790XA
Other languages
English (en)
Other versions
CN101138089B (zh
Inventor
新间康弘
小野寺正德
目黑弘一
田谷耕治
田中淳二
河西纯一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sbanson Japan Co Ltd
Spansion LLC
Original Assignee
Sbanson Japan Co Ltd
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sbanson Japan Co Ltd, Spansion LLC filed Critical Sbanson Japan Co Ltd
Publication of CN101138089A publication Critical patent/CN101138089A/zh
Application granted granted Critical
Publication of CN101138089B publication Critical patent/CN101138089B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09145—Edge details
    • H05K2201/09181—Notches in edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/361—Assembling flexible printed circuits with other printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

本发明的层叠型半导体装置为包含有被层叠的多个半导体装置、连接至所述半导体装置且含有设置于端面的电极的多个中继基板、以及将设置于所述中继基板端面的电极予以连接的连接基板。设置于中继基板端面的电极为利用例如具有导电性的接着剂或各向异性导电薄膜而连接于连接基板。藉此，由于以连接基板连接设置于多个中继基板端面的电极，且连接仅在端面进行，没有必要设置连接基板的弯曲部，故有效于层叠型半导体装置的小型化。此外，由于能够对应各种尺寸的封装件，故能够以短交货期提供层叠型半导体装置。

Description

层叠型半导体装置及层叠型半导体装置的制造方法
技术领域
本发明为有关一种层叠型半导体装置及层叠型半导体装置的制造方法。
背景技术
近年来，移动式电话机此类的便携式电子机器或IC记忆卡此类的非易失性存储媒体等产品被更加地小型化，且这些机器和媒体的部件数的削减及部件的小型化亦被要求。因此，期望一种有效率地封装构成这些机器的部件中主要部件的半导体组件的技术开发。
做为满足所述要求的封装件技术，已提案有与半导体组件相同大小的封装件的芯片尺寸封装(Chip Size package；CSP)、将多个半导体组件收容至1个封装件内的多芯片封装(Multi Chip Package；MCP)、以及层叠多个封装件而成为1个封装件的层叠型封装(Package on Package；PoP)等封装技术。
第1图为显示习知的层叠型半导体装置的图(习知技术1)。如第1图所示，层叠型半导体装置1包含有上封装件2与下封装件3。上封装件2包含有半导体组件21、基板22、以及连接半导体组件21与基板22的导线23。上封装件2的树脂封装部24是以使用有金属的模塑成形法来形成。上封装件2与下封装件3是通过焊球(solder ball)而电性连接。
第2图是显示另一个习知的层叠型半导体装置的图(习知技术2)。如第2图所示，层叠型半导体装置50是通过焊球将多个封装件51至53连接至柔性基板54。此外，做为层叠型半导体装置的另一习知例，而提案有如以下者。
专利文献1为揭示与习知技术2同样使用有柔性基板的层叠型半导体装置。专利文献2的层叠型半导体装置于中继基板端部表面所装载的隔离物的侧面设置有电极，并以连接基板连接这些电极。专利文献3的层叠型半导体装置，于中继基板的两面设置的配线是通过基板侧面的配线而相互连接。专利文献4的层叠型半导体装置是在层叠有多个侧面具有电极的半导体芯片的层叠体的侧面以电极连接线连接电极。
专利文献1：美国专利公报6,121,676号
专利文献2：日本公开专利公报特开2001-111192号
专利文献3：日本公开专利公报特开2000-294725号
专利文献4：日本公开专利公报特开2002-76167号
发明内容
发明所欲解决的课题
然而，习知技术中，为了使封装件层叠而使用具有使可层叠的上下封装件的电极(平台部；land)位置一致的构成的专用的上下封装件。当各别以模塑成形法制作该上下封装件时，模具的制作通常需要1至2个月的时间。而样品的规格也因装载的组件不同而有几种规格，封装件的尺寸也不同。因此，有从提出需求到样品完成要花掉许多时间的情形。
此外，在使用有所述习知的柔性基板的层叠型半导体装置中，由于使用柔性基板的弯曲折叠构造，故有柔性基板的弯曲部分会超出半导体装置的外形，而对封装件的小型化造成阻碍的问题。
在专利文献2记载的技术中，由于必须于中继基板的外周部确保用来配设隔离物(spacer)的面积，故不利于将封装件面积小型化。此外，在专利文献3记载的技术中，设置于中继基板两面的配线虽通过基板侧面的配线而相互地连接，且没有干涉到中继基板间的相互连接，但1与专利文献2记载的技术同样地，由于用于中继基板间的接续的电极存在于中继基板的外周部，故在面积上是不利的。在专利文献4记载的技术中，仅以预先决定的半导体芯片为对象，有无法适用于层叠不同种类的封装件的问题。
因此，本发明乃有鉴于所述问题而研创者，其目的为提供短交货期且小型的层叠型半导体装置及层叠型半导体装置的制造方法。解决课题的手段
为了解决所述课题，本发明的层叠型半导体装置包含有多个半导体装置装置、含有设置于端面的电极且安装有所述半导体装置的多个中继基板、以及将设置于所述中继基板端面的电极予以连接的连接基板。依据本发明，由于连接仅在端面进行，故没有必要设置连接基板的弯曲部，故有效于层叠型半导体装置的小型化。此外，由于能够对应各种尺寸的封装件，故能够以短交货期提供层叠型半导体装置。
设置于所述中继基板端面的电极是以例如被切断的通孔(via hole)所形成。依据本发明，由于以相同制造步骤来制造形成电极的通孔以及相同中继基板上其它的通孔，故不同于习知技术中于的后加上连接器，不需使用新部件，而能抑制成本的上升。设置于所述中继基板端面的电极是以例如被切断且内部充填有导电性树脂的通孔所形成。
设置于所述中继基板端面的电极是利用例如具有导电性的接着剂或各向异性导电薄膜而连接于所述连接基板。由于具有导电性的接着剂能够仅针对欲涂布的地方以点胶机(dispenser)等机械来供给，所以能够稳定地进行中继基板与连接基板的连接。由于各向异性导电薄膜亦能够仅在电极部谋求电性连接，且接着材料厚度通常为一定，故有尺寸差异小，且预先将薄膜设置于连接基板藉此谋求工序的削减的优点。所述连接基板是以例如柔性基板所构成。依据本发明，由于即使在连接基板变形的状态亦能够进行连接，故能够对应中继基板间的尺寸变化，而能够防止连接不良造成良率的减低。
所述连接基板是以例如配线层为单层或多层构成的柔性基板所构成。设置于所述中继基板端面的电极与所述连接基板的连接较佳为作成在所述中继基板的多个边。
本发明还包含有装载于所述连接基板内侧的电子部件。依据本发明，能够不破坏外形尺寸而装载电子部件。所述中继基板是固定于例如下段的半导体装置。依据本发明，定位变得稳定，且能够让制造良率不受到影响。所述中继基板是利用接着剂固定于例如下段的半导体装置。依据本发明，由于双方以接着剂固定，故定位变得稳定，且能够让制造良率不受到影响。所述接着剂是以例如薄膜状的接着剂所构成。依据本发明，由于薄膜的厚度为一定，故能够确保中继基板的平行度，且能够防止因连接基板的连接不良造成的制造良率的减低。
本发明的层叠型半导体装置的制造方法包含有于端面分别设置有电极的多个中继基板安装半导体装置的步骤，以及利用连接基板将设置于所述各中继基板端面的电极予以连接的步骤。依据本发明，由于连接仅在端面进行，没有必要设置连接基板的弯曲部，故有效于层叠型半导体装置的小型化。此外，由于能够对应各种尺寸的封装件，故能够以短交货期提供层叠型半导体装置。
本发明还包含有将含有所述中继基板且具有内部设置有金属膜的通孔的基板沿着该通孔切断，藉此形成设置于所述中继基板端面的电极的步骤。依据本发明，由于以相同制造步骤来制造用来形成电极的通孔以及相同中继基板上其它的通孔，故不同于习知技术中于之后加上连接器，不需使用新部件，故能够抑制成本的上升。本发明还包含有将含有所述中继基板且具有充填有导电性树脂的通孔的基板沿该通孔切断，藉此形成设置于所述基板端面的电极的步骤。
本发明还包含有将含有所述中继基板且具有内部设置有金属膜的通孔的基板沿着该通孔切断，藉此形成设置于所述中继基板端面的电极的步骤，以及供给导电性接着剂或各向异性导电性薄膜至所述电极的步骤。依据本发明，即使在难以对通孔充填导电性接着剂的情况下，亦能够将连接基板连接至中继基板。
发明的效果
依据本发明，能够提供短交货期且小型的层叠型半导体装置及层叠型半导体装置的制造方法。
附图说明
第1图为显示习知的层叠型半导体装置的图。
第2图为显示另一习知的层叠型半导体装置的图。
第3图为显示有关本发明的实施形态的层叠型半导体装置的图。
第4图为显示设置于中继基板端面的电极与连接基板的连接状态的图。
第5图为显示设置于中继基板端面的电极与连接基板的连接状态的另一例的图。
第6图为显示中继基板的另一构成例的图。
第7图为显示于连接基板的表面装载有电子部件的层叠型半导体装置的图。
第8图为显示层叠型半导体装置的第1制造方法中，通孔的切断步骤的图。
第9图为显示层叠型半导体装置的第2制造方法中，通孔的切断步骤的图。
第10图为显示层叠型半导体装置的第2制造方法中，电性连接中继基板与连接基板的步骤的图。
具体实施方式
以下，参照附加的图标说明本发明的实施形态。第3图为显示有关本发明的实施形态的层叠型半导体装置的图。如第3图所示，层叠型半导体装置60包含有：被层叠的多个半导体装置61至64；多个中继基板71至73，连接有半导电装置61至64，且含有设置于端面的电极711至732、以及连接基板81、82，用以连接设置于多个中继基板71至73端面的电极711至732。例如，半导体装置62包含有：半导体组件621、基板622、连接半导体组件621与基板622的导线623、及树脂封装部625，并通过焊球624连接于中继基板71的端子。
第4图为显示设置于中继基板端面的电极与连接基板的连接状态的图。于中继基板72的两边形成有多数的电极721及722。这些电极721及722是通过配线图案(pattem)723而连接于设置在半导体装置63下的端子。设置于中继基板72端面的电极721、722是利用导电性接着剂93、94各自连接于连接基板81、82。如所述般使用导电性接着剂，能够仅针对欲涂布的部分以点胶机等机械来供给，所以能够稳定地进行中继基板与连接基板的连接。亦可使用各向异性导电薄膜取代该导电性接着剂。由于使用各向异性导电薄膜能够谋求仅在电极部电性连接，且接着材料厚度通常为一定，故有尺寸差异小，且利用预先将薄膜设置于连接基板而谋求工序的削减的优点。
第5图为显示设置在中继基板端面的电极与连接基板的连接状态的另一例的图。第5图为显示设置于中继基板端面的电极与连接基板的连接作成于中继基板的三边(多个边)的例。于中继基板172的三边形成有多数的电极721、722、724。这些电极721、722及724通过配线图案723而连接于设置在半导体装置63下的端子。设置于中继基板172端面的电极721、722、724通过导电性接着剂93、94、97而各自连接于连接基板81至83。
此处虽针对设置于中继基板端面的电极与连接基板的连接为作成于中继基板的三边的例做说明，但该连接亦可仅作成于中继基板的至少一边，，当由于面积的关系而难以将最大四边连接的中继基板上全部的端子/配线引导至基板侧面时，能够以第5图所示于中继基板的多个端设置连接基板来谋求解决。当以连接基板使四边连接时，有在基板的内侧产生密闭空间，而在回焊(reflow)等的热施加时因膨胀而产生破裂之虞的情形。在此情形下，较佳为最多使连接基板连接于三边。
再次参照第3图，连接基板81及82是以例如柔性基板所构成。此外，连接基板81及82是配线层为以单层或多层构成的柔性基板所构成。在第3图所示的例，连接基板81及82是以单层的配线层812与单层的保护层813所构成。经由该配线层812，各半导体装置61至64会电性连接于中继基板73所形成的焊球。当配线图案多时，亦可使用多层的配线层取代单层的配线层812。以柔性基板构成连接基板81及82，即使在使基板变形的状态下仍然能够进行连接，故能够对应中继基板间的尺寸变化，能够防止连接不良造成良率的减低。所以，由于中继基板间的间隙或平行度并非为一定，故解决在硬式基板中因间隙的大小或彼此的平行度而产生连接不良的可能性的习知问题。
此外，中继基板71及72是利用接着剂97、98而固定于下段的半导体装置63、64。在将连接基板81、82连接至中继基板71、72时，当中继基板71、72未固定于下段的半导体装置63、64时，有在连接连接基板81、82时双方的的定位会变得不稳定，而使制造良率受到影响之虞。当中继基板的面积比较大时该影响较令人担心。如上所述，利用接着剂97、98将中继基板71、72固定于下段的半导体装置63、64，由于双方以接着剂固定，故定位变得稳定，能够让制造良率不受到影响。
此外，接着剂97、98较佳为薄膜状接着剂。由于接着剂97、98使用薄膜状接着剂而使薄膜的厚度为一定，故能够确保中继基板71、72的平行度，而能够防止因连接基板81、82的连接不良造成的制造良率的减低。该薄膜可为以加热方法使接着力产生的一体型材料，亦可为接着剂涂布于中心薄膜(core film)的两面的三层型。
第6图为显示中继基板的另一构成例的图。如第6图所示，显示于中继基板272四边形成有电极721、722、724及725的例。于端子726连接有半导体装置的焊球，并通过设置在中继基板272内部的配线而连接于电极721、722、724及725。设置于中继基板272端面的电极721、722、724及725的排列间距(B)为比在中继基板272的表面所形成的端子726的间距(A)还小。在将中继基板上全部的端子/配线引导至基板侧面时，有将设置于中继基板端面的电极的排列间距缩小，而在布线上较灵活的优点。
第7图为显示于连接基板的表面装载有电子部件的层叠型半导体装置1 60的例子的图。如第7图所示，连接基板8 1及82的内侧的表面装载有芯片部件(电子部件)161及162。利用将电子部件装载于连接基板81及82的内侧，能够不破坏外形尺寸地来装载电子部件。装载的电子部件为例如芯片电容、芯片电阻等的芯片部件。这些部件大多比大规模集成电路(LSI)封装件或半导体组件的高度还小，所以能够配置于中继基板的间隙。
第8图为显示第1层叠型半导体装置的制造方法中，中继基板的制造步骤的图。第8图(a)显示切断前的中继基板的一部分，第8图(b)显示第8图(a)的A-A’剖面图，第8图(c)显示切断后的中继基板，第8图(d)显示第8图(c)的B-B’剖面图。此处显示使用充填有导电性树脂的通孔做为中继基板与连接基板的连接手段(例如第6图的电极721)的例。如第8图(a)所示，于基板372形成有端子373、374、通孔375、端子373、374及连接通孔375的配线图案377。于通孔375内充填有导电性接着剂376。将基板372沿着通孔375切断，而如第8图(c)所示，于中继基板的端面形成电极381、382。亦即，设置于中继基板端面的电极是由被切断且内部充填有导电性树脂的通孔所形成。
如此，将包含中继基板且具有充填有导电性树脂的通孔375的基板372沿着通孔375切断，使其切断面露出于基板端面，而能够做为连接至连接基板的电极。由于以相同制造步骤来制造用来形成电极的通孔以及相同中继基板上其它的通孔，故不同于习知技术中于之后加上连接器，不需使用新部件，而能够抑制成本的上升。为了制作足够的尺寸来连接电极以及提升生产效率，比起光刻法(photolithography)，通孔的形成较佳为以钻孔机开孔的方法。
第9图为显示第2层叠型半导体装置的制造方法的通孔切断步骤的图。第9图(a)显示切断前的中继基板的一部分，第9图(b)显示第9图(a)的C-C’剖面图，第9图(c)显示切断后的中继基板，第9图(d)显示(c)的D-D’剖面图。第10(e)图为显示第2层叠型半导体装置的制造方法中，利用导电性接着剂将中继基板与连接基板予以电性连接的步骤的俯视图。第10(f)图为第10(e)图的前视图。如第9图所示，于基板472形成有端子473、474、通孔475、端子473、474及连接通孔475的配线图案476。
于通孔475内侧设置有金属膜477。从第9图(a)的状态开始，将于中继基板472形成的通孔475切断后，便如第9(c)图所示，于中继基板的端面形成电极481、482。如第10图所示，供给导电性接着剂93或各向异性导电性薄膜至以切断后的通孔所形成的电极482，将设置于各中继基板472端面的的电极连接于连接基板8 1、82。如同上述，将包含中继基板且具有内部设置有金属膜的通孔的基板沿着通孔切断，使其切断面露出于基板端面，而能够做为连接至连接基板的电极。由于以相同制造步骤来制造用来形成电极的通孔以及相同中继基板上其它的通孔，故不同于习知技术中于之后加上连接器，不需使用新部件，而能够抑制成本的上升。为了制作足够的尺寸来连接电极以及提升生产效率，比起光刻法，通孔的形成较佳为以钻孔机开孔的方法。即使在难以对通孔充填导电性接着剂的情况下，亦能在将连接基板连接至中继基板时供给导电性接着剂或各向异性导电性薄膜至连接基板侧的电极或中继基板的电极侧，而能够将连接基板连接至中继基板。
接着，针对层叠型半导体装置的制造方法做说明。层叠型半导体装置的制造方法包含有：于端面分别设置有电极的多个中继基板安装半导体装置的第1步骤；将含有所述中继基板且具有通孔的基板沿着该通孔切断，藉此形成设置于所述基板端面的电极的第2步骤；以及利用连接基板连接设置于所述各中继基板端面的电极的第3步骤。亦可包含有将含有所述中继基板且具有充填有导电性树脂的通孔的基板沿着该通孔切断，藉此形成设置于所述基板端面的电极的步骤以取代第2步骤。此外，亦可包含有将所述中继基板且具有内部设置有金属膜的通孔的基板沿着该通孔切断，藉此形成设置于所述基板端面的电极的步骤，以及供给导电性接着剂或各向异性导电性薄膜至所述电极的步骤以取代第2步骤。
如同上述，由于以连接基板81、82连接设置于多个中继基板71至73端面的电极711至732而使连接仅在端面进行，故没有必要于连接基板81、82设置弯曲部，而有效于层叠型半导体装置的小型化。
以上虽然针对本发明的较佳实施例做了详述，但本发明并非为限定于特定的实施例者，在申请专利范围所记载的本发明的要旨的范围内，可进行各种的变形、变更。

Claims (15)

1.一种层叠型半导体装置，包含：
多个半导体装置；
多个中继基板，含有设置在端面的电极，且安装有所述半导体装置；以及
连接基板，将设置在所述中继基板端面的电极予以连接。
2.根据权利要求1所述的层叠型半导体装置，其中，设置在所述中继基板端面的电极是以被切断的通孔所形成。
3.根据权利要求1所述的层叠型半导体装置，其中，设置在所述中继基板端面的电极是以被切断且内部充填有导电性树脂的通孔所形成。
4.根据权利要求1所述的层叠型半导体装置，其中，设置在所述中继基板端面的电极利用具有导电性的接着剂或各向异性导电薄膜而连接于所述连接基板。
5.根据权利要求1所述的层叠型半导体装置，其中，所述连接基板为柔性基板。
6.根据权利要求1所述的层叠型半导体装置，其中，所述连接基板为配线层以单层或多层所构成的柔性基板。
7.根据权利要求1所述的层叠型半导体装置，其中，设置在所述中继基板端面的电极与所述连接基板的连接是作成在所述中继基板的多个边。
8.根据权利要求1至7中的任一项所述的层叠型半导体装置，还包含有装载于所述连接基板内侧的电子部件。
9.根据权利要求1所述的层叠型半导体装置，其中，所述中继基板固定于下段的半导体装置。
10.根据权利要求1所述的层叠型半导体装置，其中，所述中继基板是利用接着剂而固定于下段的半导体装置。
11.根据权利要求10所述的层叠型半导体装置，其中，所述接着剂为薄膜状的接着剂。
12.一种层叠型半导体装置的制造方法，包含：
将半导体装置安装于端面各自设置有电极的多个中继基板的步骤；以及
利用连接基板将设置在所述各中继基板端面的电极予以连接的步骤。
13.根据权利要求12所述的层叠型半导体装置的制造方法，还包含有将含有所述中继基板且具有通孔的基板沿着该通孔切断，而形成设置在所述中继基板端面的电极的步骤。
14.根据权利要求12所述的层叠型半导体装置的制造方法，还包含有将含有所述中继基板且具有已充填导电性树脂的通孔的基板沿着该通孔切断，而形成设置在所述中继基板端面的电极的步骤。
15.根据权利要求12所述的层叠型半导体装置的制造方法，还包含：
将含有所述中继基板且具有内部设置有金属膜的通孔的基板沿着该通孔切断，而形成设置在所述中继基板端面的电极的步骤；以及
供给导电性接着剂或各向异性导电性薄膜至所述电极的步骤。
CN200580048790XA 2005-01-31 2005-01-31 层叠型半导体装置及层叠型半导体装置的制造方法 Expired - Fee Related CN101138089B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2005/001339 WO2006082620A1 (ja) 2005-01-31 2005-01-31 積層型半導体装置及び積層型半導体装置の製造方法

Publications (2)

Publication Number Publication Date
CN101138089A true CN101138089A (zh) 2008-03-05
CN101138089B CN101138089B (zh) 2011-02-09

Family

ID=36777015

Family Applications (1)

Application Number Title Priority Date Filing Date
CN200580048790XA Expired - Fee Related CN101138089B (zh) 2005-01-31 2005-01-31 层叠型半导体装置及层叠型半导体装置的制造方法

Country Status (4)

Country Link
US (1) US7696616B2 (zh)
JP (1) JP4991518B2 (zh)
CN (1) CN101138089B (zh)
WO (1) WO2006082620A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102768996A (zh) * 2012-06-18 2012-11-07 日月光半导体制造股份有限公司 半导体封装构造及其制造方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4609248B2 (ja) * 2005-09-01 2011-01-12 コニカミノルタビジネステクノロジーズ株式会社 画像読取装置及び複写装置
JP2007250764A (ja) * 2006-03-15 2007-09-27 Elpida Memory Inc 半導体装置及びその製造方法
US7990727B1 (en) * 2006-04-03 2011-08-02 Aprolase Development Co., Llc Ball grid array stack
JP2007287906A (ja) * 2006-04-17 2007-11-01 Elpida Memory Inc 電極と電極の製造方法、及びこの電極を備えた半導体装置
US7732907B2 (en) * 2006-05-30 2010-06-08 Stats Chippac Ltd. Integrated circuit package system with edge connection system
US7791744B2 (en) * 2006-08-29 2010-09-07 International Business Machines Corporation Apparatus for and method of print resuming following a print interruption event
DE102006053461A1 (de) * 2006-11-09 2008-05-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Mikroelektronische Baugruppe und Verfahren zum Herstellen einer mikroelektronischen Baugruppe
US8823160B2 (en) * 2008-08-22 2014-09-02 Stats Chippac Ltd. Integrated circuit package system having cavity
JP2010056099A (ja) * 2008-08-26 2010-03-11 Hitachi Ltd 半導体装置
KR101394964B1 (ko) * 2010-10-12 2014-05-15 한국전자통신연구원 반도체 패키지 및 그 제조 방법
US20140151880A1 (en) * 2011-08-19 2014-06-05 Marvell World Trade Ltd. Package-on-package structures
US9209163B2 (en) 2011-08-19 2015-12-08 Marvell World Trade Ltd. Package-on-package structures
JP2014112606A (ja) * 2012-12-05 2014-06-19 Shinko Electric Ind Co Ltd 半導体パッケージ
US20160172292A1 (en) * 2014-12-16 2016-06-16 Mediatek Inc. Semiconductor package assembly
JP7015691B2 (ja) 2017-12-27 2022-02-03 新光電気工業株式会社 半導体装置
CN113015324B (zh) * 2019-12-19 2023-05-09 华为技术有限公司 电路板组件、电子设备、加工电路板组件的方法
CN113133201B (zh) * 2021-04-19 2022-09-02 京东方科技集团股份有限公司 用于显示屏的电路板、显示屏组件及其加工方法

Family Cites Families (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57169298A (en) * 1981-04-10 1982-10-18 Matsushita Electric Ind Co Ltd Device for connecting circuit board
US5016138A (en) * 1987-10-27 1991-05-14 Woodman John K Three dimensional integrated circuit package
US5446620A (en) * 1990-08-01 1995-08-29 Staktek Corporation Ultra high density integrated circuit packages
JPH0482887U (zh) * 1990-11-28 1992-07-20
JPH0513666A (ja) * 1991-06-29 1993-01-22 Sony Corp 複合半導体装置
US5397916A (en) * 1991-12-10 1995-03-14 Normington; Peter J. C. Semiconductor device including stacked die
JPH0677644A (ja) * 1992-08-27 1994-03-18 Fujitsu Ltd 三次元構造電子部品の端子部形成方法
JP2500756B2 (ja) * 1993-06-17 1996-05-29 日本電気株式会社 半導体装置モジュ―ル
US5514907A (en) * 1995-03-21 1996-05-07 Simple Technology Incorporated Apparatus for stacking semiconductor chips
JP3656861B2 (ja) * 1995-04-05 2005-06-08 ソニー株式会社 半導体集積回路装置及び半導体集積回路装置の製造方法
JPH08316408A (ja) * 1995-05-22 1996-11-29 Fujitsu Ltd 三次元構造半導体装置
KR100214463B1 (ko) * 1995-12-06 1999-08-02 구본준 클립형 리드프레임과 이를 사용한 패키지의 제조방법
JP3224978B2 (ja) * 1995-10-27 2001-11-05 富士通株式会社 半導体装置
US5754405A (en) * 1995-11-20 1998-05-19 Mitsubishi Semiconductor America, Inc. Stacked dual in-line package assembly
JPH09260568A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置及びその製造方法
FR2748888B1 (fr) * 1996-05-14 1998-06-19 Gec Alsthom Transport Sa Dispositif a elements semi-conducteurs de puissance
US6121676A (en) * 1996-12-13 2000-09-19 Tessera, Inc. Stacked microelectronic assembly and method therefor
US5857858A (en) * 1996-12-23 1999-01-12 General Electric Company Demountable and repairable low pitch interconnect for stacked multichip modules
JPH1187640A (ja) * 1997-09-09 1999-03-30 Hitachi Ltd 半導体装置および電子装置
US6207474B1 (en) * 1998-03-09 2001-03-27 Micron Technology, Inc. Method of forming a stack of packaged memory die and resulting apparatus
US6153929A (en) * 1998-08-21 2000-11-28 Micron Technology, Inc. Low profile multi-IC package connector
JP2000294725A (ja) 1999-04-08 2000-10-20 Sony Corp 半導体装置
JP2001111192A (ja) 1999-10-13 2001-04-20 Toshiba Corp 電子部品及びその製造方法、電子機器及び超音波センサ部品
JP3659872B2 (ja) * 1999-11-30 2005-06-15 新藤電子工業株式会社 半導体装置
JP3589928B2 (ja) * 2000-02-22 2004-11-17 株式会社東芝 半導体装置
JP2001326441A (ja) * 2000-05-17 2001-11-22 Sony Corp 複合配線板及びその製造方法
JP2002076167A (ja) 2000-08-29 2002-03-15 Sony Corp 半導体チップ、積層型半導体パッケージ、及びそれらの作製方法
JP3722209B2 (ja) * 2000-09-05 2005-11-30 セイコーエプソン株式会社 半導体装置
DE10044148A1 (de) * 2000-09-06 2002-03-21 Infineon Technologies Ag Elektronisches Bauteil mit gestapelten Bausteinen und Verfahren zu seiner Herstellung
JP2002305286A (ja) * 2001-02-01 2002-10-18 Mitsubishi Electric Corp 半導体モジュールおよび電子部品
JP3678158B2 (ja) * 2001-03-14 2005-08-03 株式会社村田製作所 モジュール基板の実装構造
KR100621991B1 (ko) * 2003-01-03 2006-09-13 삼성전자주식회사 칩 스케일 적층 패키지

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102768996A (zh) * 2012-06-18 2012-11-07 日月光半导体制造股份有限公司 半导体封装构造及其制造方法

Also Published As

Publication number Publication date
JPWO2006082620A1 (ja) 2008-08-07
US20060170090A1 (en) 2006-08-03
US7696616B2 (en) 2010-04-13
JP4991518B2 (ja) 2012-08-01
CN101138089B (zh) 2011-02-09
WO2006082620A1 (ja) 2006-08-10

Similar Documents

Publication Publication Date Title
CN101138089B (zh) 层叠型半导体装置及层叠型半导体装置的制造方法
US7378726B2 (en) Stacked packages with interconnecting pins
JP5467458B2 (ja) 半導体デバイス及び部品のパッケージ化装置、半導体デバイス及び部品のパッケージ化方法
US9313902B2 (en) Conductive structures for microfeature devices and methods for fabricating microfeature devices
KR100606178B1 (ko) 재배선층에 의해 상호 접속된 복수의 반도체 소자를가지는 반도체 장치
US7821127B2 (en) Semiconductor device package having buffered memory module and method thereof
CN101960591A (zh) 半导体装置、其制造方法、印刷电路板及电子设备
CN102498562A (zh) 柔性电路模块
EP0408779B1 (en) High density semiconductor memory module
US20210202461A1 (en) Method for embedding silicon die into a stacked package
CN101627471A (zh) 微电子工件及用于使用所述工件制造微电子装置的方法
CN105304584A (zh) 中介基板及其制造方法
CN105405835A (zh) 中介基板及其制法
US8836102B2 (en) Multilayered semiconductor device, printed circuit board, and method of manufacturing multilayered semiconductor device
US7880093B2 (en) 3-dimensional substrate for embodying multi-packages and method of fabricating the same
CN111354716B (zh) 堆叠中抽取的nand逻辑部件
KR100610144B1 (ko) 플립 칩 조립 구조를 가지는 칩-온-보드 패키지의 제조 방법
CN113169153B (zh) 一种芯片的封装结构
JP2507564B2 (ja) マルチチップ半導体装置とその製造方法
KR20070100338A (ko) 적층형 반도체 장치 및 적층형 반도체 장치의 제조 방법
US20230207481A1 (en) Printed circuit board and semiconductor package including the same
JP2012156528A (ja) 積層型半導体装置及び積層型半導体装置の製造方法
KR100543900B1 (ko) 적층형 반도체 패키지 및 그 제조방법
KR100677825B1 (ko) 적층형 플래쉬 메모리 칩 및 그 제조방법
KR101116731B1 (ko) 듀얼 다이 패키지

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110209

Termination date: 20170131

CF01 Termination of patent right due to non-payment of annual fee