CN100524744C - 芯片层叠型半导体装置 - Google Patents

芯片层叠型半导体装置 Download PDF

Info

Publication number
CN100524744C
CN100524744C CNB021221596A CN02122159A CN100524744C CN 100524744 C CN100524744 C CN 100524744C CN B021221596 A CNB021221596 A CN B021221596A CN 02122159 A CN02122159 A CN 02122159A CN 100524744 C CN100524744 C CN 100524744C
Authority
CN
China
Prior art keywords
mentioned
chip
terminal
interlayer
distribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB021221596A
Other languages
English (en)
Chinese (zh)
Other versions
CN1399338A (zh
Inventor
尾山胜彦
远藤光芳
田窪知章
山崎尚
井本孝志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of CN1399338A publication Critical patent/CN1399338A/zh
Application granted granted Critical
Publication of CN100524744C publication Critical patent/CN100524744C/zh
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/641—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CNB021221596A 2001-06-01 2002-05-31 芯片层叠型半导体装置 Expired - Fee Related CN100524744C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001167185A JP4109839B2 (ja) 2001-06-01 2001-06-01 半導体装置
JP167185/2001 2001-06-01

Publications (2)

Publication Number Publication Date
CN1399338A CN1399338A (zh) 2003-02-26
CN100524744C true CN100524744C (zh) 2009-08-05

Family

ID=19009610

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB021221596A Expired - Fee Related CN100524744C (zh) 2001-06-01 2002-05-31 芯片层叠型半导体装置

Country Status (5)

Country Link
US (1) US6861738B2 (https=)
JP (1) JP4109839B2 (https=)
KR (1) KR100512835B1 (https=)
CN (1) CN100524744C (https=)
TW (1) TW541585B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004095799A (ja) 2002-08-30 2004-03-25 Toshiba Corp 半導体装置およびその製造方法
JP4799157B2 (ja) 2005-12-06 2011-10-26 エルピーダメモリ株式会社 積層型半導体装置
CN100547784C (zh) * 2005-12-16 2009-10-07 晨星半导体股份有限公司 多芯片封装结构的内连线
JP2009026884A (ja) 2007-07-18 2009-02-05 Elpida Memory Inc 回路モジュール及び電気部品
TWI721960B (zh) * 2014-12-18 2021-03-21 日商新力股份有限公司 半導體裝置、製造方法及電子機器
US11824009B2 (en) * 2018-12-10 2023-11-21 Preferred Networks, Inc. Semiconductor device and data transferring method for semiconductor device
WO2023119450A1 (ja) * 2021-12-21 2023-06-29 ウルトラメモリ株式会社 半導体モジュール及び積層モジュール

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804874A (en) * 1996-03-08 1998-09-08 Samsung Electronics Co., Ltd. Stacked chip package device employing a plurality of lead on chip type semiconductor chips
CN1221982A (zh) * 1997-11-21 1999-07-07 罗姆股份有限公司 半导体装置及其制造方法
CN1239831A (zh) * 1998-06-24 1999-12-29 日本电气株式会社 半导体器件及其制造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04284661A (ja) * 1991-03-13 1992-10-09 Toshiba Corp 半導体装置
JPH10107205A (ja) * 1996-09-27 1998-04-24 Hitachi Ltd 積層半導体モジュール
SE511425C2 (sv) * 1996-12-19 1999-09-27 Ericsson Telefon Ab L M Packningsanordning för integrerade kretsar
JP2870530B1 (ja) * 1997-10-30 1999-03-17 日本電気株式会社 スタックモジュール用インターポーザとスタックモジュール
KR100271639B1 (ko) * 1997-12-23 2000-11-15 김영환 적층형 반도체패키지 및 그 제조방법 및 그 적층방법
DE19801312A1 (de) 1998-01-15 1999-07-22 Siemens Ag Halbleiterbauelement mit mehreren Substratlagen und zumindest einem Halbleiterchip und einem Verfahren zum Herstellen eines solchen Halbleiterbauelementes
KR20000011420U (ko) * 1998-12-02 2000-07-05 김영환 적층형 반도체 패키지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5804874A (en) * 1996-03-08 1998-09-08 Samsung Electronics Co., Ltd. Stacked chip package device employing a plurality of lead on chip type semiconductor chips
CN1221982A (zh) * 1997-11-21 1999-07-07 罗姆股份有限公司 半导体装置及其制造方法
CN1239831A (zh) * 1998-06-24 1999-12-29 日本电气株式会社 半导体器件及其制造方法

Also Published As

Publication number Publication date
KR100512835B1 (ko) 2005-09-07
JP4109839B2 (ja) 2008-07-02
CN1399338A (zh) 2003-02-26
JP2002368185A (ja) 2002-12-20
TW541585B (en) 2003-07-11
KR20020092193A (ko) 2002-12-11
US20020180030A1 (en) 2002-12-05
US6861738B2 (en) 2005-03-01

Similar Documents

Publication Publication Date Title
JP5222509B2 (ja) 半導体装置
US8704351B2 (en) Stacked microelectronic assemblies
US7378726B2 (en) Stacked packages with interconnecting pins
KR0147259B1 (ko) 적층형 패키지 및 그 제조방법
JP4072505B2 (ja) 積層型半導体パッケージ
US6208546B1 (en) Memory module
US7875986B2 (en) Semiconductor device
JP6058336B2 (ja) 半導体装置
WO2014134118A1 (en) Microelectronic package with consolidated chip structures
KR20080076010A (ko) 반도체 메모리 장치와 이 장치의 단자 배치 방법, 및 이장치를 구비한 메모리 모듈과 이 모듈의 기판의 단자 및라인 배치 방법
JP4991518B2 (ja) 積層型半導体装置及び積層型半導体装置の製造方法
KR100844969B1 (ko) 전자 디바이스 및 그 제조 방법
CN100524744C (zh) 芯片层叠型半导体装置
JP5288892B2 (ja) スタックモジュール、及びそれを備えるカード及びシステム
JP5547893B2 (ja) 積層型マイクロエレクトロニクスパッケージ
CN208767302U (zh) 半导体装置
US7375418B2 (en) Interposer stacking system and method
US7265446B2 (en) Mounting structure for semiconductor parts and semiconductor device
JP2005072523A (ja) 半導体装置及びその製造方法
JPH0482244A (ja) 半導体集積回路装置およびその配線変更方法
JP2001053217A (ja) 三次元半導体装置用スタックキャリアおよび三次元半導体装置
JP2664720B2 (ja) Ｉｃ実装装置
JPH10284681A (ja) メモリモジュール
KR20000021618A (ko) 스택 메모리
EP3651192A1 (en) Circuit board, method for designing circuit board, and semiconductor device

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090805

Termination date: 20130531