TW531809B - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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Publication number
TW531809B
TW531809B TW090128753A TW90128753A TW531809B TW 531809 B TW531809 B TW 531809B TW 090128753 A TW090128753 A TW 090128753A TW 90128753 A TW90128753 A TW 90128753A TW 531809 B TW531809 B TW 531809B
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TW
Taiwan
Prior art keywords
film
scope
semiconductor device
insulating film
item
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TW090128753A
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English (en)
Inventor
Yoshimi Shioya
Kouichi Ohira
Kazuo Maeda
Tomomi Suzuki
Youichi Yamamoto
Original Assignee
Canon Sales Co Inc
Semiconductor Process Lab Co
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Application filed by Canon Sales Co Inc, Semiconductor Process Lab Co filed Critical Canon Sales Co Inc
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Publication of TW531809B publication Critical patent/TW531809B/zh

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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Description

531809 五、發明說明（1) 本發明係有關於一種半導體 有關於一種適用 、置及其製造方法，特％，丨 適用於防止銅引線層之銅擴散的技術。特別 相關技術說明 度-置（如:⑻等）之操作速 數薄膜”）形成於銅引線層m(參考以下之”低介電常 線層之上作為力：、:薄膜形成於銅引 中，阻障絕緣薄膜暴露出銅引線層。在形成孔洞 成在銅引線層之上，接C ln「Jatlng fllm)進-步地形 ^ ^ ^ 1巴緣薄膜形成於m暗妒從β
'二阻Ρ早絕緣薄膜係為钱刻 膜;:S 層。阻障絕緣薄膜也可作為-同擴散阻膜^刻終止 引線中之金屬銅擴散進入層間絕緣薄膜，，用以防止銅 在習知技術中，氮化矽薄膜（參考以 膜")可以防止銅擴散’被用以作 二4 然而，氮化石夕薄膜因具有高介電常彖4膜 會有降低半導體裝置之操作速度的問題。、約為7) ’ 其他習知薄m較氮切薄膜具有低介 些低介電常數薄膜係利用化= 沈積法（CVD)形成，其反應氣體係為甲基矽 甲烧（CIU，或係為含有機係烧及甲烧之氣體。二二3，)4丄和 於大量的Si-C鍵結形成於低介電常數薄膜中，這、些方法尚 第5頁 2060-4490-PF(N).ptd 531809 五、發明說明（2) 有問題存在。因為Si-C鍵結會增加薄膜中的漏電流 (leakage current)，所以藉由上述方法形成之阻障絕緣 薄膜會有漏電流的問題存在。 發明概述 本發明的目的在提供一種新的半導體裝置及其製造方 法’可以防止銅引線層中之銅擴散。 根據本發明之半導體裝置製造方法，含有任何一氮氣 和一氧化二氮之反應氣體被電漿化（plasmaniZe(J),接著 線層的表面暴露在電漿化反應氣體之下。另外，含有 氣氣和氨氣之反應氣體可能被電漿化以取代上述氣體， 著銅引線層的表面暴露在電漿化反應氣體之下。 根據檢測結果，發現藉由這些電漿程序， 層表面會改良，表層部分具有銅擴散阻礙 旬= t::不”；Γ銅擴散阻礙能力的銅擴散阻 (例如·阻P早絕緣薄膜· 纖潯膜 (氮化係薄膜之類）便 匕的兩介電薄膜 根據本發明，且= 用來防止銅的擴散。 —薄膜、“：的;===薄膜，如了 膜之類…等等。如果高介，SlCH薄膜、SiCNH薄 膜可被使用。 不具有問題，則氮化矽薄 2060-4490-PF(N).ptd 第6頁 531809 五、發明說明（3) 膜=明的鑲嵌（damascene)結構可形成於該含矽絕緣薄 絕緣薄達到此鑲嵌結構n絕緣薄膜形成於含石夕 鋼引線Π 2藏於介層孔中的插塞(plug)電性連接於 緣薄膜：上：f ΐ性連接於插塞的上層引線形成於層間絕 & ' 根據上述，因為銅引線層的表層部分被改声 擴散阻礙的功能，防止銅擴散進二 溥膜與層間絕緣薄膜。 3 7 '、巴緣 層的晨=線層的表層部分未改良前，*果銅引線 氧化薄膜氣Γϊ之下’ ％成於銅引線表面的原生 士认^ a被除去。如果原生氧化薄膜以此方式移除，帘 二弓I線層上的薄膜則;^容易自銅引線 ^ r 分，ίί丄非但沒有改良上述方法中的銅引線層=部 鋼引imt膜可以形成在未經過上述改良程序的 含氨氣:氮氣矛中’形成含石夕絕緣薄膜後，至少包 $絕緣薄膜的表面暴露在上述電聚化製程接：： 栝測結果，發現含梦絕緣镇 —下根據 舉例來說，銅擴散的功能。 薄膜：SiCH ί膜 '薄膜、Si〇薄膜、SiN薄膜' “Ο·
良的含矽絕缘薄膜1 ,H溥膜之類…等等’皆可作為被改 薄膜= = (這㈣Μ，，薄膜、讀H 氣體，經由化學)鍵結的化合物做為反應 鍵結的化ΪΓ;。當具有妙氧(S—) 。物被知用，具有低介電常數並且
2060-4490-PF(N).ptd 第7頁 531809 五、發明說明（4) 的S i 〇 C Η薄膜、S i 0 N C Η薄膜則得以形成。結果，在§丨q c η薄 膜與Si 0NCH薄膜中，不會有習知漏電流增加的問題發生' 且由於類似氮化矽（S i N)薄膜的高介電常數則導致半導體 裝置的操作速度減慢。
所谓的鑲散結構也可以形成在經過此種改良方式之含 石夕絕緣薄膜中為了得到此鑲嵌結構，層間絕緣薄膜形成在 為改良§石夕纟巴緣薄膜表面，接著，在該層間絕緣薄膜與含 石夕絕緣薄膜内部形成介層孔（via hole)。接著，插塞 (plug)被埋入於介層孔（via hole)内，用以電性接觸銅引 線然後，在上方的引線形成於層間絕緣薄膜表面，並與 插塞（Plug)電性連接。根據上述，改良的含矽絕緣薄膜;^ 、仏為防止銅擴散溥膜，可以阻礙銅擴散進入含石夕絕緣薄 膜與層間絕緣薄膜内。 實施例 接下來，配合後續的圖示說明本發明之一最佳實施 例0 實施例1 應用於本發明之半導體製造設備之說明 =1圖係顯示根據本發明之半導體製造設備剖面圖。 來成第圖，編號101標示—反應室（Chambei·) ’用以 ^ '轭仃電漿程序於其中。在上述反應室101中呈 有兩相對應電極，一 τ ^ 肋比 <4 Τ万電極1 0 2與一上方電極1 〇 4，苴形 狀白近乎為直徑約230nm的圓形平面狀。 、
531809 五 發明說明（5) 。上_述下方電極102亦做為一承載檯，用以放置一基底 力ϋ熱器（圖未不）用以加熱上述基底103於上述下方 雷％ π is之上’直到所需要的溫度為止。標號1 0 5係標示一 電源i,、應導線，用以提供該加熱器的電源。 ，士，上述上方電極1 〇 4亦可做為一喷射頭，用以提 仏一氣體進入上述反應室101。 第一咼頻率電源供應器1 07和一第二高頻率電源供 I ^ g :別與上述上方電極104、上述下方電極102相連 =。反應室101内部的氣體可經由提供的高頻率電源川， 1 0 9而被電漿化。 一軋體導入口 108提供在上述上方電極1〇4上，且氣體 可以經由上述氣體導入口1〇8被引導進入上述反應室1〇1。 提供一抽氣口106 ’導入反應室m的氣體 述抽乳口106被抽離，以減低反應室101内部的壓 力0 實施例2 根據本發明之一較佳實施例之半導體褒置製造方法之 呑兄明。 接下來，將說明根據本發明之半導 根據本實施例之半導靜获箸制栌太土版蒗罝I仏万法 <牛導體裝置方法可分為兩種，說明如 卜· 第一方法 首先明配合第2 A圖至第2 C圖說明第一方法。 531809
在此方法中，一基底1〇3放置於上述 第1圖），如第2A圖所示。上述基底1〇3係由一勒極102見 以及位於下方之絕緣薄膜丨丨2，例如為一 & 、5引線層11 0 類，所構成。上述位於下方之曜為膜7,薄膜之 底（圖未示）表面。 、/係形成於矽基 接著，實施一 表面，如第2B圖所 (條件A) 電漿與改良程序於 示。此程序係根據 上述銅引線層1 1 〇的 下列條件A施行。
13·56MHz 0 W (未施加） 380KMHz 150W 基底1 0 3溫度：3 7 5 反應室壓力101 ·· 〇. 5〜le 〇 Tou 第一高頻率電源供應器107之頻率 第一高頻率電源供應器107之功率 第二高頻率電源供應器丨〇 9之缉率 第二高頻率電源供應器1〇9之功 施行時間：3 0秒 、 反應氣流速率：見第1表
2060-4490-PF(N).ptd 第10頁 531809 五、發明說明（7) 第1表 反應氣體 氣流速率（s ccm〉 氮氣 (w2) 氮(w2o〉 氨氣 (WH3) CxHy (1)氪氣（w2) 100 — — — (2〉氮氣(N2)+氧氮(W2〇） 200 100 — — (3)氪氣（W2〉+ 氨氣（WH3) 200 ————— 100 — (4〉11 氣（W2) + CxHy 200 — 100 (5〉氡化二氮（w20〉+ CxHy — 100 — 200 (6)氮氣（w2〉+氡化二氪 100 100 — 100 (W20)+ CxHy
如第1表所示，在此有六種反應氣體。所有的反應氣 體皆存在氮氣或一氧化二氮之其中一者。這些氣體被電浆 化於上述反應室1 0 1内部。在此，反應氣體（3 )中添加氨 氣’反應氣體（4)中添加CxHy (hydrocarbon)。CxHy例如 為CH4和qH2。如果添加CxHy，則在銅引線1 1()的表面會形 成一由CxHy所構成的薄膜。可以預期到，銅引線11〇 ^會 因為此薄膜而在後續步驟中難以被#刻。 如第2圖所示，含矽絕緣薄膜丨丨1形成於銅引線層11〇 之上。此含矽絕緣薄膜111係根據下列條件B以 相沈積（CVD )方法形成。 +
531809 五、發明說明（8) (條件B) 基底103溫度：375。(： 反應室壓力101 : 1. 0 T〇rr 第一向頻率電源供應器丨〇7之頻率：1 3· 56MHz 第一，頻率電源供應器1〇7之功率：〇w (未施加） 第一南頻率電源供應器1 〇 9之頻率：3 8 0 Κ Μ Η z 第一焉頻率電源供應器1 〇 9之功率·· 1 q 〇〜1 & 〇 w 沈積薄膜厚度：1 〇〇nm 反應氣流速率：見第2表 第2表 含碎絕緣薄膜 氣流迷率（seem) 111的種類 HMD SO TMS (Si(CH3〉4) SiB4 w2o wh3 ch4 (1)SiOCH 50 — — — — 100 (2)SiO — 50 — 100 — — (3)SiW — — 50 100 100 — (4)SiONCH 50 — — 200 100 — (5)SiCH — 50 — — — 100 (6)SiCWH — 50 — — 200 100
如第2表所示，含矽絕緣薄膜的種類例如為Si OCH薄 膜、SiO薄膜、SiN薄膜、SiONCH薄膜、SiCH薄膜、SiCNH
2060-4490-PF(N).ptd 第12頁 531809 五、發明說明（9) 薄膜。這些薄膜可以第2表中的氣體結合而形成。本發明 可，適用於任一上述薄膜。值得注意的是，當薄膜的種類被 以”SiXYZM表示時，則代表此薄膜至少包含Si元素、X元 素、Y元素、Z元素。 在苐2 表中 ’ HMDSO(hexamethyldisiloxane: (Sl(CH3)3)2〇))在室溫（20 °C )下係為液體。液態HMDS0的 流速可以由液態質流儀控制，接著，液態HMDS0經過加熱 ，汽化’且導入反應室1〇。或者，液態HMDS〇汽化後，氣 態HMDSO的流速可以藉由高溫質流控制儀調整（未圖示 )’接著再供給汽化HMDSO進入反應室101。HMDSO汽化後 可以達到條件B之HMDSO流速。 特別的是，藉由條件B之下使用HMDSO所形成之SiOCH 的介電常數大約為〇·4，較SiN薄膜的介電常數為低。再 者’當使用HMDSO時，因為HMDSO中的Si與0相鍵結而形成 Si-0 - Si(silicon)鍵結，所以SiOCH中之Si-C鍵結便減 少。結果，具低介電常數之SiOCH及成為可以抑制漏電流 的薄膜。使用HMDSO形成Si 0NCH時也會發生同樣的情形。 HMDSO是具有矽氧（ s i 1 ο X a n e )鍵結的化合物，但當任 何下列具有矽氧鍵結之化合物用以取代HMDSO時，亦具有 相似的優點。 ' OMCTS(octamethy ldisi loxane : (Si (CH3 )2 )4 04 ) HEDS(hexaethy ldisi loxane ·· (Si (C2H5)3)20) TMDSCtetramethy ldisi loxane : (S i H(CH3 )2 )2〇) TEDS(tetraethy ldisi loxane : (SiH(C2H5)2)2〇)
2060-4490-PF(N).ptd 第13頁 531809 五、發明說明（10) TMCTS(tetramethylcyclotetrasiloxane：(SiH(CH ) 4〇4) 3 TECTS(tetraethylcyclotetrasiloxane:(SiH(C2H5) 4〇4) 25 如果使用任一上述化合物，則可形成可抑制漏電流之 低介電常數含矽絕緣薄膜111。 再者，使用第2表中之有機矽烷（tetramethylsilane: Si(CH3)4))形成SiO薄膜、SiCH薄膜以及SiCNH薄膜，但亦 可用其他有機矽烷（例如：三甲基矽烷（SiH(CH3)3)、二曱 基矽烷（81112((：113)2)以及一曱基矽烷（31113((：113)))取代 TMS ° 接著，檢驗銅由銅引線層1 1 〇擴散至含矽絕緣薄膜丨i 1 的結果，且請參照第圖與第4圖之說明。特別的是，見第 表中之（1 )利用2做為製程氣體並且利用s i 0CH薄膜（見 第表之（1 ))做為含矽絕緣薄膜1 11。 第3圖係顯示形成含矽絕緣薄膜後之各元素含量之 SI MS (二次離子質量分析儀）分析結果。其中檢測銅濃度 與含矽絕緣薄膜111自表面之深度之關係。第3圖之橫座標 以線性刻度標示絕緣薄膜1 1 1由表面起之深度，左側之縱 座標表示銅濃度（每lcc之原子數目；atoms/cc)之log 值。亦檢測薄膜中矽（S i )與碳（C)之二次離子強度 (cts/sec)。左側之縱座標表示矽（si)與碳（C)之二次離子 強度（cts/sec)之log 值。 第3圖中’標示於元素左側之數值表示該元素之原子
2060-4490-PF(N).ptd 第14頁 531809 五、發明說明αυ 序。 第4圖係表示第3圖之含矽絕緣薄膜丨丨1檢驗後，再於 真空下退火50 0 °c、 4小時，各元素含量之SIMS (二次離 子質量分析儀）分析結果。其檢測方式與第3圖之方式相 似。 注意第4圖中深度6〇〜80nm之銅濃度，其顯示曲線在此 區域之斜率較為陡峭。即表示銅自銅引線1 1 〇擴散進入絕 緣薄膜111之量較少。 並且，在中間區間（深度約2 0〜6 0 nm )含矽絕緣薄膜 111所含的銅含量非常少。特別的是，本發明可以使得中 間區間之薄膜之銅含量少於1 〇ι7。 上述論點表示實施退火處理可以防止銅擴散。 接著，為了進一步確定N2電漿製程的影響，將參考第 5圖與第6圖說明未實施N2電漿製程的情況。第5圖係顯示 形成含矽絕緣薄膜111後，未經過N2電漿製程，其各元素 之SIMS分析結果。即為為執行第B圖，就直接執行第2C 圖，並且，第圖係顯示第5圖之含矽絕緣薄膜111進一步於 真空、500 °C下進行退火4小時後，各元素之SIMS分析結 果。 第圖與第6圖之橫座標係顯示絕緣薄膜111由表面算起 之深度（nm)。左側之縱座標表示銅濃度（每lcc之原子數 目；a t 〇 m s / c c )之1 〇 g值。亦檢測薄膜中石夕（S i)與碳（C)之 二次離子強度（c t s / s e c)。左側之縱座標表示石夕（S i)與碳 (C)之二次離子強度（cts/sec)之log值。
2060-4490-PF(N).ptd 第15頁 531809 五、發明說明（12) 比較第圖與第6圖之銅濃度，可以瞭解 由退火擴散進入含矽絕緣薄膜丨丨丨。 、、之銅藉 另一方面，比較第4圖（實施N電漿製程）血 (未實施電漿製程），可以說明N2電漿製裎的、与圖 發現第4圖之銅濃度低於第6圖之銅濃度。 〜θ 。可 根據以上第圖至第6圖之說明，發現當納 表面暴露在條件Α與電漿之下，銅引線層丨丨〇的、、、γ 1 0的 改良為銅擴散阻礙層。發明人推測銅引線層i 部分破 分可施以氮化電漿處理，因此可於表層部分、的^表層部 成之薄膜，以做為銅擴散阻礙層。 /成虱化銅組 這表不銅引線層1 1 0本身具有阻礙銅擴散 此，根據第一方法，便不需要形成銅擴散、％。因 110的表面以防止銅擴散。因此，第一方法中部於•銅引線層 習知例如為SiN之高介電常數薄膜，藉其提 ς =用 的能力。 疋口丨且礙鋼擴散 接著，請參照第j圖至第7C圖說明第二方法。 如第7圖所TF，-基底103中設置一低電極1〇2 i基底1G3係由形成銅引線層110於絕緣薄膜⑴之上 \斤構成。下分絕緣薄膜112形成餘一之基底之上（圖未= 接著，請參照第7B圖，厚度約為1〇〇11111之含矽絕 膜m形成於銅引線層11()之上，且係根據第—方法之停專 B以化學氣相沈積法形成。 條件
531809 五、發明說明（13) 接著，請參照第7C圖，含矽絕緣薄膜1 1 1的表面根據 下列條件利用電漿製程進行改良。 (條件C) 基底103溫度：375 °C 反應室壓力101 : 0· 5〜6. 0 Torr 第一高頻率電源供應器1 〇 7之功率：〇 W (未施加） 第二高頻率電源供應器109之頻率：380KMHz 第二高頻率電源供應器丨〇 9之功率：1 5 〇W 施行時間：3 0秒 反應氣流速率：見第3表 3表 反應氣體 氣流速率（s ccm) (1〉氨氣（ϊιη3) 100〜300 (2〉氮氣（w2〉 100〜300 (3) —氡化二氮（w2〇） 100^300 第3表中可使用NH3、&或\〇知其中之一或其組合為製 程氣體。
雖然條件C只有使用第二高頻率電源供應丨〇 9，第一高 頻率電源供應107也可以與第二高頻率電源供應1〇9 一起使 用。或者，第一高頻率電源供應1〇7可以單獨使用。 接著，檢驗銅由銅引線層110擴散至含矽絕緣薄膜m
531809 五、發明說明（14) ___ 的結果，且清參照第圖斑笛只闽 表中之（"利用做為製說明。特別的是’見第2 ΓΓ緣請"…氨氣 第8圖係顯示形成含矽頌 450 1 4小時，各元素13=111後’於真空下退火 儀）分析結果。此檢測方、去里斑 S (一次離子質量分析 檢測銅濃度與含石夕絕緣薄;μ檢測相同。其中 同第-方法，亦檢測薄自表，，深度之關係。如 度（cts/sec)。 中⑽D與碳⑹之：次離子強 左側之縱座標表示石夕（u你山，、 (cts/sec)之lQg值。（0與以）之二次離子強度 第8圖顯示銅擴散輕微。比較第6圖（為實 製。與第8圖（實施）NH3電漿製程，可以發現 : 銅濃度較低。 < 這表示含矽絕緣薄膜丨丨丨受到改良可以具有鋼擴散阻 礙的功能。 在此實施例中，含矽絕緣薄膜1U可以藉由含有〇D 之反應氣體（見條件B)使用Si〇CH。因此，不僅薄膜介 常數較低（約為4 ) ’並且可以抑制漏電流。 發明人確實量測漏電流。第9圖顯示測量漏電流之剖 面圖。標號202顯示一接地之P型矽基底。接著，含矽絕1緣 薄膜ill在條件B之下形成於p型矽基底2〇2。201表示一采 探針’用以測試含矽絕緣薄膜之電壓。
2060-4490-PF(N).ptd 第18頁 531809 五、發明說明（15) 第1 〇圖與第11圖顯示其測量結果。這些圖中，橫座標 顯示一應用於汞探針201 (見第9圖）之電場強度 (MV/cm)。橫座標上之負號表示應用於汞探針織電壓為負 值。坐坐標顯示漏電流。 第1 0圖係顯示當絕緣薄膜111形成後立即實施NHs電漿 製程（條件C之下），其絕緣薄膜1 11之漏電流。 另一方面，第11圖係顯示當絕緣薄膜實施電漿製 程後，再進行退火，其絕緣薄膜之漏電流。退火處理係於 真空下4 5 0 X：，進行4小時。 比較第1 0圖與第11圖，可以發現絕緣薄膜丨丨1實施叫 $漿製程在執行退火處理前後之漏電流沒有明顯差異。注 意第1 0圖與第1丨圖之曲線A，發現當實施退火處理（第丄丄 圖）後，曲線A向左側位移（電場較大區域）。因此，可 以預期退火處理可以改善漏電流情形。 如前所述，根據本方法，銅的擴散可以藉由一相較於 電常數之含矽絕緣薄膜lu而加以防止。因 二二電常數較習知為低，因此絕緣薄膜便不 細作速度下降的問題。 ’ ^灰 =意的是’第一與第二方法可以獨立或灶 鉍。右結合時施例一與第二方瑞、，，口 口二 點。 灯j獲付上述相同之優 (3 )說明移除銅引線層丨丨〇表面之 、 上述第一與第二方法可在移除銅線 ㈢之方法 生氧化薄膜後再施行。可以防止含：；：由表面之原 、巴緣溥膜由鋼引線層
531809 發明說明（16) 剝落。此實施例中， 膜，銅引線層的表面 漿製程條件。 為了移除鋼引線層11 〇之原生氧化薄 被施以NH3電漿處理。條件係為NH3電 (條件C) N H3 流速：5 〇 〇 s c c m 基底103溫度：375 °C 反應室壓力101 : 6. 〇 T〇rr
第一尚頻率電源供應器1 〇7之頻率：1 3. 56MHz 第一高頻率電源供應器107之功率：400W 第二高頻率電源供應器109之功率：〇MHz(未施加） 施行時間：1 〇秒 實施例3 說明本發明之應用實施例 接下來將舉例說明本發明之應用。本發明應用於用』 形成銅引線層之鑲嵌方法。第12圖至第12H圖係為本發明 應用於鑲嵌方法之剖面圖。 首先，請參照第12A圖，提供一基底1〇3。基底1〇3係 由銅引線層（下方引線）丨丨〇所構成，銅引線層設置於材 質例如為Si〇2之下方絕緣薄膜112之上。雖然圖未示，下 方絕緣薄膜1 1 2形成於石夕基底表面。 ，著:請參照第12B圖，為了移除銅引線層11()表面 原生氧化薄膜，其表面將施加㈣3電漿。nh電漿製程的條
531809 五、發明說明（17) 件如條件D。 接著，請參照第1 2C圖，移除原生4 # 線層11〇表面被施以電漿處理。其實施行條= 之條件a。銅弓丨線層η。之部分表面藉由電聚=-方法 且這些表面具有防止銅擴散的功能。 、矛被文良 線声二著之:參二第12D圖’形成含石夕絕緣薄膜111於銅引 線層110之上。含矽絕緣薄膜ηι係在條件3下 在本發明中，含矽絕緣薄膜111係為塊狀，柏y f^ 之：並且，因為銅引線層表3原= 易驟中被移除’塊狀絕緣薄膜… 如同第二方法之說明，形成堍妝 件C，將塊狀絕緣薄膜的表面暴成露免於狀電= 下膜後在:條 中亦可以除去第12C圖之電漿製程。但是 = 緣薄膜111具有防止銅擴散的功能，所以 進入内i絕緣薄膜除緣薄说膜不可能防止銅擴散 簿膜1Ι3Ί參照第12Ε圖’形成低介電常數之内層絕緣 2 3愉快狀絕緣薄膜⑴之上，且一保護薄膜ιΐ4形成 於上。内層絕緣薄膜113可以為習知之FsG(f =6)或多孔性之Μ薄膜。厚度薄、高密度之 Ϊ I ί具有雜質之矽氧薄膜）可以做為保護薄膜 。 沒有保護薄膜114，内層絕緣薄膜113的品質會 被光阻的製程氣體或㈣言免置於内層絕緣薄膜下方且使絕
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緣薄膜之低介電常數退化之塊狀絕緣薄膜丨丨1之蝕刻氣體 所改變。如果沒有上述問題，則可以免除保護薄膜114。 接著，請參照第1 2 F圖，形成一光阻1 1 5於保護薄膜 1 1 4之上’再利用微影製程形成一開口 1 1 & a於光阻11 $之 中。接著，藉由反應性蝕刻形成内層絕緣薄膜丨丨3與保護 嶒1 1 4形成一經過開口 1 5a達到塊狀絕緣薄膜丨丨}之開口 113a。 · 在此蝕刻中，可以利用混合氣體⑼“⑶匕做為蝕刻氣 體。塊狀絕緣薄膜1 1 1具有對這些氣體的抗蝕刻能力。換 句話說，塊狀絕緣薄膜可以做為蝕刻終止層。 接著’請參照第12G圖，去除光阻115後，藉由蝕刻塊 狀絕緣薄膜111形成一開口11 la，經由開口113&露出銅引 線層11 0表面。此蝕刻係利用反應性離子蝕刻進行。蝕刻 氣體係混合CFJCHF3，用以蝕刻絕緣薄膜11 3，但蝕刻過程 中氣體混合比例會改變。因為銅引線層丨丨〇對於此蝕刻氣 體具有抗蝕刻能力，所以不會被蝕刻。根據此步驟，一介 層孔可利用開口 111 a與11 3a定義出來。 接著’請參照第1 2圖，一晶種層11 7利用濺鍍製程形 成於介層孔11 6的侧壁與保護薄膜1 1 4之上。晶種層係銅所 構成。然後，藉由供給電流至晶種層丨丨7上，以形成一第 一電解銅板薄膜118。接著，高度較介層孔116高的第一電 解銅板薄膜118藉由CMP移除。根據此步驟，得到以埋藏於 介層孔116之電解銅板薄膜118做為插塞。 最後，藉由再度供給一電解電流於晶種層丨丨7與第一
531809 五、發明說明（19) 電解銅板薄膜1 1 8，以形成一第二電解銅板薄膜（上引線 )119 〇 接著，上述步驟達成一結構，此結構中銅引線層（下 弓丨線）11 0與電解銅板薄膜（下引線層）11 9倍内層絕緣薄 膜11 3分隔開來，且藉由插塞電性連接。 如前所述，當銅引線層（下引線）11 〇的表面根據上 述條件A施以電漿製程，銅引線層（下引線）丨丨〇的表面被 改良成為銅擴散阻礙層。結果，當塊狀絕緣薄膜形成於銅
引線層（下引線）11 〇之上，便不需要採用習知之具高介 電常數SiN薄膜。 第2表中所列的薄膜皆可適用。其中，SiOCH薄膜、 SiONCH薄膜皆使用HMDS〇，可以抑制漏電流且具有較低介 電常=(約為4)。因此，可使得元件具有高操作速度。 綜上所述，根據本發明之半導體裝置之製造方法，電 漿化製程氣體係由N2或％〇其中之一或其組合所構成，使的 表面暴露於其下。含石夕絕緣薄膜被改良成銅擴散 阻礙薄膜。 如果含矽絕緣薄膜係利 烧鍵結之化合物的反應氣體 可抑制漏電流。結果，此種 電流增加以及高介電常數（ 速度慢的問題。 用化學氣相沈積法使用具有矽 丄例如：具有低介電常數，且 s石夕絕緣薄膜不會有習知之漏 例如SiN )導致的半導體操作
本發明雖以較佳實施例揭露 本發明的範圍，任何熟習此 上，然其並非用以限定 、支藝者，在不脫離本發明之
531809
2060-4490-PF(N).ptd 第24頁 531809 圖式簡單說明 ----—----- 第1 i %供圖係顯示根據本發明之一最佳實施例之半導體製 仏汉壻剖面圖。 第2 A圖至第2 c圖係顯示根據本發明之一第一方法最 貫施例之丰I ^ 1 〜千導體裝置製程剖面圖。 笛 c\ __ 圖係顯示根據本發明之第一方法之一最佳實施 {歹丨J ， B石夕絕緣薄膜形成後，立即經由S I MS分析其薄膜中 各70素含量分析之結果。 一第4圖係顯示根據本發明之第一方法之一最佳實施例 之-合石夕絕緣薄膜在真空中經由5 〇 〇 〇C退火處理4小時後， 再經由SIMS分析其薄膜中各元素含量分析之結果。 第5圖係顯示根據本發明之第一方法之一最佳實施 例’當未實行一氮氣電漿程序下，一含矽絕緣薄膜形成 後’立即經由S I MS分析其薄膜中各元素含量分析之結果。 第6圖係顯示根據本發明之第一方法之一最佳實施 例’當未經過一氮氣電漿程序處理之含矽絕緣薄膜行程 後’在真空中經由5 〇 〇 °c退火處理4小時後，再經由s丨MS分 析其溥膜中各元素含量分析之結果。 第7A圖至第7C圖係顯示根據本發明之一第二方法最佳 實施例之半導體裝置製程剖面圖。 第8圖係顯示根據本發明之第二方法之一最佳實施例 之一含矽絕緣薄膜在真空中經由5 〇 〇它退火處理4小時後， 再經由S I MS分析其薄膜中各元素含量分析之結果。 第9圖係顯示根據本發明之第二方法之一最佳實施例 之含石夕絕緣薄膜，其量測漏電流之結構剖面圖。
2060-4490-PF(N).ptd 第25頁 531809 圖式簡單說明 第1 〇圖係顯示根據本發明之第二方法之一最佳實施例 之一含矽絕緣薄膜形成後，立即經由一氨氣電漿程序處 理，其漏電流的量測結果。 第1 1圖係顯示根據本發明之第二方法之一最佳實施例 之一含石夕絕緣薄膜形成後，立即經由一氨氣電漿程序處理 並且退火處理，其漏電流的量測結果。 第1 2 A圖至第1 2 Η圖係顯示本發明應用在鑲嵌方法之製 程剖面圖。 符號說明 _ 101反應室； 102下方電極； 104上方電極； 103基底； 1 〇 5電源供應導線；丨〇 7第一高頻率電源供應器； 109第二高頻率； 110銅引線層； 111含矽絕緣薄膜；11 2絕緣薄膜； 2 0 2 Ρ型矽基底； 2 0 1汞探針； II 3内層絕緣薄膜；11 4保護薄膜； 115 光阻； 113a 開口； III a開口； 11 6介層孔； 11 7晶種層； 11 8第一電解銅板薄膜； 119第二電解銅板薄膜。

Claims (1)

  1. 、、申請專利範圍 1電；導體裝置之製造方法，包括： 其中之—老製程氣體，其中上述製程氣體含有N2或\0知 有或其組合； 漿製程氣2弓丨線層表面，將銅引線層表面暴露於上述電 阻礙層。 下，使上述銅引線層表面部分成為一銅擴散 法 其中t =專利範圍第1項所述之半導體裝置之製造方 3.如由=製程氣體中加入碳氫化物（1^(11'0(^1^(^)。 法 复中μ =專利範圍第1項所述之半導體裝置之製造方 " 上述碳氫化物係為CH4或(：211 。 電：：半導體裝置之製造方法：包括： 知其中Ϊ-= 上述製程氣體含有化或nh3 < 者或其組合；以及 述電毁f鞋Γ =線層表面，將上述銅引線層表面暴露於上 擴散阻U體之下M吏上述銅引線層表面部分成為-銅 法 5苴ί ί請專利範圍们項所述之半導體裝置之製造方 ^I在改良上述銅引線層之前更包括： /、路上述銅引線層表面於一ΝΗ3電漿之下。 法 直I申明專利範圍第1 2項所述之半導體裝置之製造方 ""在改良上述銅引線層之後更包括： 形成一含石夕絕緣薄膜於上述銅引線層之上。 法
    1 ^如申睛專利範圍第6項所述之半導體裝置之製造方 2 其中更包括： 531809 六、申請專利範圍 ___ 電漿化一製程氣體’上述 知其中之一者； 表長亂體至少含有NH3、〜或 於形成含矽絕緣薄膜後， 述電漿化製程氣體。 、 迷3矽絕緣薄膜於上 8·如申請專利範圍第6 法，其中更包括： 員所逑之+導體裝置之製造方 =-=絕緣薄膜於上述含石夕絕緣薄膜之上； 膜内〔層孔於上述切絕緣_與上述内層絕緣薄
    引線;里=塞，用以電性連接至上述界層孔内之上述銅 之上引線層’用以電性連接至内層絕緣薄膜上方 ^ 一種半導體裝置之製造方法，包括： 形成一含矽絕緣薄膜於上述銅引線層之上； 電漿化一製程氣體，其中上述製程氣體含有N 〇、N NH3知其中之一者或其組合；以及 2 2〆 改良含石夕絕緣薄膜，將上述含石夕絕緣薄膜暴露於上 述電漿製程氣體之下。
    、10·如申請專利範圍第9項所述之半導體裝置之製造方 法’其中在改良上述含石夕絕緣薄嫉之前更包括·· 暴露上述銅引線層表面於^nH3電漿之下。 11·如申請專利範圍第9項所述之半導體裝置·之製造方 法，其中更包括··
    531809 六、申請專利範圍 ' 在改良上述含石夕絕緣薄膜之後，形成一内層絕緣薄膜 於上述含矽絕緣薄膜之上； ' 形成一介層孔於上述含;g夕絕緣薄膜與上述内層絕緣薄 膜之上； ~ 埋入一插塞’用以電性連接至上述界層孔内之上述銅 引線層；以及 形成一上引線層，用以電性連接至内層絕緣薄膜上方 之上述插塞。 1 2.如申請專利範圍第丨丨項所述之半導體裝置之製造 方法’其中上述内層絕緣薄膜係由FSG薄膜或多孔性s i 〇2 薄膜。 I 1 3·如申請專利範圍第6項或第9項所述之半導體裝置 之製造方法，其中上述含矽絕緣薄膜係由si〇CH薄膜、Si 〇 薄膜、SiN薄膜、SiONCH薄膜、siCH薄膜、SiCNH薄膜其中 之一者所構成。 1 4·如申請專利範圍第丨3項所述之半導體裝置之製造 方法’其中上述S i 0CH薄膜係利用化學氣相沈積使用—含 有矽氧烷（si loxane)鍵結之化合物做為反應氣體所形成。 1 5 ·如申請專利範圍第丨3項所述之半導體裝置之製造/ 方法:其中上述Si 0NCH薄膜係利用化學氣相沈積使用/含 有石夕氧燒（si loxane)鍵結與之化合物做為反應氣艨戶斤 形成。 1 6 ·如申請專利範圍第丨4項所述之半導體裝置之製造 方法，其中上述化合物係由HMDS0( (Si (ch3)3)2〇)、
    2060-4490-PF(N).Ptd 第29頁 531809 六、申請專利範圍 _ 0MCTS((Si (CH3)2)4〇4) ^ HEDS((Si(C2H5)3)20) ^ TMDS((SiH(CH3)2)2〇) ^ TEDS( (SiH(C2H5 )2 )20) ^ TMCTS((SiH(CH3)4〇4)、TECTS((SiH(C2H5)4〇4)其中之一 構成。 贫所 1 7 ·如申請專利範圍第1 5項所述之半導體裝置之製造 方法’其中上述化合物係由HMDS0((Si(CH3)3)20)、 OMCTS((Si(CH3)2)4〇4)、HEDS((si(C2H5)3)2〇)、 TMDS((SiH(CH3)2)2〇) > TEDS ((S i Η (C2 H5 )2 )20 ) ' TMCTS((SiH(CH3)4〇4)、TECTS((SiH(C2H5 )4 04 )其中之一者 構成。 1 8·如申請專利範圍第丨3項所述之半導體裝置之製造 方法，其中上述S i Ν薄膜係利用化學氣相沈積使用一含有 S i H4與N2 0之反應氣體所形成。 1 9·如申請專利範圍第丨3項所述之半導體裝置之製造 方法，其中上述S i 0薄膜係利用化學氣相沈積使用一含有 有機矽烧（organic silane)之反應氣體所形成。 2 0 ·如申請專利範圍第1 3項所述之半導體裝置之製造 方法，其中上述S i 0薄膜係利用化學氣相沈積使用一含有 有機石夕烧（organic silane)之反應氣體所形成。 21 ·如申請專利範圍第1 3項所述之半導體裝置之製造 方法，其中上述SiCH薄膜係利用化學氣相沈積使用一含有 有機矽烷（organic si lane)與碳氫化合物（hydrocarbon) 之反應氣體所形成。 2 2.如申請專利範圍第13項所述之半導體裝置之製造
    2060-4490-PF(N).ptd 第30頁
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