TW531769B - Semiconductor device, method of manufacturing the same and method of designing the same - Google Patents

Semiconductor device, method of manufacturing the same and method of designing the same Download PDF

Info

Publication number
TW531769B
TW531769B TW090124046A TW90124046A TW531769B TW 531769 B TW531769 B TW 531769B TW 090124046 A TW090124046 A TW 090124046A TW 90124046 A TW90124046 A TW 90124046A TW 531769 B TW531769 B TW 531769B
Authority
TW
Taiwan
Prior art keywords
pattern
aforementioned
area
layer
masking
Prior art date
Application number
TW090124046A
Other languages
English (en)
Chinese (zh)
Inventor
Hiroki Shinkawata
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW531769B publication Critical patent/TW531769B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
TW090124046A 2001-01-10 2001-09-28 Semiconductor device, method of manufacturing the same and method of designing the same TW531769B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001002331A JP2002208676A (ja) 2001-01-10 2001-01-10 半導体装置、半導体装置の製造方法及び半導体装置の設計方法

Publications (1)

Publication Number Publication Date
TW531769B true TW531769B (en) 2003-05-11

Family

ID=18870861

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090124046A TW531769B (en) 2001-01-10 2001-09-28 Semiconductor device, method of manufacturing the same and method of designing the same

Country Status (6)

Country Link
US (1) US6690045B2 (ko)
JP (1) JP2002208676A (ko)
KR (1) KR100417366B1 (ko)
CN (1) CN1187812C (ko)
DE (1) DE10147365A1 (ko)
TW (1) TW531769B (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4136684B2 (ja) 2003-01-29 2008-08-20 Necエレクトロニクス株式会社 半導体装置及びそのダミーパターンの配置方法
US6693357B1 (en) 2003-03-13 2004-02-17 Texas Instruments Incorporated Methods and semiconductor devices with wiring layer fill structures to improve planarization uniformity
KR100546354B1 (ko) * 2003-07-28 2006-01-26 삼성전자주식회사 원하는 분석 위치를 용이하게 찾을 수 있는 반도체 소자
JP3933619B2 (ja) * 2003-10-10 2007-06-20 沖電気工業株式会社 研磨工程の残存膜厚判定方法および半導体装置の製造方法
JP4401874B2 (ja) 2004-06-21 2010-01-20 株式会社ルネサステクノロジ 半導体装置
KR101084632B1 (ko) 2004-12-29 2011-11-17 매그나칩 반도체 유한회사 반도체소자
US7224069B2 (en) * 2005-07-25 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structures extending from seal ring into active circuit area of integrated circuit chip
JP4630778B2 (ja) * 2005-09-15 2011-02-09 シャープ株式会社 アライメントマークの形成方法
JP4302720B2 (ja) * 2006-06-28 2009-07-29 株式会社沖データ 半導体装置、ledヘッド及び画像形成装置
JP2009027028A (ja) * 2007-07-20 2009-02-05 Toshiba Corp 半導体装置の製造方法
JP4735643B2 (ja) * 2007-12-28 2011-07-27 ソニー株式会社 固体撮像装置、カメラ及び電子機器
JP2010267933A (ja) 2009-05-18 2010-11-25 Elpida Memory Inc ダミーパターンの配置方法及びダミーパターンを備えた半導体装置
US9287252B2 (en) * 2011-03-15 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor mismatch reduction
JP6054596B2 (ja) * 2011-05-31 2016-12-27 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体装置および半導体装置設計方法
US9594862B2 (en) 2014-06-20 2017-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating an integrated circuit with non-printable dummy features
CN108140668B (zh) * 2015-07-03 2021-11-19 应用材料公司 半导体器件
JP6798318B2 (ja) * 2017-01-05 2020-12-09 富士通株式会社 設計支援装置、設計支援方法、および設計支援プログラム
KR20180102866A (ko) * 2017-03-08 2018-09-18 에스케이하이닉스 주식회사 심볼 간섭 제거 회로
CN109755223A (zh) * 2017-11-06 2019-05-14 联华电子股份有限公司 半导体结构及其制造方法
CN109461717A (zh) * 2018-10-15 2019-03-12 上海华虹宏力半导体制造有限公司 一种晶圆及其形成方法、等离子体裂片方法
US11282798B2 (en) * 2020-02-20 2022-03-22 Globalfoundries U.S. Inc. Chip corner areas with a dummy fill pattern
CN118073326A (zh) * 2024-04-18 2024-05-24 深圳市辰中科技有限公司 一种晶圆的切割道结构及光罩

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61113007A (ja) 1984-11-08 1986-05-30 Nippon Telegr & Teleph Corp <Ntt> 光フアイバ
JP2724828B2 (ja) 1987-07-02 1998-03-09 国際電信電話株式会社 光ファイバ
US5715346A (en) 1995-12-15 1998-02-03 Corning Incorporated Large effective area single mode optical waveguide
JP3638778B2 (ja) 1997-03-31 2005-04-13 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
JP3488606B2 (ja) 1997-10-22 2004-01-19 株式会社東芝 半導体装置の設計方法
JP2000223492A (ja) 1999-01-29 2000-08-11 Nec Corp 多層配線を有する半導体装置の製造方法
JP3333993B2 (ja) * 1999-04-27 2002-10-15 前田工繊株式会社 動的荷重吸収用補強盛土の構築方法及び動的荷重吸収用補強盛土

Also Published As

Publication number Publication date
DE10147365A1 (de) 2002-07-18
US20020089036A1 (en) 2002-07-11
KR20020060561A (ko) 2002-07-18
JP2002208676A (ja) 2002-07-26
CN1363954A (zh) 2002-08-14
US6690045B2 (en) 2004-02-10
KR100417366B1 (ko) 2004-02-05
CN1187812C (zh) 2005-02-02

Similar Documents

Publication Publication Date Title
TW531769B (en) Semiconductor device, method of manufacturing the same and method of designing the same
JP3229278B2 (ja) ダマシン金属回路パターンの平坦化方法
US9865545B2 (en) Plurality of substrates bonded by direct bonding of copper recesses
US6782512B2 (en) Fabrication method for a semiconductor device with dummy patterns
TW396524B (en) A method for fabricating dual damascene
JP4982921B2 (ja) 半導体装置及びその製造方法
JPH06326065A (ja) 半導体デバイスおよび製造方法
JP2002110908A (ja) スパイラルインダクタおよびこれを備える半導体集積回路装置の製造方法
JP2000286263A (ja) 半導体装置及びその製造方法
US10692733B2 (en) Uniform back side exposure of through-silicon vias
CN107808882A (zh) 半导体集成电路结构及其制作方法
US20050127496A1 (en) Bonding pads with dummy patterns in semiconductor devices and methods of forming the same
JP2006135107A (ja) 半導体装置およびその製造方法
US6833622B1 (en) Semiconductor topography having an inactive region formed from a dummy structure pattern
TW457571B (en) Fabrication process for dishing-free CU damascene structures
KR100816247B1 (ko) Mim 캐패시터 및 그 제조방법
JPH0870101A (ja) 集積回路コンデンサ構造およびその製造方法
US20230197603A1 (en) Electronic devices with a low dielectric constant
Nelson Optimized pattern fill process for improved CMP uniformity and interconnect capacitance
TW425667B (en) Selectivity reduction method to different pattern densities for inter-metal dielectric during planarization processing
TW436999B (en) Method of improving surface planarity of chemical-mechanical polishing operation by forming shallow dummy pattern
TW200400562A (en) Polishing of conductive layers in fabrication of integrated circuit
TW548735B (en) Dummy pattern for application on CMP process
KR100829361B1 (ko) 자기 메모리 소자의 제조방법
JP5582154B2 (ja) 半導体装置及び半導体装置の製造方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees