TW548735B - Dummy pattern for application on CMP process - Google Patents

Abstract

This invention provides a method of preventing cracks on the film layer to be polished during CMP process. The CMP process is performed on a layer of a semiconductor substrate, which includes an active region and a dummy pattern region. The dummy pattern is used to uniformly adjust the pattern density distribution of the layer. This invention employs a dummy pattern with dummy shapes selected from groups formed by polygons with an included angle greater than 90 degrees, ellipses and circles.

Description

548735

FIELD OF THE INVENTION The present invention relates to a method of a chemical mechanical polishing process (CMp) and an integrated circuit made by the method, especially a method of changing the shape of du_ies of a dummy pattern. Avoiding chemistry: the method of cracking in the two-type grinding system and the integrated circuit made by the method. 〆Background of the invention: According to 'With the rapid development of semiconductor technology, in the development and design of ultra large integrated circuits (ULSI), in order to meet the design trend of high density integrated circuits', the size of various components has been reduced to sub-micron the following. After entering the generation with line widths smaller than 0.18 microns, the conditions of various processes are more stringent than in the past, which has also led to unprecedented difficulties encountered in carrying out related semiconductor processes, and the complexity of the processes has continued to increase. Chemical Mechanical Polishing (CMP) is a typical method in the current semiconductor process that can achieve comprehensive ^ globalization (global Pianarizati), using the principle of mechanical polishing 'with appropriate chemical additives The fluctuating contour (fr0f 1 le) of the wafer surface is smoothed. If various process parameters are properly controlled, CMP can provide a flatness of more than 94% for the polished surface.

Page 4 548735 V. Description of the invention (2)-: The chemical mechanical polishing process usually uses a circular polishing table to place a polishing pad and then a wafer carrier ( The wafer carrier) puts the wafer under pressure on a polishing pad provided with a slurry, and achieves the effect of chemical mechanical polishing by the relative movement between the wafer and the polishing pad. However, because the polishing pad used has considerable flexibility, during the chemical mechanical polishing process, the flatness of the polished film layer of the wafer after polishing will be affected by the surface shape of the polished film layer, resulting in a surface. The concave shape causes a dishing effect. In other words, when the pattern density on the plane of the film layer to be polished is unevenly distributed, the polishing rate of the CMP process will be different in these plane regions with different pattern densities, which will cause the above-mentioned disc effect. Currently, The solution is to add a dummy pattern to the polished film layer to adjust the pattern density distribution on the plane of the wafer layer to improve the effect of the CMP process. For some reason, this figure of the corner ee layer. } Angle (In P, if the display is straight away and so on, the 90th grade should be peeled, but the shape C should be the surface shape of the layered crystal pattern, usually a square or rectangular integrated circuit chip. The top view of the inner metal wiring layer is enlarged from the corners 2 of these image-like patterns 1 are sharp right angles. When under pressure, for example, in the grinding platform of the CMP process, the stress at the landing becomes very high. Not only makes the trench filler near the corner of the pattern easy to ling while grinding), but also causes the material of the wafer metal dielectric layer (IMD) where the crystal pattern is located, as shown in Figure 2.

Page 5 548735 V. Description of the invention (3) One of the cracks in the metal wiring layer is the current technology in order to reduce the delay ::: Big picture, especially the material 14 of the metal dielectric layer tends to be selected Low ;; material: the mechanical properties of the electric material are so weak that it is easier to interpose the inner metal dielectric material M where the pattern 11 is located, which occurs more brittle in the material, at the sharp corners of these patterns Change the place ... " ㈣points). At the point of Xiao Luo, the potential cracking point has become the method used by the semiconductor industry in pursuing comprehensive flattening because of the chemical mechanical polishing process. Dong Shi's current semiconductor process has extremely high utilization value, and the material of the dielectric layer The choice is increasingly towards low dielectric materials, because,

Therefore, how to improve the above problems of this process' has become an important issue in the current process. I Summary of the Invention: The main purpose of the present invention is to provide a method for avoiding cracking of the polished film layer in the chemical mechanical polishing process by changing the shape of the dununies of the dummy pattern. . Another object of the present invention is to provide a dummy pattern applied to integrated circuits, which can reduce the stress generated during the chemical mechanical polishing process, and avoid trench filling materials or Researched

548735

The negative impact of the peeling of the abrasive film layer, and improve the process yield and reduce the defects of the wafer produced. The invention discloses an integrated circuit, which includes a semiconductor substrate, a dielectric layer, at least one conductive trench, and a pattern. The dielectric layer is disposed on the semiconductor substrate and includes a connection area and an open space. Area, the conductive trench system (a) is disposed in the connection area in the dielectric layer, and the locust pattern is formed in the open area in the dielectric layer, so that the open area The pattern density is similar to the density of the conductive trenches in the connection area. The integrated circuit is characterized in that the horizontal cross-sect ion shape of the locust injury pattern is selected from the group consisting of a polygon, an ellipse, and a circle each having an angle greater than 90 degrees. Group. In another aspect of the present invention, a metal frame is disposed in the half area and an open channel, and the metal area of the open area is such that the missing angle is greater than 90 in the area and the emptying. The conductor bottom region, the inner-area pattern, and the dense dielectric layer region are provided. The integrated circuit includes half of the dielectric layer on the material, and the connection region of the dielectric layer has a plurality of layers. The metal cymbal pattern has a degree similar to that of the conductive element in the connection area, and the chemical mechanical polishing process has a substantially uniform and flat top grade.) The shape, angle, ellipse, and circle of the metal pattern are applied to a product. After the body circuit conductor substrate and a conductive metal trench including a connection line make the electrical trench in the open area dense, the surface of the connection line without depression is selected from the group consisting of. 548735

The polygonal layer of the locomotive pattern is a low dielectric material.

In a preferred embodiment of the present invention, it is a hexagon or an octagon. And the agency consists. ~ #Mechanical Grinding Process (CMP). In the method of the present invention, in the semi-conducting grinding process, the layer includes a shame pattern area, the shading pattern is distributed, and the shading pattern is polygonal, oval, and round. In addition, the invention also discloses an avoidance method. In the method of cracking of the ground film layer, one layer on the substrate is subjected to the chemical mechanical active region (active region) and a case is used to uniformly adjust the pattern of the layer. The dense shape is selected from the group consisting of angles greater than 90 degrees. Group. ^ In the method of the invention, the so-called "active area" is relative to the 傀儡 pattern area. The pattern contained in the active area has a specific effect ^ and is connected to other structures of the semiconductor substrate without The crystal pattern like the crystal pattern region, except for adjusting the degree distribution of the pattern of the semiconductor layer in which it is located, has no effect by itself, and is not connected with other non-crystal patterns. According to the method of the present invention, by defining the 傀儡 pattern on the layer of the semiconductor substrate, light having a shape selected from the group consisting of a polygon, an ellipse, and a circle each having an angle greater than 90 degrees is used. A mask to form the (or other) ridge with the shape of the mask, and achieve the above-mentioned purpose of the present invention.

Page 8 548735 V. Description of the invention (6) In a preferred embodiment of the method of the present invention, the system is made by masking each corner of the quadrangular pattern on the photomask, or filling it into a hexagon. Or one eight = (chamfer) and so on.乂 or approximately circular. In another embodiment of the present invention, the ground 儡 pattern is made of different materials. ^ The thousand-conductor layer and the 傀 series are a low-dielectric material and — ^ M 4 layer and the 傀儡 pattern copper material 椹 # a low-dielectric material and a nitrided fu Cheng 'or are the methods of the present invention, respectively, can be applied to _ $ + Conductor Kai # as long as the layer contains傀儡 设计 和 、 # Any layer on your material, Cheng. The detailed description of the invention of chemical mechanical polishing and planarization is as follows: The upper wiring layer is made on the metal substrate to complete the sect and semiconductor substrate to illustrate the inner ten percent of the 傀儡 pattern in the angle shape. Methods. See Figures 3A to 3C. The 箄 -angled 傀儡 pattern is used to facilitate the use of the metal wire development and pre-mechanical grinding process 定义 defined in the photomask without cracks. )schematic diagram. 1. vertical cross section

$ 9 pages as shown in Figure 2A.

A dry active device, such as a MOS transistor and a passive device, such as a capacitor (not shown above), is deposited on a semiconductor substrate. A dielectric material layer 101 is deposited, and the dielectric material layer 101 is etched and embedded. A first metal pattern = 102a, 102b, 102c, and 102d is formed, thereby generating a plurality of action zones and a plurality of open regions II. Generally speaking, single crystal silicon or other types of semiconductor materials, such as gallium arsenide, germanium, or silicon ions on the insulating layer (silicon ON silicon substrates, S 0 I ) Can be used as a semiconductor substrate, and the crystal orientation of the semiconductor material can be selected as < 110 > or < 11 1 >. Next, a first low dielectric material layer 2000 is deposited on the dielectric material layer 101 and the first metal pattern 102a, 102b, 102c, and 102d as an interlayer dielectric layer. (I LD) use. In a preferred embodiment, the first low-dielectric material layer 200 can be formed using a porous material. As for other materials having a low dielectric constant, such as BD, CORAL, SiLK, Flare, HSQ, and _

Nanoglass can also be used. Among them, a barrier layer (not shown) may be deposited between the dielectric material layer 101 and the first low-dielectric material layer 2000 to cover the "electrical material layer 10". 1 and the first metal pattern 102a, 102b, 102c, and 102d, and protect various components below to prevent improper damage in subsequent processes. Then, as shown in FIG. 2B, in the first low-dielectric material layer 2000, metal interconnecting trenches connecting the first metal patterns 102a, 102b, 102c, and 102d are simultaneously produced. And interlayer dual mosaic patterns 20ia, 20b, 201c and 201d

Page 10 548735 V. Description of the invention (8) and the partial partial embedding patterns 202a, 202b, and 20 2c used to improve the yield of the subsequent chemical mechanical polishing planarization process. Among them, the interconnected double mosaic patterns 2 0 1 a, 2 0 1 b, 2 0 1 c, and 2 0 1 d are located in the action areas I, and the pseudo mosaic patterns 2 02a, 202b, and 2 0 2c is located in these open areas. / That is, at the same time that a known technique 1 forms an interconnected double mosaic pattern in the active areas / it is also synchronized in the open areas II to define the connected photomask corresponding to the open areas The hexagonal patterns (not shown) in the II space form a cross section (h〇rizontal cr0ss secti〇n), which is also a mosaic pattern of Liu Zhi, so that the pattern density in the open area is similar. The density of conductive trenches in area I is straight, middle, continuous, and continuous Λ = 6. The inlay pattern includes a barrier layer and seed layer 205 and a back-filled copper layer IV. Lishan / h mountain side of extra copper sounds, recording; thinking / will be double inlaid / inlay process back), the i low one 'two barrier layer can be removed, and can even be reground (Polish's flat inner metal connection Line layer, and because of the present invention: two C: the cross section of the case is hexagonal β 4 傀 "the inlay picture is a partial top view of Fig. 3C), as shown in Fig. 30, of which Fig. 3C The corners are in chemical mechanical grinding ^ official; V Hai ^ each reduction of the pseudo-embedding pattern, not only to avoid these I3 and fight hard, so The generated stress is large (Peenng), and the filling layer in the pattern is peeled off. (The second layer is ground and the first low-dielectric material layer of the first-low-dielectric material is also prevented from being scratched by the right X column. (Cracklng), so reduce the clothing marks and peel (peel ing) and reduce the production

548735 V. Description of the invention (9) The internal defects (d e f e c t s) of the final wafer are obtained. For this reason, the method of the present invention can indeed solve the problems currently encountered by using a low-dielectric material and adopting a chemical mechanical polishing process for comprehensive planarization. The above description uses a preferred embodiment to describe the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will understand that appropriate changes and adjustments will still be made without departing from the spirit of the present invention. It does not depart from the spirit and scope of the present invention. For example, the above-mentioned preferred embodiment uses copper dual damascene / damascene process as an example, but other conductive metals, such as aluminum, aluminum alloy, doped polycrystalline silicon or combinations thereof, and other metallization processes can also be applied to the present invention. invention.

Page 548 735

Brief Description of the Drawings By combining the following detailed description with the attached drawings, the above-mentioned technical content and many advantages of the present invention can be easily understood. 'Among them, Figure 1 is a integrated circuit chip of a conventional technology. Top view of a metal wiring layer and an enlarged view of the 傀儡 pattern therein; FIG. 2 is a top view of a metal wiring layer crack in a conventional technology and an enlarged view thereof; FIGS. 3A to 3c are The vertical cross-section of the method for forming a plutonium-free inner metal connection layer according to the present invention is a schematic cross-sectional view; and FIG. 3C ′ is a partial top view of FIG. 3c. Description of drawing number: 1, 11 pseudo patterns 2 corners of locomotive pattern 1 4 material of dielectric layer 1 5 cracks 201a, 201b, 201c, 201d metal interconnect 2 0 0 first low dielectric material layer 2 0 2a, 2 0 2b, 2 2 2c Mosaic pattern I active area 100 semiconductor substrate 102a, 102b, 102c, 102d 1st 1st dielectric material layer 1 metal pattern line double mosaic pattern 2 05 barrier layer and seed 2 〇6 backfilled copper layer II open area layer

Claims (1)

548735 銮 虢 91113939 Said 6. Scope of patent application The semiconductor substrate is in an open area, and the open area forms gold in the open area. The mechanical consistency of the helical connection area is flat, and it is characterized by any combination greater than 90 degrees. The upper surface of the dielectric layer after the multiple conductive metal trenches in the connection area of the pseudo-pattern pattern is modified, the (special) metal polygon and ellipsoid correction, the dielectric layer includes a connection area and a A plurality of metal conductive trenches, the dummy locust pattern (dummy pattern), the density (pattern density) is close to the degree, so that the connection area in the dielectric layer and the open area have substantially no depression (dishing); The shape of the ashamed pattern is selected from the group consisting of angled circles and circles, or a series of six such methods to avoid cracking of the polished film layer in the chemical mechanical polishing process (CMP) Wherein the chemical mechanical polishing process is performed on a layer on a semiconductor substrate, the layer includes an active region and a dumffly pattern region, and the ashamed pattern is used to uniformly adjust the Pattern density distribution of layers' The method is characterized in that the dummies shape of the 傀儡 pattern is selected from polygons and ellipses whose angles are all greater than 90 degrees And the group consisting of a circle. 7. The method as described in item 6 of the scope of patent application, wherein the shape of the embossed crystal of the 傀儡 pattern is used to define the 傀儡 pattern on the layer of the semiconductor substrate by using a shape having the shape. Photomask. Page 15 548735 _Case No. 91113939_Revision of the month of June The corners are chamfered or filleted to be approximately circular. 9. The method according to item 6 of the scope of patent application, wherein the layer and the 傀儡 pattern are made of different materials. I 〇 The method as described in item 9 of the scope of patent application, wherein the layer and the 傀儡 pattern are made of a low dielectric material and a copper material, respectively. II. The method as described in item 9 of the scope of patent application, wherein the layer and the hafnium pattern are a low-dielectric material and a nitride, respectively. Page 16