TW508683B - Method for hermetic sealing of electronic components - Google Patents

Method for hermetic sealing of electronic components Download PDF

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Publication number
TW508683B
TW508683B TW090127001A TW90127001A TW508683B TW 508683 B TW508683 B TW 508683B TW 090127001 A TW090127001 A TW 090127001A TW 90127001 A TW90127001 A TW 90127001A TW 508683 B TW508683 B TW 508683B
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Taiwan
Prior art keywords
solder
electronic components
cap
layer
weight
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Application number
TW090127001A
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English (en)
Inventor
Shozaburo Iwai
Masaru Kobayashi
Osamu Sawada
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Tanaka Precious Metal Ind
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Publication of TW508683B publication Critical patent/TW508683B/zh

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/30Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/3013Au as the principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00Articles made by soldering, welding or cutting
    • B23K2101/36Electric or electronic devices
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
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  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Wire Bonding (AREA)
  • Ceramic Products (AREA)

Description

五、發明說明(1) 發明所屬之技術領域 本發明係有關於將載置著 帽罩’通過焊錫接合的電子元 有關於洩漏發生率與習知法才目 的氣密封合方法。 半導體元件的容器(基底)及 件之氣密封合方法。特別係 比’可降低到1 0分之1以下 習知技術 SAW過濾器、水晶振動子等 動的狀態了,由於空氣中的氧氣的甚種+導府體70件原封不 案或墊片,有可能使特性:化:i t軋’腐蝕其導體的圖 須與外氣完全遮斷。通常’内部係真空或被He N =必 以被金屬製或陶竟制的容器(包封體)氣密封合狀載 於電子機器。 ®习口狀態,搭载 術):/封\+、導=件術(真空密封技 中覆Π Π法係將载置著半導體元件的基Si 谇接巾目罩’覆盍+導體元件的密閉方法”匕焊錫 =縫焊般的,對容器材質及其薄度有限制的必要,且 ' 因 為亦不像雷射费封法般地,要求高價的接合裝 ^當的費用實現高標準的氣密狀態的方法,被廣泛地二 然而,關於上述要求密-«·“一… 508683 五、發明說明(2) ^使用著。於此,使用此些氣密封合技術的電子元件的 製k工私中,必須測定製品的洩漏率,進行被稱為精細洩 漏測試的試驗。藉此,捕捉1〇4atm/cc · sec以下的極其微 小的洩漏,排除與此不符的不良品,以努力提供 ^ 的信賴性保證。 电T兀件 以上各點的, 生率少的、有 子元件之小型 術為目的。 對於要求如此 製造洩漏發生 電子元件的低 對電子機器的 搭載的電子元 此的要求謀取 。另外,若加 密封法亦要求 且’焊錫密封法 件,雖可能高效率地 電子元件,在為取得 降低此洩漏發生率。 一方面,近年來 斷’此些電子機器上 化。然而,藉按照如 其氣密封合變得困難 低之要求,對於焊錫 生率少的方法。 本發明係考慮到 與習知法相比洩漏發 的、即使對今後的電 子元件之氣密封合技 南的氣密性的電子元 率(不良率)0· 2%以下的 費用化,則期望能更加 小型化的要求一直不 件被要求進一步的小型 電子元件的小型化,使 上上述般的不良率的降 更簡易的氣密不良之發 以提供在烊錫密封法, 效的氣密封合係可能 化’亦無戌漏發生的電 發明的概述 了對im;二;=課題進行了深刻的研討,以 因為如果只是;變適】的用進行重新考慮, i更了照樣使用從前的機器, 508683 五、發明說明(3) 無須追加新的設備。 系焊錫(sH : ?法中使用的烊锡材料’大多使用Sn—Pb 2〇番旦Γ Pb卜 焊I作1 在此,本發明者等首先使用了 Au — Sn系 擁、、66 : _錫材料的基本組成。此係因為Pb對人體有令人 ^二虐〜1從對操作者的安全性、近來的環境保全的觀 J考慮,Pb被認為不係合適的材料。 〇/c ,本發明者等在使用AU —Sn系焊錫(Au-20重量 π 1:錫材料的場合’為得到比習知更具信賴性的密 封,^為有必要變更其組成。此係因 點約為280 〇C、t卜鲈柄絲女土上人+ ^ ^ L比軚低,雖有封合時不影響半導體元件的 接口邛之優點,但使用此焊錫的場合,盡管只是少許, 有戌漏發生的場合。 且,本發明者等對使用Au-20重量%Sn系焊錫時的接人 部進行了詳細的研討,得知此焊錫材料的接合部,雖缺i 本上呈現Au-Sn的共晶組織,但局部的形成了 Au濃度高、、土 Au-Sn合金相(以下稱為濃^層)。因為此濃^層係金屬 化合物的1種、較硬,比周圍的Au — Sn的共晶相的熔點古曰, 在帽罩的接合溫度下並未溶融,而是作為固相殘留著阿 且,由於所形成的濃Au層的大小不同,即使將帽罩士 加壓並接合在基底上,在帽罩或基級的接合面有各種 大小的濃Au層附著。依照其大小而產生焊錫層的厚产= 或厚的地方,而使焊錫層的厚度不均一。 又殊4 如此般的焊錫層的厚度不均一並非直接成為洩漏的原
五、發明說明(4) :ίΐ錫層的厚度不均一明顯的場合’被推測係 測試;:=;期使用而導致的焊錫層表,或浅漏 之處產::ϊ 外產生差麼而引起的,從焊錫層較薄 焊錫的量亦:兔t ’今後電子兀件的小型&,及所使用的 A 亦蜒為〉、量,此些被認為對濃Au層的影響變大。 久形成接合不良之處,有可能產生即使在接合後不 、狀態、亦無法保持氣密狀態的接合部。 考慮到濃Au層相的影響,將帽罩的接合溫度,即 ' ^加熱溫度昇至使濃Au層可能溶融的、焊錫 =相的高溫,此亦被考慮i^但是,使接合溫度^成 的手二部:半導體元件產生不良影響,因此不認為係適當 于数。在此,本發明者等使接合溫度與習知的同樣範 上重ϊϊ凝固過程中不產生濃Au層’有從根本 董新考慮其組成的必要,研討結果以致想到本發明。 與帽子元ΐ(含有使載置半導體元件的基底 ^ ^知錫接口的工程)的氣密封合方法中,作為此焊 二使用Au 78重量%以上、79· 5重量%未滿,其餘的由^ 、卫成的焊錫,對電子元件進行接合的氣密封合方法。 本發明中,將Au的組成與原來使用的Au —^系焊錫有 微小的改變,藉此,可使凝固時焊錫的組織幾乎都是 Au-Sn的共晶組織。其結果,接合時焊錫層中無濃-層的 可使焊錫層有均-的厚度。因&,長期使用或洩漏 =广時無洩漏的發生。進而,使接合部的洩漏率(不良品 率)可能比以往更加降低,能有效地製造電子元件。口口 1-—. 第7頁 508683 五、發明說明(5) —而且,如本發明般的,對使用的輝錫,將Au的组 疋於Au 7δ重量%以上、79. 5重量%未滿的狹窄範圍的, 因為若在79.5重量%以上則大量產生濃^層,而78重量以 滿時,開始產生濃Sn層,此場合亦對接合部份有不良$ f二然:’在本發明的組成中雖亦有少量的濃如層出:, ί :S。。層係微細的’即使有少量亦不會使焊錫層的厚 可是’如焊錫密封法般的’使用焊錫的接合技術中, 為確保接合部材的接合強度,#交好的係使焊錫有良= 濃性。特別是,作為電子元件中使用的帽 .^ 多地#用斜姑攸^ 0材質’雖較 夕也使用科拔路-儿,54重量%Fe-29重量%Ni —17會旦 =合气的商品名)’但由於科拔路不濕潤於焊錫,對= 路製的巾@罩直接焊接的場合,有可能產生人 的剝離。因此,為確伴焊裼的捫 a不良、焊錫 A . ^ ^ , 馮確保绊錫的潤濕性,且防止焊錫中的澧 u曰的產生,並使焊錫層的厚度均一,如申 所示’最好對帽罩進行鍍金,作為焊錫,申m2旦 %以上、79重量%未滿,其餘的由如 7二! 如此般地,對帽罩進行鍍金,並使焊 f利fe圍1所述的範圍更狹小,係 對罩且比明 提ΐ,,亦可抑制由於此:金而t 座王/辰U /t 就疋,對帽罩進行鍵今的i县人 層接觸,使焊錕由 ’焊錫與鍍金 二金的濃度增加而產生濃au 從~錫的組成中的AU 78重量〇/0以μ 以下,藉此’使錢金層的Au擴散至微量里二= 第8頁 2169-4441 -PF;Ahddub.p t d 508683
五、發明說明(6) 使焊錫的組織成為Au-Sn的共晶組織。 因此,根據申請專利範圍2的發明,在使帽罩的潤濕 性良好以確保接合強度的同時,亦可抑制濃Au層的 使焊錫層的厚度均一。 ㈢、^ 圖式簡單說明 第1圖係顯示本實施形態的I c包封體製造工程的概略 圖。 第2圖係顯示在本實施形態製造的Ic包封體的 圖。 第3圖、第4圖各係顯示本實施例及比較例的接入 織的SEM照片。 口 ° 符號說明 1C; 2〜1C1所搭載的陶瓷製基底; 3〜帽罩; 4〜焊錫; 5~ 1C包封體。 發明的實施形態 以下’將本發明的實施形態與圖面共同說明。 實施例: 將’合解鑄造法製造的、78· 5wt%Au-21 · 5wt%Sn的塊, 壓延加I 士、@ 1 , 欣溥板形狀後,穿孔加工製造成角環狀的焊錫。 且’用此焊錫將帽罩接合於搭載著IC晶片的基底,以製造
508683 五、發明說明(7) ic包封體。如圖1所示,ici搭載的陶瓷製基底2,及預先 鍍過$的柯拔路製帽罩3之間,夾進上述加工後的焊錫4, 專送爐加熱至3〇〇c ’使焊錫4溶融並接合成1C包封體 5此時接合後的IC包封體的剖面如圖2所示。 比較例: 對本實施形態,製造8〇wt%Au〜20wt%Sn的蠟材,製造 了 I y包封體。在此,蠟材的製造方法、加工法及丨c包封體 的製造方法係與上述實施形態用同樣的方法。 實施例1 (洩漏率的測定): 對於以上的實施形態及比較例製造的丨c包封體,實行 精細线漏測試的氦洩漏測試。對兩者中製造的IC包封體的 戍漏率進行比較和研討。於此,氦洩漏測試係將製造的IC 包封體放入氦洩漏探測器,使丨c包封體的外部成真空,對 於從内部漏出的氦分子進行計數。 其結果,比較例中,用8〇wt%Au-20wt%Sn的蠟材製造 的1C包封體的洩漏率(不良率)係〇· 2%。與此相對,本實施 形態中製造的1C包封體的洩漏率係〇· 1%,與比較例的氣密 方法相比,確認洩漏率得到了改善。 實施例2 (接合部組織的觀察): 接著,須確認實施形態及比較例製造的丨C包封體的接 合部(焊錫層)的組織,對於雙方的接合部進行SEM觀察。 實施形態及比較例的接合部的SEM照片如圖3及圖4所示。 從此些的SEM照片可確認本實施形態的接合部有微細的共 晶組織。一方面,比較例的接合部被確認有粗大的濃Au層
2169-4441-PF;Ahddub.ptd 第10頁 (圖4中的白色部分)。、 同,使接合時的炫雜 因為此濃Au層的大小亦有不 而產生洩漏的。 曰的厚度稍有不均一,被推剛係由此 產業上的利用可能性 後的本發明能在不產生濃^層(使接合 件的密閉封合=不=一化的要因)的情況下’使電子元 , 』此 错此,使電子元件的洩漏發生率比習 雷不氐彼可有效地製造電子元件。而1,本發明對今後的 電子疋件的小型化亦可適應。
2169-4441-PF;Ahddub.ptd 第11頁

Claims (1)

  1. 508683 六、申請專利範圍 1. 一種電子元件的氣密封合方法,含有載置半導體元 件的基底與帽罩用焊錫接合工程, 其特徵在於: 作為上述焊錫,使用Au 78重量%以上、79. 5重量%未 滿,其餘的由S η組成的焊錫,而進行接合。 2. 如申請專利範圍第1項所述的電子元件的氣密封合 方法,其中對帽罩施行鍍金,使用Au 78重量%以上、79重 量%以下,其餘的由Sn組成的焊錫,而進行接合。
    2169-4441-PF;Ahddub.p t d 第12頁
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