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Method for hermetic sealing of electronic parts

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Publication number
EP1341229A1
EP1341229A1 EP20010997845 EP01997845A EP1341229A1 EP 1341229 A1 EP1341229 A1 EP 1341229A1 EP 20010997845 EP20010997845 EP 20010997845 EP 01997845 A EP01997845 A EP 01997845A EP 1341229 A1 EP1341229 A1 EP 1341229A1
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Patent type
Prior art keywords
solder
au
sealing
electronic
parts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP20010997845
Other languages
German (de)
French (fr)
Other versions
EP1341229A4 (en )
Inventor
Shozaburo c/o Tanaka Kikinzoku Kogyo K.K. IWAI
Masaru c/o Tanaka Kikinzoku Kogyo K.K. KOBAYASHI
Osamu c/o Tanaka Kikinzoku Kogyo K.K. SAWADA
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tanaka Kikinzoku Kogyo KK
Tanaka Metal Ind Co Ltd
Original Assignee
Tanaka Kikinzoku Kogyo KK
Tanaka Metal Ind Co Ltd
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Publication date

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/22Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
    • B23K35/24Selection of soldering or welding materials proper
    • B23K35/30Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
    • B23K35/3013Au as the principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2201/00Articles made by soldering, welding or cutting by applying heat locally
    • B23K2201/36Electric or electronic devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • HELECTRICITY
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
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    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
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    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
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    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
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    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/161Cap
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    • H01L2924/16195Flat cap [not enclosing an internal cavity]
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Abstract

There is provided a method of hermetically sealing electronic parts, comprising the step of bonding a base having semiconductor devices mounted thereon and a cap together via a solder. The solder is composed, by weight, of 78% or more but less than 79.5% Au, and the balance Sn. It is particularly preferred that the bonding is performed with the use of a solder composition composed, by weight, of 78% or more but 79% or less Au, and the balance Sn as the solder and furthermore through plating the cap with gold.

Description

    TECHNICAL FIELD
  • [0001]
    The present invention relates to a method of hermetically sealing electronic parts by which a container (base) having semiconductor devices placed thereon and a cap are bonded together via a solder. More particularly, it relates to a method of hermetic sealing that can reduce the leak rate to not more than one tenth of levels under conventional methods.
  • BACKGROUND ART
  • [0002]
    In various semiconductor devices, such as SAW filters and quartz-crystal oscillators, if they are kept as they are, there is a fear that due to the oxygen and humidity in the air, their conductive patterns and pads might be corroded, resulting in poor properties. Therefore, in order to completely cut off these semiconductor devices from the outside air, usually they are mounted on eleotronic apparatus while being hermetically sealed in a metal or ceramic container (package), the interior of which is in a vacuum or is filled with He or N2.
  • [0003]
    As the hermetic sealing technology of semiconductor devices, the solder sealing method, seam welding method, laser sealing method, etc., are known, and these methods are appropriately used according to the scale of electronic parts to be manufactured, required sealing performance, etc. Among others, the solder sealing method involves soldering a cap to a base on which semiconductor devices are mounted, and sealing the semiconductor devices by covering them. Because it is unnecessary to limit container materials and their thickness unlike the seam welding method and because expensive bonding devices required by the laser sealing method are unnecessary, this solder sealing method has come into widespread use as a method that allows a high-level sealed state to be realized at appropriate cost.
  • [0004]
    Incidentally, for electronic parts for which the above-described sealed state is required, needless to say, it is necessary that the semiconductor devices in the interior be completely cut off from the outside air and be used without a fear of the generation of leakage. In the manufacturing processes of electronic parts by use of these hermetic sealing techniques, a test called the fine leak test is conducted in order to measure the leak rate of products. This test enables even very minutes leaks of not more than 10-6 atm/cc·sec to be captured and defective parts that do not meet this standard are rejected to guarantee the reliability of electronic parts.
  • [0005]
    And even for electronic parts of which such a high sealing property is required, through the use of the solder sealing method it is possible to efficiently manufacture electronic parts at a leak rate (fraction defective) of not more than 0.2%. However, in order to further reduce the cost of electronic parts, it is desirable that this leak rate be capable of further reduced.
  • [0006]
    On the other hand, due to the continuing requirement for smaller-size electronic apparatus of the recent years, it is required that electronic parts to be mounted on these electronic apparatus be also smaller in size. However, when the size of electronic parts is reduced to meet this requirement, the hermetically sealing the electronic parts becomes difficult. When the requirement for a reduction in the fraction defective is considered in addition to this requirement for small size design, it can be said that also for the solder sealing method, a method with a low rate of poor sealing is sought for more readily.
  • [0007]
    The invention was made in consideration of a situation as mentioned above, and it is the object of the invention to provide a hermetic sealing technique of electronic parts, which permits hermetic sealing by the solder sealing method at a lower leak rate and more efficiently than with conventional methods, and which does not cause leakage even in the trend toward smaller-size electronic parts in the future.
  • DISCLOSURE OF THE INVENTION
  • [0008]
    The present inventors has made intensive investigations to solve the above-described problem and decided to review solder materials used in the conventional solder sealing method. This is because existing equipment can be used without a modification and addition of new equipment is unnecessary if a change is made only in the solder materials.
  • [0009]
    As the solder materials used in the solder sealing method, Sn-Pb-based solders (Sn-37 wt.% Pb) are mostly used and Au-Sn-based solders (Au-20 wt.% Sn) are sometimes used. The present inventors decided to use Au-Sn-based solders as the basic composition of solder materials. This is based on the conception that Pb, which is an element that presents a danger to the human body, is not a desirable material in view of the safety to workers and the standpoint of environmental conservation of the recent times.
  • [0010]
    And the inventors considered that in using Au-Sn-based solders (Au-20 wt. % Sn) as solder materials, it is necessary to change their compositions in order to ensure higher-reliability sealing than before. This is because although Au-20 wt. % Sn solders have the advantage that they have no effect of sealing on the bonded portions of semiconductor devices, leakage may sometimes occur, though not frequently, because of their relatively low melting points of about 280°C.
  • [0011]
    And the inventors closely examined the bonded portions obtained by Au-20 wt.% Sn solders, and found out that the bonded portions obtained by the solder materials basically show an Au-Sn eutectic microstructure with a partial mixture of an Au-Sn alloy phase having a high concentration of Au (hereinafter referred to as an Au rich phase) . Because this Au rich phase is a kind of intermetallic compound and is hard, it has a higher melting point than the surrounding Au-Sn eutectic phase. At temperatures below the bonding temperature of a cap, therefore, this Au rich phase does not melt and remains as a hard phase. And because of diverse sizes of this Au rich phase, even if a cap is bonded to a base under uniform pressure, Au rich phases of various sizes adhere to the bonded surfaces of the cap or base, with the result that areas of small solder layer thickness and those of large solder layer thickness are formed, leading to a nonuniform thickness of the solder layer.
  • [0012]
    This nonuniformity of the solder layer is not a direct cause of leakage. However, when the nonuniformity of the solder layer is remarkable, it might be thought that leakage occurs from portions of small solder layer thickness due to the deterioration of the solder layer resulting from use of electronic parts for a long time or due to a pressure difference that occurs in and outside electronic parts during a leak test. Also, it might be thought that when the sizes of electronic parts are reduced in the future, the amount of solder used also decreases and hence the effect of an Au rich phase becomes great. In this case, there is a fear that portions of defective bonding might be formed and that bonded portions whose air-tight state cannot be maintained even immediately after bonding might be formed.
  • [0013]
    When this effect of an Au rich phase is considered, it is also conceivable that a high temperature at which the Au rich phase can also be melted and at which the solder is a complete liquid phase is used as the bonding temperature of the cap, i.e., the heating temperature of the solder. However, raising the bonding temperature results in an adverse effect on the semiconductor devices in the interior and, therefore, it cannot be said that this is an appropriate means. Therefore, considering that a drastic review of solder compositions is necessary for preventing an Au rich phase from being formed in the melting and solidification processes while keeping the bolding temperature in the same range as before, the inventors conducted an investigation and, as a result, they reached the present invention.
  • [0014]
    In the invention there is provided a method of hermetically sealing electronic parts that includes the step of bonding a base, on which semiconductor devices are mounted, and a cap together via a solder, in which this solder consists, by weight, of 78% or more but less than 79.5% Au, and the balance Sn.
  • [0015]
    In the invention, the Au content was slightly changed from those of conventionally used Au-Sn-based solders and by this slight change the microstructure of the solder during solidification can be almost converted to an Au-Sn eutectic structure. As a result, an Au rich phase is not formed in the solder layer during bonding and uniform thickness can be given to the solder layer. As a result, leakage does not occur during use for a long period or during a leak test. As a result, it becomes possible to lower the leak ratio (fraction defective) of bonded portions from conventional levels and to efficiently manufacture electronic parts.
  • [0016]
    The reason why in the invention the content of Au of the solder to be used is limited to a narrow range of 78 wt.% or more but less than 79.5 wt.% is as follows. Au rich crystals are formed in large amounts when the Au content is not less than 79.5 wt.%, whereas Sn rich crystals begin to be formed when the Au content is less than 78 wt.% and, also in this case, the formation of Sn rich crystals has an adverse effect on bonded portions. Also with the composition of the invention, Sn rich crystals are formed in small amounts. However, because the Sn rich crystals are fine, they do not make the solder layer thickness nonuniform if they are formed in small amounts.
  • [0017]
    Incidentally, in bonding techniques using solders as in the solder sealing method, it is desirable to improve the wettability of solders in order to ensure the bonding strength of bonded members. In particular, as a material for caps used in electronic parts, Kovar (brand name of a 54 wt.% Fe-29 wt.% Ni-17 wt.% Co alloy) is often used. However, because Kovar is not wetted by solders, bonding defects and solder exfoliation might occur if bonding is performed by directly applying solders to a cap made of Kovar. Therefore, in order to ensure the wettability of solders and a uniform solder layer thickness by preventing the generation of an Au rich phase in solders, it is desirable to perform bonding by plating the cap with gold and by using a solder composition composed, by weight, of 78% or more but 79% or less Au, and the balance Sn, as the solder described in a second aspect of the present invention.
  • [0018]
    The reason why the cap is plated with gold and why besides the solder composition is made narrower than the range described in Claim 1 is that the wettability of the cap is improved by plating the cap with gold and that, at the same time, the formation of an Au rich phase caused by this plating with gold is suppressed. That is, when the cap is plated with gold, the solder and the gold coating layer come into contact with each other and gold is diffused in the solder, resulting in an increase in the gold content of the solder. As a result, an Au rich phase may sometimes be formed. For this reason, by using an Au content of solder in the range, by weight, of 78.5% or more and 79% or less, the Au coming from the coating layer is diffused into an Sn rich phase that is formed in a small amount due to this composition, whereby the microstructure of the solder is formed as an Au-Sn eutectic structure.
  • [0019]
    Therefore, according to the second aspect of the invention, it is possible to ensure bonding strength by improving the wettability to the cap and, at the same time, it is possible to ensure a uniform solder layer thickness by suppressing the formation of an Au rich phase.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0020]
    • Fig. 1 is a schematic representation of the steps of an IC package fabrication process in this embodiment;
    • Fig. 2 is a sectional view of an IC package fabricated in this embodiment;
    • Fig. 3 shows a SEM photograph of the microstructure of a bonded portion in this embodiment; and
    • Fig. 4 shows a SEM photograph of the microstructure of a bonded portion in a comparative example.
  • BEST MODE FOR CARRYING OUT THE INVENTION
  • [0021]
    The embodiment of the invention will be described below in connection with the drawings.
  • [0022]
    Embodiment: A 78.5 wt.% Au-21.5 wt.% Sn ingot obtained by a melting-casting process was rolled into a sheet and after that, a solder in square ring form was obtained through punching. This solder was employed to bond a cap to a base on which IC chips are mounted, whereby an IC package was produced. As shown in Fig. 1, between a base 2 made of ceramics, on which an IC 1 is mounted, and a cap 3 made of Kovar and previously plated with Au was sandwiched a solder 4 after the above-described working, and they were heated in a conveyor furnace to 300°C, whereby the solder 4 was melted and bonded to obtain an IC package 5. The section of the IC package after bonding is shown in Fig. 2.
  • [0023]
    Comparative example: In contrast to the embodiment, an 80 wt.%-Au-20 wt.% Sn brazing material was produced and an IC package was produced. The method of producing the brazing material, method of working the brazing material and method of producing the IC package were the same as in the above embodiment.
  • [0024]
    Example of experiment 1 (measurement of leak rate) : The IC packages produced in the above-described embodiment and comparative example were subjected to a helium leak test, which is a fine leak test. The leak rates of the IC packages produced in the embodiment and comparative example were compared and examined. Incidentally, the helium leak test was conducted by applying the IC packages thus produced to a helium detector, causing the helium molecules in the interior to leak out through drawing a vacuum in the exterior of the IC packages, and counting the leaking helium molecules.
  • [0025]
    As a result, the leak rate (fraction defective) was 0.2% in the IC package produced with the use of the 80 wt.%-Au-20 wt.% Sn brazing material of the comparative example. In contrast to this, the leak rate of the IC package produced in the embodiment was 0.1% and it was confirmed that the leak rate is improved from that of the hermetic sealing method of comparative example.
  • [0026]
    Example of experiment 2 (observation of microstructures of bonded portions): Next, in order to investigate the microstructures (solder layers) of the IC packages produced in the embodiment and comparative example, the two bonded portions were observed under an SEM. The SEM photographs of the bonded portions of embodiment and comparative example are shown in Fig.s 3 and 4, respectively. From these SEM photographs it was ascertained that the bonded portion of the embodiment has a fine eutectic structure. On the other hand, it was ascertained that coarse Au rich phases (the white parts in Fig. 4) are present in the bonded portion of the comparative example. Because these Au rich phases have different sizes, it might be thought that they make the solder layer thickness during bonding nonuniform, though slightly, thereby causing leakage.
  • INDUSTRIAL APPLICABILITY
  • [0027]
    As described above, the present invention makes it possible to hermetically seal electronic parts without generating an Au rich phase that makes the solder layer thickness after bonding non-uniform. This enables the leak rate of electronic parts to be lowered from levels of conventional ones, making it possible to efficiently manufacture electronic parts. Further in the future, the invention is adaptable for the miniaturization of electronic parts.

Claims (2)

  1. A method of hermetically sealing electronic parts, said method comprising the step of bonding a base having semiconductor devices mounted thereon and a cap together via a solder, wherein said bonding is performed with the use of said solder composition composed, by weight, of 78% or more but less than 79.5% Au, and the balance Sn.
  2. The method of hermetically sealing electronic parts according to Claim 1, wherein said bonding is performed through plating the cap with gold and with the use of said solder composition composed, by weight, of 78% or more but less than 79% Au, and the balance Sn.
EP20010997845 2000-11-27 2001-11-27 Method for hermetic sealing of electronic parts Withdrawn EP1341229A4 (en)

Priority Applications (3)

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JP2000358744A JP2001176999A (en) 2000-11-27 2000-11-27 Method of sealing electronic component
JP2000358744 2000-11-27
PCT/JP2001/010302 WO2002043141A1 (en) 2000-11-27 2001-11-27 Method for hermetic sealing of electronic parts

Publications (2)

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EP1341229A1 true true EP1341229A1 (en) 2003-09-03
EP1341229A4 true EP1341229A4 (en) 2005-08-24

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JP (1) JP2001176999A (en)
CN (1) CN1394359A (en)
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JP4769469B2 (en) * 2004-02-20 2011-09-07 田中貴金属工業株式会社 Joining method according au-Sn based brazing material
JP4285753B2 (en) 2004-06-21 2009-06-24 田中貴金属工業株式会社 Hermetic seal cover and manufacturing method thereof
JP4560830B2 (en) * 2004-06-28 2010-10-13 三菱マテリアル株式会社 Au-Sn alloy powder for a solder paste
JP2007142054A (en) * 2005-11-16 2007-06-07 Sumitomo Metal Mining Co Ltd Seal cover and its manufacturing method
JP4826735B2 (en) * 2005-11-21 2011-11-30 三菱マテリアル株式会社 Method for producing a Au-Sn alloy bump without incorporating a large voids
US7910945B2 (en) * 2006-06-30 2011-03-22 Cree, Inc. Nickel tin bonding system with barrier layer for semiconductor wafers and devices
US7855459B2 (en) * 2006-09-22 2010-12-21 Cree, Inc. Modified gold-tin system with increased melting temperature for wafer bonding
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JP5145964B2 (en) * 2008-01-18 2013-02-20 株式会社大真空 Electronic components of the main body casing member, the method of manufacturing electronic components, and electronic components
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JP2001176999A (en) 2001-06-29 application
WO2002043141A1 (en) 2002-05-30 application
US20020190106A1 (en) 2002-12-19 application
EP1341229A4 (en) 2005-08-24 application
CN1394359A (en) 2003-01-29 application
US6691911B2 (en) 2004-02-17 grant

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