TW490674B - Semiconductor memory device - Google Patents

Semiconductor memory device Download PDF

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Publication number
TW490674B
TW490674B TW089126201A TW89126201A TW490674B TW 490674 B TW490674 B TW 490674B TW 089126201 A TW089126201 A TW 089126201A TW 89126201 A TW89126201 A TW 89126201A TW 490674 B TW490674 B TW 490674B
Authority
TW
Taiwan
Prior art keywords
data
mentioned
output
test
memory device
Prior art date
Application number
TW089126201A
Other languages
English (en)
Chinese (zh)
Inventor
Masaki Tsukude
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW490674B publication Critical patent/TW490674B/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
TW089126201A 2000-04-10 2000-12-08 Semiconductor memory device TW490674B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000107921A JP4497645B2 (ja) 2000-04-10 2000-04-10 半導体記憶装置

Publications (1)

Publication Number Publication Date
TW490674B true TW490674B (en) 2002-06-11

Family

ID=18620852

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089126201A TW490674B (en) 2000-04-10 2000-12-08 Semiconductor memory device

Country Status (4)

Country Link
US (1) US6331958B2 (enExample)
JP (1) JP4497645B2 (enExample)
KR (1) KR100358622B1 (enExample)
TW (1) TW490674B (enExample)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001242226A (ja) * 2000-02-29 2001-09-07 Fujitsu Ltd 半導体装置及びその試験方法
KR100393217B1 (ko) * 2001-03-09 2003-07-31 삼성전자주식회사 메모리장치들과 데이터 버퍼를 동일한 클럭 주파수로동작시키기 위한 제어 회로를 구비하는 메모리 모듈
JP2003303498A (ja) * 2002-04-08 2003-10-24 Mitsubishi Electric Corp 半導体記憶装置
KR100448706B1 (ko) * 2002-07-23 2004-09-13 삼성전자주식회사 단일 칩 시스템 및 이 시스템의 테스트/디버그 방법
KR100487946B1 (ko) * 2002-08-29 2005-05-06 삼성전자주식회사 반도체 테스트 시스템 및 이 시스템의 테스트 방법
KR100555532B1 (ko) * 2003-11-27 2006-03-03 삼성전자주식회사 메모리 테스트 회로 및 테스트 시스템
JP4562468B2 (ja) * 2004-09-13 2010-10-13 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100669546B1 (ko) * 2005-03-29 2007-01-15 주식회사 하이닉스반도체 메모리 장치의 병렬 압축 테스트 회로
KR100733409B1 (ko) 2005-09-29 2007-06-29 주식회사 하이닉스반도체 테스트 제어 장치 및 이를 포함하는 반도체 메모리 장치
KR100695436B1 (ko) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 직렬 입/출력 인터페이스를 가진 멀티 포트 메모리 소자 및그의 동작 모드 제어방법
US7529139B2 (en) * 2007-01-26 2009-05-05 Mediatek, Inc. N-port memory circuits allowing M memory addresses to be accessed concurrently and signal processing methods thereof
JP2010182358A (ja) * 2009-02-04 2010-08-19 Elpida Memory Inc 半導体装置
KR101039853B1 (ko) 2009-10-30 2011-06-09 주식회사 하이닉스반도체 반도체 메모리장치 및 이의 압축 테스트 방법
JP5606880B2 (ja) * 2010-11-11 2014-10-15 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
KR101282722B1 (ko) * 2011-03-09 2013-07-04 에스케이하이닉스 주식회사 메모리 장치 및 메모리 장치의 테스트 방법
KR20120110431A (ko) 2011-03-29 2012-10-10 에스케이하이닉스 주식회사 반도체 메모리 장치
KR20160039461A (ko) * 2014-10-01 2016-04-11 에스케이하이닉스 주식회사 반도체 메모리 장치
KR101705589B1 (ko) * 2015-03-31 2017-04-04 (주)피델릭스 테스트 효율이 향상되는 반도체 메모리 장치
CN120164517B (zh) * 2025-05-20 2025-08-12 合肥康芯威存储技术有限公司 存储芯片测试数据的配置系统及配置方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2974219B2 (ja) * 1990-08-02 1999-11-10 三菱電機株式会社 半導体記憶装置のテスト回路
JPH05135600A (ja) 1991-11-12 1993-06-01 Fujitsu Ltd 半導体記憶装置
US5668764A (en) * 1995-03-22 1997-09-16 Texas Instruments Incorporated Testability apparatus and method for faster data access and silicon die size reduction
JPH10289600A (ja) * 1997-04-14 1998-10-27 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
KR100358622B1 (ko) 2002-10-25
JP4497645B2 (ja) 2010-07-07
KR20010090702A (ko) 2001-10-19
JP2001291399A (ja) 2001-10-19
US20010028583A1 (en) 2001-10-11
US6331958B2 (en) 2001-12-18

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