經濟部中央標準局員工消費合作杜印製 410306 A7 _ B7 五、發明説明(I ) 〔發明之背景〕 本發明是關於記憶装置,且尤指一棰冗餘的I /0線 霉路。 半等體DRAM —般是由列線與行赛組成。鄰近各行 列穿越處的電容器儲存電荷(代表欲被儲存之資料),且 電容器是被切換到行線以於行線收到逋當電歷之際接納電 荷或者放出電荷。選定列線與行線是為了便於藉由列解碼 器與行解碼器譲取及寫入特定的電容器。 有時候行線或者相關的元件會引出許多缺陷,如記憧 格本身或者感測放大器。有鑒於此,D RAM通常包含冗 餘(備用)行*其包括提供額外的記憶元件與行電路。該 額外的記億體與所需的冗餘解碼器(用以代替有缺陷的行 Μ存取該記憶髏)使用有用的半等體晶片區並使記憶體效 率降低。 較大的記憶體一般是细分為列與行的子陣列。較早期 的記憶體於一行解碼器陣列的各面上實體設置一子陣列* 且行解碼器存取各鄰近的子陣列内的行。記憶體是分成塊 ,各塊是由位於行解碼器兩面上的兩個子陣列構成。冗餘 行與行解碼器是設置在通常位於各塊一端的位置上。一有 缺陷的行之位址必須被規盡到一冗餘解碼器*以當一有缺 陷行的位址被接收到時致能一冗餘行。該有缺陷的行解碼 器亦是Μ電氣方式使用冗餘解碼器之輸出•或者Μ實體上 具備一局部保險躲的方式而禁能。Printed by the staff of the Central Bureau of Standards of the Ministry of Economic Affairs on consumer printing 410306 A7 _ B7 V. Description of the Invention (I) [Background of the Invention] The present invention relates to a memory device, and particularly to a redundant I / 0 line. Semi-equal DRAM is generally composed of columns and rows. The capacitors near the crossings of the columns store the charge (representing the data to be stored), and the capacitors are switched to the row line to receive the charge or discharge the charge when the row line is received. The column and row lines are selected to facilitate the extraction and writing of specific capacitors by the column and row decoders. Sometimes lines or related components cause many defects, such as the grid itself or the sense amplifier. For this reason, D RAM usually contains redundant (spare) rows * which includes the provision of additional memory components and row circuits. The additional memory banks and redundant decoders needed to access the memory skull instead of defective rows use useful semi-equal chips and reduce memory efficiency. Larger memories are generally sub-arrays subdivided into columns and rows. Earlier memories physically set up a sub-array * on each side of a row of the decoder array, and the row decoder accessed the rows in each adjacent sub-array. The memory is divided into blocks, and each block is composed of two sub-arrays on both sides of the row decoder. Redundant row and row decoders are provided at positions normally located at one end of each block. The address of a defective row must be exhausted to a redundant decoder * to enable a redundant row when the address of a defective row is received. The defective row decoder is also disabled by M using the output of the redundant decoder in the electrical mode, or by having a partial safe-haven method on the M entity.
本紙張尺度適用中國國家標準(CNS ) Λ4規格(210 297公釐) I ^ κ I ~訂 I 矣 i先閱讀背面之注意事項寫本頁) 經濟部中央標準局貝工消費合作社印掣 410306 Α7 Β7 i、發明说明(>) 於一 1 Μ位元的DRAM中可能有2個瑰,各塊包括 —具有2個冗餘解碼器之Y解碼器的專用陣列*各塊內具 有二個陣列,每個Y解碼器具有2個輸出端*且每個陣列 具有2條寅料匯流排。 設置記憶格的冗餘列與(或)冗餘行,是為了取代在 測試期間(如晶圆分類期間)發現的有缺陷的主記憶陣列 之列與(或)行。一般而言,冗餘列與(或)冗餘行具有 最初未指定的位址Μ及與之耦連的冗餘解碼器。冗餘解碼 器是為可程式者,Μ匹配被確定為有缺陷的列與(或)行 之位址。随後禁能該等有缺陷的列與(或)行。 於操作時 > 當執行一記憶體謓取或寫入循環時,可防 止存取該等有缺陷的列與(或)行*並且冗餘解碼器是僅 因應於該等有缺陷的列與(或)行的位址*藉此有效地Μ 冗餘列與(或)行來取代有缺陷的列與(或)行,冗餘列 與(或)行有時候被稱為備用列與(或)行。 可程式冗餘解碼器之一種典型的實施是為一位址解碼 器,其中一多晶矽易熔連路(即保險綠)是連接到一列位 址或行位址媛衡器的各位址位元線•取決於該冗餘解碼器 分別是為一冗餘列堪是一冗餘行。為了以具有一有缺陷記 憶格之記憶格的行或列位址來規划該一冗餘解碼器*保除 绦中被選定者為切斷/焼斷狀態•如•藉助一雷射器。 美國専利第5,325,33 4號中提出了冗餘行電路的實例。 美國專利第5,469,401號中討論了可苗活指派到一單個陣列 本紙張尺度適用中國國家榡準(CNS ) A4規格(2丨0 X 297公釐) 裝 訂 -sC, .(請先閱讀背面之注意事項-?&寫本買) A7 B7 經濟部中央標準局貝工消費合作社印製 五、發明説明 ( ) I 1 1 而 非 所 有 陣 列 的 冗 餘 行 電 路 〇 美 國 專 利 第 5, 4 6 7, 655號掲示 ! 1 1 了 種 可 減 少 所 餺 的 保 險 絲 數 g 的 冗 餘 行 電 路 〇 1 | 於 1 6 Μ 的 D R A Μ 技 術 之 上 , 記 憶 陣 列 分 解 為 多 簇 請 先 閱 1 | 在 用 於 各 簇 連 接 到 I / 0 線 的 全 局 I / 0 線 路 的 加 入 之 讀 背 1 1 面 1 下 9 其 本 來 在 先 前 的 结 構 中 即 已 直 接 進 入 到 積 體 霣 路 I / 之 注 | 意 I 0 0 該 等 全 局 I / 0 線 一 般 是 平 行 於 行 理 擇 線 » 且 垂 直 於 華 項 1 再 1 I 來 白 各 簇 用 之 感 測 故 大 器 的 I / 0 〇 因 此 提 供 — 種 層 次 1 寫 本 的 I / 0 结 構 〇 頁 1 I 層 次 的 I / 0 结 構 可 對 於 64M位元及以上的D R AM提 l 供 了 便 宜 高 頻 寬 的 D R A Μ 磁 心 的 潛 力 〇 其 允 許 大 霣 來 1 白 同 一 子 陣 列 的 感 測 放 大 器 可 藉 由 執 行 垂 直 於 感 測 放 大 器 訂 行 而 非 平 行 於 感 測 放 大 器 行 的 全 局 I / 0 媒 而 存 取 〇 1 I m 而 寬 層 次 I / 0 設 計 的 一 個 問 題 是 行 冗 餘 〇 若 使 1 1 I 用 傳 統 的 冗 餘 9 則 所 需 的 冗 餘 行 的 數 g 係 正 比 於 I / 0 位 1 1 元 之 數 巨 0 此 問 題 將 與 另 一 行 冗 餘 方 案 一 起 詳 细 描 述 0 f 線 第 一 圏 顯 示 了 一 種 用 於 一 子 陣 列 的 傳 統 行 冗 餘 設 計 ί 1 I 該 子 陣 列 具 有 6 4 行 選 擇 線 ( C S L ) 1 0 及 兩 個 垂 直 執 1 ! i 行 的 備 用 行 選 擇 線 ( S C S L ) 1 2 0 各 行 選 擇 線 將 四 個 1 1 感 測 放 大 器 ( 頂 部 與 底 部 感 測 放 大 器 部 分 1 4 與 1 6 各 具 1 有 兩 個 感 測 放 大 器 ) 連 接 到 局 部 I / 0 線 對 1 8 與 2 0 0 1 [ 這 局 部 對 依 次 連 接 到 垂 直 的 全 局 I / 0 線 2 2 〇 此 傳 铳 1 I 設 計 相 當 昂 貴 » 寅 例 中 所 有 記 憶 格 的 3 % Μ 上 是 用 於 行 冗 1 1 I 餘 〇 -6- 1 1 1 1 本紙張尺度適用中國國家標準(CNS > A4規格(210X297公廣) 經濟部中央標隼局員工消費合作社印製 4i〇3°6 A7 B7__五、發明说明(ψ) 〔發明之概要] 本發明提供了一種藉由連接一鄰近的線以取代一有缺 陷的線,隨後移位Μ下線之連接的冗餘備用線的改進使用 。因此*各線無需自線組邊掾選擇—備用線路徑,而僅補 連接到其鄰近的媒Κ允許取代。於另一實施例中’多條相 鄰的線可互連,Μ在需要取代兩條有缺陷的媒之情形中允 許兩條線的移位操作。 藉由使用移位暫存器或其他電路來執行一類似的功能 ,當定址非缺陷線區域時,I/0線可Κ普通的方式連接 。當定址一有缺陷區域時,輸出可於試圈到逹有缺陷區域 的讀取或寫人之時移位(一般而言* 一連接到該線的有缺 陷記憶格或感測放大器為有缺陷者)。 於一較佳實施例中,備用的全局I /0線僅連接到兩 個感測放大器,各感測放大器位於簇的各側。兩備用的行 選擇線於該兩個感測放大器之間選擇。本發明無需連接到 同一全局I /0線的各姐行之備用•而僅需特殊全局I / 0線的一組備用線。於本發明之一實施例中,僅需要1/16 的備用行。 為進一步理解本發明之本質與優點,應作出结合附圖 之對Μ下描述之參考。 〔附圖簡要說明〕 I 裝 訂 腺 (請先閱讀背面之注項萝%寫本頁) 本紙張尺度適用中國國家標準(CNS ) A4i)t格(2丨ΟΧ297公釐} 經濟部中央標準局貝工消費合作社印製 410306 A7 ^ _B7__ 五、發明説明(f ) 第一圈是為一前技之行堪擇線的冗餘設計。 第二圖是為結合本發明之整體記憶體電路的示意團。 第三圖是為一示意圖,說明依據本發明對第一圓之前 技的變更。 第四與五圈是為示意圃》分別說明一軍移位與一雙移 位。 第六圃是為一更為詳细的示意围,頭示了本發明之移 位暫存器輸出電路。 第七圃是為用於第六困之移位暫存器的一個位元的移 位暫存器電路的更詳细示意圈。 第八圖是為用於備用位元之移位(或一雙位元移位) 的第七圖之移位暫存器電路的另一實施例示意圖。 第九圖是為一傅用I/◦選擇器電路的電路圖。 C發明之描述〕 第二圖顯示了一種適用於高帶寬都件之可能的蘑次陣 列结構。於該示意圖中,1 28條全局I/O線24垂直 地執行到位於底部的行I/O放大器2.. 6。依據本發明· 資料使用16涸八位元移位暫存器28而被多工到埴些故 大器V各個八位元移位暫存器用於各個資料接腳。此國中 並未顯示行冗餘。 該基本結構之各棰互換排列有可能提供不同的子陣列 尺寸、列解碼器位置、資料接脚、觸排計數等。所述的行 本紙張尺度適用中國國家標隼(CNS ) Α4規格(210X297公釐) ! I ! i 1 t _^ 訂"~ . * 备 (請先閲讀背面之注意事項/%寫本頁) 410306 A7 B7 經濟部中央標準局員工消費合作杜印製 五、發明説明 (y ) 1 1 1 冗 餘 設 計 可 很 容 易 地 適 用 這 些 變 化 的 任 意 —— 種 〇 * 1 1 1 第 三 圖 舉 例 說 明 使 用 本 發 明 將 I / 0 線 連 接 到 記 憶 陣 J 1 列 〇 第 三 圖 所 示 者 是 為 包 括 一 記 憶 格 陴 列 3 2 之 記 憶 子 陣 請 先· 閲 1 1 列 3 0 » 該 記 憶、 格 陣 列 3 2 是 由 兩 組 感 測 放 大 器 3 4 與 讀 背 1¾ 1 1 I 3 6 為 界 限 0 這 些 感 測 放 大 器 是 如 第 一 圖 所 示 連 接 到 全 局 之 注 意 1 1 I / 0 線 3 8 0 然 而 » 此 處 僅 有 6 4 條 行 選 擇 媒 4 0 被 使 I 項 1 I 再 1 I 用 免 除 了 第 圖 中 每 個 子 陣 列 需 要 兩 條 備 用 的 行 m 擇 媒 K % 本 1 裝 1 2 0 子 陣 列 3 0 最 好 於 一 積 體 電 路 中 重 複 八 次 〇 頁 w 1 I 依 據 本 發 明 備 用 線 是 由 位 於 八 線 子 陣 列 之 邊 緣 的 霄 1 路 4 2 來 提 供 〇 電 路 4 2 提 供 四 條 備 用 的 行 選 擇 線 4 4 與 1 ! 4 6 Μ 及 備 用 的 感 m 放 大 器 4 8 5 0 5 2 5 4 〇 訂 提 供 兩 條 備 用 的 全 局 I / 0 線 5 6 與 5 8 〇 1 | 於 移 位 冗 餘 設 計 中 9 使 用 少 量 的 備 用 I / 0 線 如 第 1 I 三 圖 所 示 0 不 同 於 連 接 到 每 個 子 陣 列 之 6 4 個 慼 測 放 大 器 1 1 I 中 一 個 的 一 正 常 的 全 局 I / 0 線 , 一 備 用 的 全 局 I / 0 線 1 線 僅 連 接 兩 個 感 測 放 大 器 f 各 位 於 簇 的 各 側 〇 兩 條 備 用 的 行 1 1 選 擇 線 於 該 兩 個 感 測 放 大 器 冬間 選 擇 〇 ( 或 者 可 K 使 用 1 1 各 用 於 上 下 感 測 放 大 器 的 兩 條 備 用 I / 0 媒 * 其 结 果 被 1 1 I 多 X 〇 ) 由 於 逭 些 感 測 放 大 器 位 於 陣 列 的 邊 嫌 不 必 於 感 1 1 測 放 大 器 的 狹 小 間 距 内 提 供 備 用 的 I / 0 與 備 用 的 C S L 1 1 訊 號 1 但 是 若 需 要 的 話 f 可 於 俘 獲 區 内 局 部 地 選 揮 備 用 的 ! I I / 0 與 備 用 的 C S L 訊 號 路 徑 〇 第 圈 顯 示 了 兩 處 該 等 1 I 備 用 儘 管 於 理 論 上 可 使 用 任 9- 數 的 備 用 Q 1 1 1 1 本紙張尺度適用中國國家標準{ CNS ) A4規格(2丨0X29?公釐) 經濟部中央標準局貝工消費合作社印製 410306 A7 B7五、發明説明(;;) 移位設計超出傅統設計之區域優點是顯而易見的。其 不需要連接到同一全局I / 〇線之各組行的備用線•而僅 済要用於特殊全局I /〇線的一姐備用線。舉例而言*僅 霈要1/1 6的備用行線(其他實施將獲得不同的節省) 〇 移位設計產生34個行I /0線的備用線*其中僅需 32條備用線。對於將要工作的冗餘,必須選擇備用1/ 0線之路徑Μ取代所需之處的有缺陷I/O線。I/O放 大器與資料移位暫存器之間的連接方式顧示於第六圖中。 第四、五圖舉例說明分别用於單移位與雙移位的移位 。第四圖顯示了多條I/O線41、43、45、47、 49、51 、53。於所示的S例中,一 I/O線45為 失效,或者其所連接之電路為失效。備用線為5 1與53 。該等I / 0線顯示為具有一對應的输出嫒衝器4 Ρ 、 4 3 y 、45' 、47/ 、49'。於所示的實例中·Ι /0線4 1與43連接到其對懕的輸出鑀衝器4 1 '與4 3 '。然而 > 失效的線4 5未連接。取而代之的是移位I /0線Λ 7,>乂提供輸出至媛衝器45'。類似地* 1/ ◦線49被移位,Μ提供其輸出至緩衝器47'。缓衝器 49'之輸出是由備用冗餘線51中的一條所提供。 第五圖顯示了一電路的更多部分,以舉例說明多重失 效。此圖中顯示了附加線33、35、37、39,Μ及 其對應的输出嫒衡器33' > 3 5 , 、37' 、39'。 -10- 本紙張尺度適用中國國家標準(CNS ) Α4規格(2丨0X297公釐) ! n J ~Ϊ I 訂 , . -¾¾ (諸先閱讀背面之注填寫本頁) 經濟部中央標準局員工消費合作杜印取 A7 B7 7、發明说明(涔) 於第五圖中所示的寅例中•於線37、43上存在失效。 因,可K見及,線33與35完全未被移位。而線39 、41均被移位一處至媛衝器37'與39'。由於線4 3為失效•剩餘的線45、47、49被移過兩個嬢衝器 位置。最後,如前所述,使用連接至輸出級街器47'、 49'的冗餘線51、53。 移位操作與新的連接可K任一種方式於不同時刻進行 。當偵測到缺陷時*保險絲可燒斷以重新進行路徑選擇並 移偉線,因此有效地儲存了缺陷資料。或者*可使用一儲 存缺陷定位的記憶體*其於存取到一有缺陷之I /0線時 動態地將備用線移位到I /媒,從而具有使用所儲存之錯 誤資料的動態移位。於該一實施中*不使用保險躲*而可 使用一 AND閘,其具有來自埋輯内適當位置處之記憶體 的一個輸人端。 缺陷有可能發生在多個位置。例如|缺陷可發生於格 本身内、行線内、或I/O線內。若缺陷是在前兩者中· 則移位操作取決於所存取之行線是杏具有缺陷。若缺陷是 在I / 0線中,則移位操作將始終箱要發生。 第六圖顯示了全局I /0線3 8M及備用的全局I / 0線56與58。這些I/O線是提供給1/020個謓 取/寫入(R/W)放大器60與備用的I/O放大器6 2。其提供四個移位暫存器6Λ、66、68、70,K 及一個2位元的拥轼移位暫存器7 2。逋些移位暫存器插 -11- 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 2们公釐) I ! I I I 批衣- - I -ITtl —1 n (銪先閲讀背面之注$項声.4寫本頁) 經濟部中央榡牟局員工消费合作社印製 410306 A7 B7 五、發明说明(7 ) 入到I/〇放大器與連接至線74之積體電路的寅料I/ 0焊墊之間。 於正常操作時•速接至移位暫存器64用於位元0 : 7的I/O線76是經由8位元移位暫存器64¾接,無 箝移位。然.而,當定址一有缺陷的DRAM區域時,控制 移位暫存器,以移位I/O線。例如,若位元線6為有缺 陷時,其將被禁能*位元線位到其位置*且來自毗鄰 姐的位元線8车線7 8上移入。所有剰餘的線亦將移位, 其一條備用線於線8 0之一條的端部處移入。若於同一定 \ 址區(同一行)中遇到另一條有缺陷的線,則所有位置需 要一第二移位,移至該第二有缺陷線的右方,其中於線8 0上將移入兩條備用線。 除了最右邊的移位暫存器位元,所有的移位暫存器位 元均是連接到兩個訊號;直接位於上方的謓取一寫入資料 (RWD)線與右邊的RWD線。用於控制哪條線連接至 輸入或輸出移位暫存器的電路顯示於第七圖中。 第七圖顯示了一If位茜移位器電路8写,其是對應 於一單個位元之電路6 4 — 7 2中一個電路的一部分。例 如*這八個電路將含括於移位器64中。如画所示,此特 殊的位元1 0於兩不同的I / 0線84與86之間理擇, 其是為第六圖之I/O線76、78或80中特殊的一個 位元。開關88與90分別是由一控制線9 2以及一反相 器94來控制,該等開闞確保兩條線中僅有一條是連接到 -12- 本紙張尺度適用中國國家榡率(CNS ) Λ4規格(210X 297公釐) I ] _ —批私-'^~ ' β (請先1¾讀背面之注意事項/.填寫本頁) A7 B7 經濟部中央標隼局員工消費合作社印製 五、發明説明U °) 1 1 I 位 元 移位器 霉 路 8 2 〇 1 I 1 控制線 9 2 之控 制訊號 是 由 保 險絲 9 4 與 9 6 來 控 制 r—S 1 I I 保 險絲9 4 與 9 6 透過〃 及 // 閘 9 8 與 1 0 0 以 及 請 先 閱 1 I 或 閘1 0 2 耦 連.。 當一對 應 於 有 缺陷 位 址 之 位 址 出 現 於 讀 背 面 1 1 I 控 制 線1 0 4 與 10 6上時 > 這 些 保險 絲 的 狀 態 使 I / 0 1 | I 線 移 位。這 牲 控 制線 是為備 用 選 擇 器, 當 - 位 址 對 應 於 有 事 項 1 1 缺 陷 位址時 % 其 為現 用者。 該 等 保 險綠 在 對 應 於 有 缺 陷 I -r 寫 本 1 裝 / 0 線的位 置 及 該等 位置之 右 方 處 將適 當 地 燒 斷 〇 I •«w1 1 I 若備用 選 擇 器中 的一個 為 現 用 且該 位 元 位 置 的 保 險 絲 1 已 焴 斷時, 則 移 位器 是連接 到 位 元 位置 η + 1 0 若 備 用 選 1 1 擇 為 高或者 用 於 一現 用備用 的 保 險絲 尚 未 燒 斷 則 使 用 訂 m 定 的R W D 線 η ° 1 I 用於最 右 方 位元 (第八 圔 ) 之 控制 為 類 U 者 * 除 了 其 1 1 是 連 接到兩 條 備 用線 。若對 應 的 備 用選 擇 器 被 觭 發 則 使 1 1 用 備 用的I / 0 線Μ 取代穩 定 的 R W D 線 0 I 線 當允許兩 處 移位 ,Κ置 入 兩 條 不同 的 傅 用 線 時 可 使 1 I 用 — 類似於 第 八 _之 電路。 如 圖 所 示, 亨移位 路 1 0 1 I 8 -是 經由開 關 1 1 0 ' 11 2 、 1 1 4 而 連 接 到 三 條 不 同 1 1 的 I / 0線 〇 根 據控 制訊號 可 完 成 一條 或 兩 條 線 的 移 位 0 1 1 —搮準 備 用 I / 0選擇 器 電 路 可用 於 控 制 其 實 例 顯 1 I 示 於 第九圖 中 0 此特 殊的霉 路 將 取 代所 有、觸 排 内 相 同 的 行 1 I 位 址 :觸排 堪 擇 能力 可藉由 複 製 此 霣路 加 入 用 於 鵑 排 位 1 1 址 之 特殊保 險 絲 、並 將结果 一 起 作 理梅 或 (or)來 獲 得 0 1 | -13- 1 1 本紙張尺度適用中國圉家標準(CNS ) Λ4说格(2丨0X297公釐) A7 410306 B7This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210 297 mm) I ^ κ I ~ Order I 矣 i Read the precautions on the back to write this page) Central Standards Bureau of the Ministry of Economic Affairs, Paige Consumer Cooperative Press 410306 Α7 Β7 i. Description of the invention (>) There may be 2 bits in a 1 M bit DRAM, each block includes-a dedicated array of Y decoders with 2 redundant decoders * each block has two arrays , Each Y decoder has 2 outputs * and each array has 2 data buses. The redundant columns and / or redundant rows of the memory cells are set to replace the defective main memory array columns and / or rows found during testing (such as wafer sorting). In general, the redundant columns and / or redundant rows have an initially unspecified address M and a redundant decoder coupled thereto. The redundant decoder is programmable, and M matches the addresses of the columns and / or rows identified as defective. The defective columns and / or rows are then disabled. During operation > When performing a memory fetch or write cycle, access to these defective columns and / or rows can be prevented * and redundant decoders only respond to these defective columns and / or rows The address of the (or) row * thus effectively replaces the defective column and / or row with the redundant column and / or row. The redundant column and / or row is sometimes referred to as the spare column and ( Or) OK. A typical implementation of a programmable redundant decoder is a one-bit decoder, where a polycrystalline silicon fusible link (ie, insurance green) is a bit line connected to a column or row address element weigher Depending on whether the redundant decoder is a redundant column or a redundant row. In order to plan a redundant decoder with a row or column address of a memory cell with a defective memory cell *, the selected person in 绦 is switched off / off. • For example, with the help of a laser. An example of redundant row circuits is proposed in U.S.A. No. 5,325,33 4. U.S. Patent No. 5,469,401 discusses the ability to assign a seedling to a single array. The paper size is applicable to the Chinese National Standard (CNS) A4 (2 丨 0 X 297 mm). Binding-sC,. (Please read the note on the back first Matters-? &Amp; copy-bought) A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shelley Consumer Cooperative, V. Invention Description () I 1 1 Redundant Row Circuits Not All Arrays US Patent No. 5, 4 6 7, 655 No.! 1 1 A redundant line circuit that can reduce the number of fuses g. 〇1 | On top of the 16 mega DRA Μ technology, the memory array is divided into multiple clusters. Please read 1 | The addition of the global I / 0 line connected to the I / 0 line is read back 1 1 side 1 down 9 which originally had been directly entered into the integrated circuit I / in the previous structure | Note I 0 0 etc. The global I / 0 line is generally parallel to the row rational line »and perpendicular to the Hua Xiang 1 Then I will use the I / 0 of each cluster to sense the I / 0 of the main device. Therefore, it provides a kind of I / 0 structure of level 1 writing. Page 1 I / 0 structure of I level can be used for DR of 64M bits and above. AM provides the potential of cheap high-frequency DRA M cores. It allows the amplifiers of the same sub-array to perform a global I by executing a global I sub-array instead of parallel to the sense amplifier rows. / 0 media access 0 1 I m One problem with the wide-level I / 0 design is row redundancy. If 1 1 I uses conventional redundancy 9, then the number of redundant rows g is proportional to I / 0 bit 1 The number of 1 yuan is huge. This problem will be described in detail with another row redundancy scheme. 0 f line The first line shows a traditional row redundancy design for a subarray. 1 I This subarray has 6 4 line selection lines (CSL) 1 0 and two alternate row selection lines (SCSL) for 1! I rows 1 2 0 Each row selection line will be four 1 1 sense amplifiers (top and bottom sense amplifier sections 1 4 and 1 6 each with 1 yes Two sense amplifiers) are connected to local I / 0 line pairs 1 8 and 2 0 0 1 [this local pair is connected to the vertical global I / 0 line 2 2 in sequence. This transmission 1 I design is quite expensive »In the example 3% of all memory cells are used for line redundancy 1 1 I more than 0-6- 1 1 1 1 This paper size applies to Chinese national standards (CNS > A4 size (210X297)) Employees of the Central Bureau of Standards, Ministry of Economic Affairs Printed by Consumer Cooperatives 4i0 ° 6 A7 B7__ V. Description of the Invention (ψ) [Summary of Invention] The present invention provides a method for replacing a defective line by connecting an adjacent line, and then shifting it to offline. Improved use of connected redundant spare lines. Therefore, * each line does not need to choose from the line group side-the spare line path, but only the supplementary media K connected to its neighbor is allowed to replace. In another embodiment, 'a plurality of adjacent lines may be interconnected, and M allows a shift operation of the two lines in the case where it is necessary to replace two defective media. By using a shift register or other circuit to perform a similar function, I / O lines can be connected in the usual way when addressing non-defective line areas. When addressing a defective area, the output can be shifted from the test circle to the reading or writing of the defective area (generally * a defective memory cell or sense amplifier connected to the line is defective By). In a preferred embodiment, the spare global I / 0 line is connected to only two sense amplifiers, each sense amplifier being on each side of the cluster. Two spare row selection lines are selected between the two sense amplifiers. The present invention does not need a spare line of each sister line connected to the same global I / 0 line, but only a group of spare lines of a special global I / 0 line. In one embodiment of the present invention, only 1/16 spare rows are required. In order to further understand the nature and advantages of the present invention, reference should be made to the following description in conjunction with the drawings. [Brief description of the drawings] I Binding gland (please read the note on the back side to write this page) This paper size is applicable to the Chinese National Standard (CNS) A4i) t grid (2 丨 〇297mm) Printed by the Industrial and Consumer Cooperatives 410306 A7 ^ _B7__ V. Description of the Invention (f) The first circle is a redundant design of a selectable line for a previous technology trip. The second figure is a schematic group of the integrated memory circuit of the present invention The third figure is a schematic diagram illustrating the changes to the previous technique of the first circle according to the present invention. The fourth and fifth circles are to indicate the garden. For a detailed schematic view, the shift register output circuit of the present invention is shown in the head. The seventh garden is a bit shift register circuit for one bit of the sixth shift register. A detailed schematic circle. The eighth figure is a schematic diagram of another embodiment of the shift register circuit for the seventh bit shift (or a two-bit shift) of the seventh bit. The ninth figure is for The circuit diagram of the first I / ◦ selector circuit. C Description of the invention] The second figure shows a A possible mushroom array structure suitable for high-bandwidth components. In this diagram, 1 28 global I / O lines 24 are executed vertically to the bottom row I / O amplifiers 2 .. 6. According to the present invention. Data The 16 涸 octet shift register 28 is used to multiplex to some old devices V. Each octet shift register is used for each data pin. Row redundancy is not shown in this country. The basic structure The interchangeable arrangement of each frame may provide different sub-array sizes, column decoder positions, data pins, touch row counts, etc. The paper size mentioned applies to the Chinese National Standard (CNS) Α4 specification (210X297 mm) ! I! I 1 t _ ^ Order " ~. * Preparation (please read the precautions on the back /% write this page) 410306 A7 B7 Printed by the Consumers' Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. 1 1 1 Redundant design can be easily applied to any of these changes-Kind 0 * 1 1 1 The third figure illustrates the use of the present invention to connect the I / 0 line to the memory array J 1 column. The one shown in the third figure Is for bag A memory sub-array 3 2 of the memory sub-array please read · 1 1 row 3 0 »The memory, grid array 3 2 is composed of two sets of sense amplifiers 3 4 and read back 1¾ 1 1 I 3 6 is the limit 0 these The sense amplifier is connected to the global attention as shown in the first figure. 1 1 I / 0 Line 3 8 0 However »Only 6 of the 4 line selection media here 4 0 are enabled I item 1 I then 1 I In the figure, each sub-array requires two spare rows. M Selective medium K% Ben 1 1 2 0 Sub-array 3 0 It is best to repeat eight times in an integrated circuit. Page w 1 I According to the present invention, the spare line is composed of Xiao 1 on the edge of the eight-wire sub-array 4 2 to provide 0 circuit 4 2 to provide four spare row selection lines 4 4 and 1! 4 6 Μ and spare sense amplifier 4 8 5 0 5 2 5 4 〇 order Provides two spare global I / 0 lines 5 6 and 5 8 〇1 | In shift redundant design 9 uses a small amount of Use I / 0 line as shown in Figure 1 I. 3 is a normal global I / 0 line different from one of the 6 4 sense amplifiers 1 1 I connected to each sub-array, and a spare global I / 0 Line 1 Line only connects two sense amplifiers f each on each side of the cluster 〇 Two spare rows 1 1 Select a line to choose between the two sense amplifiers in winter 〇 (or K can be used 1 1 each for up and down sensing Two spare I / 0 media of the sense amplifier * The result is 1 1 I more X 〇) Because some sense amplifiers are located on the edge of the array, it is not necessary to provide spare I / 0 and Spare CSL 1 1 signal 1 But if needed, f can be selected locally in the capture area! II / 0 and spare CSL signal path. The circle shows two such 1 I spares, although theoretically possible Use any 9-number backup Q 1 1 1 1 This paper size applies to the Chinese National Standard {CNS) A4 specification (2 丨 0X29? Mm) Printed by the Shell Industry Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 410306 A7 B7 V. Description of the invention (;;) The regional advantages are obvious. It does not need a spare line connected to each group of rows of the same global I / 〇 line, but only a sister spare line to be used for a special global I / 〇 line. For example * only 1/1 6 spare line is required (other implementations will get different savings) 〇 The shift design produces 34 spare I / 0 line spare lines * of which only 32 spare lines are required. For the redundancy to be operated, the path M of the spare 1/0 line must be selected to replace the defective I / O line where needed. The connection between the I / O amplifier and the data shift register is shown in Figure 6. The fourth and fifth figures illustrate the shifts for single shift and double shift respectively. The fourth figure shows multiple I / O lines 41, 43, 45, 47, 49, 51, 53. In the example S shown, an I / O line 45 is disabled, or the connected circuit is disabled. Spare lines are 5 1 and 53. The I / 0 lines are shown as having a corresponding output punch 4P, 43y, 45 ', 47 /, 49'. In the example shown, the I / 0 lines 4 1 and 43 are connected to their opposing output punches 4 1 ′ and 4 3 ′. However > Failed lines 4 5 are not connected. Instead, a shift I / 0 line Λ 7 is provided, > 乂 provides an output to the yuan punch 45 '. Similarly * 1 / ◦ line 49 is shifted and M provides its output to buffer 47 '. The output of the buffer 49 'is provided by one of the backup redundant lines 51. The fifth figure shows more parts of a circuit to illustrate multiple failures. This figure shows the additional lines 33, 35, 37, 39, M and their corresponding output scales 33 '> 3 5, 37, 39'. -10- This paper size applies to China National Standard (CNS) Α4 size (2 丨 0X297 mm)! N J ~ Ϊ I order,. -¾¾ (please read the note on the back to fill in this page) Staff of Central Bureau of Standards, Ministry of Economic Affairs Consumption Cooperation Du Yin take A7 B7 7. Invention Description (涔) In the example shown in the fifth figure, there is a failure on lines 37 and 43. Therefore, it can be seen that the lines 33 and 35 have not been shifted at all. The lines 39, 41 are shifted to the Yuan punches 37 'and 39'. Since line 4 3 is ineffective • The remaining lines 45, 47, 49 have been moved through two punch positions. Finally, as mentioned before, the redundant lines 51, 53 connected to the output stage street 47 ', 49' are used. The shifting operation and the new connection can be performed in different ways at any time. When a defect is detected * the fuse can be blown to re-route and move the conductor, thus effectively storing defect data. Or * can use a memory that stores defect location * which dynamically shifts a spare line to the I / media when accessing a defective I / 0 line, thereby having a dynamic shift that uses the stored incorrect data . In this implementation * an insurance gate can be used * without using insurance dodge, which has an input terminal from memory at an appropriate position in the memory. Defects can occur in multiple locations. For example, | defects can occur in the cell itself, in the line, or in the I / O line. If the defect is in the first two, then the shift operation depends on whether the line being accessed is defective. If the defect is in the I / 0 line, the shift operation will always occur. The sixth figure shows global I / 0 lines 38M and spare global I / 0 lines 56 and 58. These I / O lines are provided to 1/020 of a fetch / write (R / W) amplifier 60 and a spare I / O amplifier 62. It provides four shift registers 6Λ, 66, 68, 70, K and a 2-bit crowd shift register 72. Some shift registers are inserted-11- This paper size is applicable to China National Standard (CNS) A4 specification (210 X 2 mm) I! III batch--I -ITtl —1 n (read the first Note $ Item sound.4Write this page) Printed by the Consumer Cooperatives of the Central Government Bureau of the Ministry of Economic Affairs 410306 A7 B7 V. Description of the invention (7) Input to the I / 〇 amplifier and the integrated circuit connected to line 74 I / 0 pads. During normal operation • The I / O line 76, which is connected to the shift register 64 for bits 0: 7, is connected via the 8-bit shift register 64¾, without shifting. However, when a defective DRAM area is addressed, the shift register is controlled to shift the I / O line. For example, if bit line 6 is defective, it will be disabled * bit line to its position * and bit line 8 from line 7 8 from the next sister will be moved in. All remaining lines will also be shifted, with one spare line moving in at the end of one of the lines 80. If another defective line is encountered in the same addressing area (same line), all positions need a second shift to the right of the second defective line, where Move in two spare lines. Except for the rightmost shift register bit, all the shift register bits are connected to two signals; the grab-and-write data (RWD) line directly above and the RWD line on the right. The circuit used to control which line is connected to the input or output shift register is shown in Figure 7. The seventh figure shows an If-bit shifter circuit 8 write, which is part of a circuit corresponding to a single bit circuit 6 4-72. For example * these eight circuits will be included in the shifter 64. As shown in the drawing, this special bit 10 is chosen between two different I / 0 lines 84 and 86, which is a special bit among the I / O lines 76, 78 or 80 in the sixth figure. . The switches 88 and 90 are controlled by a control line 92 and an inverter 94, respectively. These openings ensure that only one of the two lines is connected to -12- This paper standard applies to China's national standard (CNS) Λ4 specification (210X 297 mm) I] _ — Approval-'^ ~' β (Please read the precautions on the back / fill in this page first) A7 B7 Printed by the Consumers' Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs Description of the invention U °) 1 1 I bit shifter mold circuit 8 2 〇1 The control signal of I 1 control line 9 2 is controlled by fuses 9 4 and 9 6 r—S 1 II fuse 9 4 and 9 6 through 〃 and // Gate 9 8 is connected with 1 0 0 and please read 1 I or Gate 1 0 2 first. When a pair of addresses corresponding to a defective address appears on the read back 1 1 I control lines 1 0 4 and 10 6 > The status of these fuses shifts the I / 0 1 | I line. This control line is a backup selector, when -address corresponds to the event 1 1 defective address% it is the current user. These insurance greens will be properly blown at the positions corresponding to the defective I -r copybook 1 pack / 0 line and to the right of those positions. 0I • «w1 1 I if one of the spare selectors is active and When fuse 1 at this bit position is broken, the shifter is connected to bit position η + 1 0. If the spare option 1 1 is set to high or the fuse for an active spare has not blown, use the order m. The RWD line η ° 1 I is used for U-like control of the rightmost azimuth element (eighth 为) * except that 1 1 is connected to two spare lines. If the corresponding spare selector is issued, make 1 1 replace the stable RWD line with a spare I / 0 line M. 0 I line allows two shifts, and puts 1 when two different Fu lines are inserted. I use — similar to the eighth circuit. As shown in the figure, Hengyi Road 1 0 1 I 8-is connected to three different 1 1 I / 0 lines via switches 1 1 0 '11 2, 1 1 4. One or two can be completed according to the control signal Line shift 0 1 1 — 1 I / 0 selector circuit can be used to control its example. 1 I is shown in the ninth figure. 0 This special mold path will replace all the same rows in the touch bar. 1 I bit Address: The optional ability to touch the bank can be obtained by copying this path and adding a special fuse for the cuckoo rank 1 1 address, and combining the results as a plum or (or) to obtain 0 1 | -13- 1 1 paper The scale is applicable to the Chinese Standard (CNS). Λ4 grid (2 丨 0X297 mm) A7 410306 B7
五、發明説明(i U ,(請先Μ讀背面之注意事項濟^舄本頁) 為了取代位元位置m處I / 0線之一指定行位址,備 用的I / 0選擇器程式該位址。對於j大於或等於m處的 所有保險絲F〇 <j>$F i <j>亦規斷。此舉將専致I / 0 線到達欲被正常壤接之m的左側•其右方的I / 0線左移 1。I/O線m本身並未用於此行位址。 K上的實施是為基本冗餘概念的一個實例。冗餘概念 存在許多可能的變化,其中一些將在此部分中描述。 於圖式所示的S例中,I/O線被分離為32條一姐 K供冗餘。為達到特佳的效率亦可增加這些姐的I / 0線 數*或者為達到特佳的靈活性亦可減少這些組的I /0媒 數,其是取決於所期望的位元失效型式。 画式之實例中所使用的移位暫存器並不允許取代用於 同一行位址(SP〇與SPi必須用於不同的行)之兩條1/ 0線。達成此目的的一種實施是可能的;各位元位置必須 支持移1位或移2位。 經濟部中央標準局貝工消費合作社印聚 此一實施需要η— 1條保險絲(實例中為3 1條)以 指出那一條I / 0線將被取代。同樣的訊息可在log(n-l)條 保險絲中編碼•若保險絲區域是為高值,則具有附加的理 輯Μ將二進制位置值轉換到所需的溫度計碼。 热悉此項技S之人士應當理解,本發明可實施為未脫 離本發明之精神與内在特質的其他特定的形式。例如*本 發明之移位操作的冗餘設計不僅可應用於全局I/0媒, 且可應用於子陣列中的行線、或字線。因此,前文的描述 -14- 本紙張又度適用中國國家標準(CNS ) Μ規格(2丨0 X 29?公釐) 經濟部智慧財產局員工消費合作杜印製 410306 A7 _B7_ 五、發明說明() 僅為說明性,而並未限定於K下串請專利範圍内提出之本 發明的範羈。 元件符號說明 30 記憶子 陣 列 Ο Λ 0 ά 記憶格 陣 列 34 33 56 58 全局ί/0線 40 44 4 6 行選擇 線 48 50 52 54 感測放 大 器 41 4 3 45 47 49 5 1 53 I/O線 δΐ 53 備甩線 4 1 1 '43 > 45 ' 47, 43 ' 輸出鍰 衝 器 51 〇± m 渑用几 餘 媒 33 35 37 38 附加線 8 4 66 8 〇 70 移位暫 存 器 72 測試移 位 暫 存 器 82 覃假位 元 移 位 器電路 84 86 I/O線 3 8 90 開關 9 2 控制線 34 S6 谋險線 98 100 及閛 i(K i 或閛 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I.----------- I 少衣--------訂---------線 . {請先閲讀背面之泫意事項再填寫本頁) 89 經濟部智慧財產局員工消費合作社印製 410306 A7 ___B7_ 五、發明說明() 1 0 4 1 0 6 控制線V. Description of the invention (i U, (please read the precautions on the back of this page first) ^ This page) In order to replace one of the I / 0 lines at the bit position m to specify the row address, the spare I / 0 selector program should Address. For all fuses where j is greater than or equal to m, F 0 < j > $ F i < j > is also a rule. This will cause the I / 0 line to reach the left side of m to be normally soiled • The right I / 0 line is shifted to the left by 1. The I / O line m itself is not used for this row address. The implementation on K is an example of the basic concept of redundancy. There are many possible changes to the concept of redundancy, Some of them will be described in this section. In the example of S shown in the figure, the I / O lines are separated into 32 one-sister K for redundancy. To achieve the best efficiency, I / O of these sisters can also be increased. The number of lines * or to achieve excellent flexibility can also reduce the number of I / 0 media for these groups, which depends on the expected bit failure pattern. The shift register used in the example of the drawing is not It is permissible to replace two 1/0 lines for the same row address (SP0 and SPi must be used in different rows). An implementation to achieve this is possible; each meta position must be Supports shifting by 1 or 2. It is required that η—1 fuse (31 in the example) be used to indicate the implementation of the printing and gathering of the Bayer Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs to indicate which I / 0 line will be replaced. Similarly The message can be encoded in the log (nl) fuse. • If the fuse area is high, there is an additional logic to convert the binary position value to the required thermometer code. Those who know this technology should understand The invention can be implemented in other specific forms without departing from the spirit and inherent characteristics of the invention. For example, the redundant design of the shift operation of the invention can be applied not only to global I / 0 media, but also to sub-arrays Line, or word line. Therefore, the previous description -14- this paper is again applicable to the Chinese National Standard (CNS) M specifications (2 丨 0 X 29? Mm) printed by the consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs 410306 A7 _B7_ V. The description of the invention () is only illustrative, and is not limited to the scope of the present invention within the scope of the patent application under K. Symbol description 30 memory sub-array 0 Λ 0 ά memory grid array 34 33 56 58 Global ί / 0 line 40 44 4 6 line selection line 48 50 52 54 sense amplifier 41 4 3 45 47 49 5 1 53 I / O line δΐ 53 spare line 4 1 1 '43 > 45 '47, 43 'output buffer 51 〇 ± m 几 using several media 33 35 37 38 additional line 8 4 66 8 〇70 shift register 72 test shift register 82 Qin bit shifter circuit 84 86 I / O line 3 8 90 Switch 9 2 Control line 34 S6 Trouble line 98 100 and 閛 i (K i or 閛 -15- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I .----------- I Little Clothes -------- Order --------- Line. {Please read the notice on the back before filling this page) 89 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 410306 A7 ___B7_ V. Description of Invention () 1 0 4 1 0 6 Control Line
G 8 ο I 8 路電 位移關單開 (請先閱讀背面之注意事項再填寫本頁) 4---- 訂------- 線 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)G 8 ο I 8 Electric Displacement Closed Single Open (Please read the precautions on the back before filling this page) 4 ---- Order ------- The size of the wire paper is applicable to China National Standard (CNS) A4 (210 X 297 mm)