TW476858B - Liquid crystal display device - Google Patents

Liquid crystal display device Download PDF

Info

Publication number
TW476858B
TW476858B TW087102997A TW87102997A TW476858B TW 476858 B TW476858 B TW 476858B TW 087102997 A TW087102997 A TW 087102997A TW 87102997 A TW87102997 A TW 87102997A TW 476858 B TW476858 B TW 476858B
Authority
TW
Taiwan
Prior art keywords
electrodes
electrode
bulge
liquid crystal
crystal display
Prior art date
Application number
TW087102997A
Other languages
English (en)
Inventor
Motoji Shiota
Kiyoshi Inada
Hirokazu Yoshida
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW476858B publication Critical patent/TW476858B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13452Conductors connecting driver circuitry and terminals of panels
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/14104Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/0665Epoxy resin
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811Extrinsic, i.e. with electrical conductive fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03Conductive materials
    • H05K2201/0332Structure of the conductor
    • H05K2201/0364Conductor shape
    • H05K2201/0367Metallic bump or raised conductor not used as solder bump
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709Staggered pads, lands or terminals; Parallel conductors in different planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

476858 A7
A7
餘部分隱藏於電極片4後方,如圖丨〇所示)。 下文描述習用液晶顯示裝置300,其中液晶顯示面板3及 用以驅動液晶顯示面板3之驅動器1C 1係藉異.方性導電性 黏著劑2而以面朝下之方式連接。 參照圖10,於驅動器IC i上形成多個電極片4(電極片4 <其餘部份係隱藏於電極片4之後方,如圖1 〇所示)。各 電極片4係具有突起狀之隆突電極5。一對基板3 &及3 b之 一,即基板3 a ,具有對應於個別電極片4之多個結合片 6。 、'口 圖1 1係為沿圖9中箭頭2 0所示方向觀看習用液晶顯示裝 置300之剖面圖。圖1 2係為圖1 1中5〇D部分之實例之部分 放大圖’其中該電極片4係沿著與其對正方向垂直之方向 觀看。 參照圖1 2,如前文所述,該多個電極片4及該多個結合 片6個別對正,以於一對一之方式彼此對應。每個電極片4 皆具有一個隆突電極5 ^隆突電極5及結合片6係藉異方性 導電性黏著劑2彼此電性連接,該黏著劑係為整體分散有 導電性粒子7之絕緣黏著劑8。 根據使用異方性導電性黏著劑2之方法,包含於異方性 導電性黏著劑2中之導電性粒子7係夾置於驅動器IC i之隆 突電極5與液晶顯示面板3之結合片6之間並與彼接觸,而 於驅動器1C 1與液晶顯示面板3之間提供電性連接。此種 結構有利於例如使介於驅動器1C 1與液晶顯示面板3之間 之電性連接部分間距僅與隆突電極5之大小有關,而於相 -5-本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) A7 B7 ) 五、發明説明(3 ^隆突电極5之P㈣中充填絕緣黏著劑8,以於彼處提供充 分絕緣性。因為此等優點,故使用異方性導電性黏著劑2 之方法於COG系統中變得極為重要。 於則述習用液晶顯示裝置中,為了縮短相鄰電極片4之 間距以減少裝置驅動器IC i所需之面積,將各電極片4之 形狀凋成矩型等形狀,使電極片4之較短邊對正於對正方 白而且’為了使相鄰電極片4之間距更短,相鄰電極片4 可於與電極片4之對正方向垂直之方向交錯,而形成鋸齒 狀排列。 參照圖13 A及13B ’如下形成習用液晶顯示裝置3〇〇之隆 突電極5。首先,於具有多個電極片4之驅動器…1上施加 光阻1 〇〇。光阻丨00較所形成之隆突電極5之厚度厚約數微 米至約5微米。如圖1 3 A所示,光阻1 〇〇曝光並顯影,留下 欲形成隆突電極5之開口。該開口之形成方式係一個開口 對應於一個電極片4。之後,將驅動器IC i具有光阻1〇〇之 表面浸入電鍍溶液(例如A u溶液)中。浸於電鍍溶液中之 電極與驅動器IC i之間通過適量電流,使All沉積於該開 口中,如圖13B所示。電鍍後’去除光阻100,以於各電 極片4上形成隆突電極5。 然而,如前文所述般形成之隆突電極5具有諸如視光阻 100中開口之條件或其電鍍溶液之條件而定之電鍍無法持 續之問題。此情況導致隆突電極5喪失或高度不均勾。例 如,使電鍍溶液循環,而使該開口内具有電鍍溶液。然 而,於循環期間,可能產生阻斷該開口而阻止該電鍍持續 -6 - 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐) A7
(沉積)之凹洞(即氣泡),而使隆突 外,光阻loom水*» π 电極5炙向度降低。此 t 光掩模中存有粉塵,則可能嚴曝 先I不足而播法形成足量開口,以 如圖10及12所示,其中隆突電極5未喪失二5… 之緊隆突電極5與結合片6之間,並與 緊在地接觸,而於其間提供電性連接。 圖二4係為圖9中50。部分之另一個實 於0 1 4所-、π 向硯看(而其餘電極片4則隱藏 =電極片4之後方)。圖15係為圖"中-部 正方分放大圖,纟中電極片4係自與其對 万向觀看。於圖14及15中,導電性粒子7係 夬置於隆突€極5與結合片6之間,但未接觸,因此,其中 並供電流,造成連接失敗。 、 發明簡述 明,液晶顯示裝置包括具有線路圖型之基板, 、·-導電層而電性連接於該線路圖型之電路元件。該線 路圖型具有至少一個結合片。該電路元件具有至少一個電 極片。該至少一個電極片上層具有多個隆突電極。該至少 一個電極片係經由導電層電性連接於該至少一個結合片, 該=層係位於該多個隆突電極與面對於該多個隆突電極 之結合片之間’其中該導電層係為整體上分散有導電性粒 子之絕緣材料。 二 於本發明之一具體實例中 微米或更大。 相鄰隆突電極之間隔係約5 本紙張尺度適财iiii^CNS) A4規格(21GX297公爱) 476858 A7 B7 五、發明説明(5 ) 於另一個本發明具體實例中,液晶顯示裝置包括多個電 極片。該多個電極片各具有長邊及短邊。該多個電極片係 對正於與電極片短邊平行之方向。該多個隆突電極係對正 於使該多個電極片之各個長軸平行之方向。 另一個本發明具體實例中,液晶顯示裝置包括多個電極 片。該多個電極片係排列成鋸齒狀,隆突電極之邊角經裁 切,使位於一電極片上之隆突電極之經裁切邊角大體上與 位於相鄰電極片上之隆突電極之經裁切邊角平行。 另一個本發明具體實例中,該多個隆突電極與結合片相 向之表面係排列成大體上與結合片之表面平行。 另一個本發明具體實例中,液晶顯示裝置包括多個電極 片及多個與該多個電極片相向之結合片。該多個結合片與 對應電極片之間藉由異方性導電性黏著劑所製造之單一導 電層提供電性連接。 另一個本發明具體實例中,位於基板上之線路圖型及電 路元件以面狀黏合方式而彼此電性連接。 另一個本發明具體實例中,該基板係為玻璃基板。 根據本發明,於位在電路元件上之多個電極片上各提供 多個隆突電極。因此,即使位於一電極片上之多個隆突電 極中之一未具有預定高度,例如,因電鍍持續失敗所致, 其餘隆突電極仍可於電路元件之電極片與液晶顯面板之 對應結合片之間提供電性連接。換言之,只要適當地形成 該多個隆突電極中之至少一個,則該電路元件之電極片及 該液晶顯示面板之結合片即可電性連接。 -8- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 裝 訂
476858
因為位於各電極片上之相鄰隆突電極之間隔係約5微米 或更大,故相鄰隆突電極不會在持續電鍍期間彼此短路。 因此,形成隆突電極以使彼此完全絕緣。 若例如將電極片製成距形以使間距縮短,電極片之短邊 對正於對正方向,隆突電極以於各電極片上對正於與電極 片長軸平行之方向為佳。如此一來,隆突電極之總面積則 夠大而有效率。 此外,為了使相鄰電極片之間距更小,相鄰電極片可於 與電極片對正方向垂直之方向上交錯,而形成鋸齒狀排 列。此情況下,可裁切該隆突電極之邊角(故該隆突電極 之形狀係為五邊形、七邊形等),使隆突電極位於一電極 片上之經裁切邊角大體上平行於相鄰電極片之隆突電極之 經裁切邊角。是故,位置最接近之隆突電極之間距可長至 即使電極片間距縮短仍足以避免相鄰電極片間之短路,而 增加電路元件與液晶顯示面板間之電性連接的可信度。或 者,藉著提供經裁切邊角以取代電極片間距之縮短,可增 加各隆突電極之面積。 本發明因而可得到提供一種液晶顯示裝置之優點,其中 電路元件之電極片與液晶顯示面板之結合片之間不會有電 性連接損壞之情況。 熟習此技藝者可於參照附圖閱讀並明瞭以下詳述下明白 本發明之此項及其他優點。 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
裝 訂
476858 A7 B7 五、發明説明(7 ) 附圖簡述 圖1係為顯示本發明液晶顯示裝置之剖面圖,其裝置有 用以驅動液晶顯示面板之驅動器I C ; 圖2係為圖1中50A部分之部分放大圖; 圖3係為顯示本發明液晶顯示裝置之剖面圖,自圖1中箭 頭4 0所示之方向觀看; 圖4係為圖3中50B部分之部分放大圖; 圖5係為50A部分之另一個實例之部分放大圖; 圖6係為50B部分之另一個實例之部分放大圖; 圖7 A及圖7 B係為剖面流程圖,各顯示製造本發明液晶 顯示裝置200之隆突電極之步騾; 圖8 A及8 B係為顯示隆突電極於本發明電極片上之排列 實例之平面圖; 圖9係為顯示習用液晶顯示裝置之剖面圖; 圖10係為圖9中50C部分之部分放大圖; 圖1 1係為顯示習用液晶顯示裝置之剖面圖,自圖9中箭 頭20所示之方向觀看; 圖12係為圖11中50D部分之部分放大圖; 圖13A及圖13B係為剖面流程圖,各顯示製造習用液晶 顯示裝置之隆突電極之步驟; 圖14係為圖9之50C部分之另一個實例之部分放大圖; 且 圖1 5係為圖1 1中50D部分之另一個實例之部分放大圖。 -10- 本纸張尺度適用中國國家標準(CNS) A4規格(210X297公釐) 裝 訂
476858 A7 B7 五、發明説明( 符號說明
1 驅動器1C 2 異方性導電性黏著劑 3 液晶顯示面板 3a,3b 基板 4 電極片 5 突起狀隆突電極 5a,5b 隆突電極 6 結合片 7 導電性粒子 8 絕緣黏著劑 2 0,4 0 箭頭 10,100 光阻 2 〇〇,3 0 0液晶顯示裝置 50A〜5 0D部分 較佳具體實例描述 下文係參照附圖藉說明例描述本發明,其 口奋立此a 仰叫參考編 思4曰相同組件。 圖1係為顯示本發明液晶顯示裝置200之剖面圖,其裝置 有用以驅動液晶顯示面板3之驅動器IC 1。圖2係為圖^中 50A部分之部分放大圖,其中電極片4係自其對正方向觀 看(其餘電極片4係隱藏於圖2所示之電極片4之後)。液晶 顯不裝置200包括多個位於驅動器IC 1表面上之電極片4。 每個電極片4皆具有隆突電極5a及5b,由諸如Au之金屬 11 本紙張尺度 _Tiiii^(CNS) A4^(21GX297公釐) 476858 A7 B7 五、發明説明(9
製k並對正於與電極片4之對正方向垂直之方向。基板 3a(其係為液晶顯示面板3之一對基板3 &及3b中之一)具有 多個結合片6,對應於位在驅動器ICi上之各電極片4。 圖3係為顯示該液晶顯示裝置之剖面圖,自圖丨中箭頭 40所不之方向觀看。圖4係為圖3中5〇B部分之部分放大 圖’其中該電極片4係自與其對正方向垂直之方向觀看。 如圖4所示,該多個電極片4及該多個結合片6係經對 正,以於一對一之方式下彼此對應。如前文所述,每個電 極片4皆具有隆突電極5 a及5 b (其中隆突電極5 a係隱藏於 隆突電極5b之後)。隆突電極“及讪與結合片6係經由異 方性導電性黏著劑2而電性連接,例如整體分散有導電性 粒子7之絕緣黏著劑8。該異方性導電性黏著劑2中所含之 導電性粒子7係夾置於隆突電極5a&5b與結合片6之間並 與彼接觸,以於驅動器IC i之電極片4與液晶顯示面板3之 結合片6之間提供電性連接。 度根據本發明’該異方性導電性黏著劑2可為但不限於環 乳ACF (異万性導電膜)。任何市售ACFs皆可用作異方性導 電性黏著劑2。根據本發明’導電性粒子7之粒徑約為3微 米。亦可使用粒徑約5微米之導電性粒子7。隆突電極5之 不均勻高度差以約3微米或較小為#,約!微纟或更小更 佳。隆突電極5《不均勻高度差大於3微米時,分教於異 性導電性黏著射之導電性粒子無法於驅動器K丨之隆突 電極5與液晶顯示面板3之結合片6之間提供電性連接,而 損及其間之可信度。隆突電極5之高度可藉習用方法測 -12 -
476858 A7 發明説明(10 量,諸如使用探針等物之接觸測量法、採用顯微鏡焦點之 非接觸測量法、及使用雷射易位測量裝置之非接觸測量 法。 電極片之不均勻高度差係為數十毫微米或更小。 於圖2及4中,隆突電極5 a及5b不喪失或無高度差。因 此,導電性粒子7係夾置於隆突電極5 a及5 b與結合片6之 間,並與彼緊密地接觸,而於驅動器Ic i之電極片4與液 晶顯示面板3之結合片6之間提供電性連接。 圖5係為50A部分之另一個實例之部分放大圖。圖6係為 50B部分之另一個實例之部分放大圖。 根據本發明,即使喪失隆突電極5a*5b中之任一者,例 如5 b,或如圖5及6所示般地具有不均勾隆突高度,只要 適當地形成隆突電極5a(即,只要適當地形成隆突電極& 及5b中之至少一個),則驅動器IC i與液晶顯示面板3仍彼 此電性連接。於圖5中,導電性粒子7夾置於隆突電極5 & 與結合片6之間並與彼接觸,而使驅動器IC i之電極片$電 性連接於液晶顯示面板3之結合片6上。顯然喪失隆突電2 5 a或具有不均勻隆突高度時亦然。此情況下,只要適當地 形成隆突電極5b,導電性粒子7夾置於隆突電極几與:合 片6之間並與彼接觸,而使驅動器Ic丨之電極片*電性連接 於液晶顯示面板3之結合片6上。 圖7 A及圖7 B係為剖面流程圖,各顯示製造本發明液晶 顯示裝置200之隆突電極5 a及5 b之步驟。 阳 參照圖7A及7B,如下形成液晶顯示裝置2〇〇之隆突電極
裝 訂
線 -13-
476858 A7 五、發明説明(11 5a及5b。首先,於具有多個電極片4之驅動器1(: 1上施加 光阻10。光阻10較所形成之隆突電極5a及5b之厚度厚約 數微米至約5微米。光阻丨〇曝光並顯影,留下欲形成隆突 電極5 a及5 b之開口。如圖7 A所示,每個電極片4具有兩 個對應於隆突電極5a&5b之開口。之後,將驅動器ic夏 具有光阻1 0之表面浸入電鍍溶液(例如A u溶液)中。浸於 電鍍溶液中之電極與驅動器Ic丨之間通過適量電流,使 Au沉積於該開口中,如圖7B所示。電鍍後,去除光阻 10,以於各電極片4上形成隆突電極5&及51)。 根據本發明,例如每個電極片4於光阻1〇中提供兩個開 〜果因例如氣泡充填該開口所致之隆突電極5 a及 5 b兩者生長與習用方法比較之失敗率係為··( &習用方法之 隆突電極生長失敗率)2χ(1/本發明液晶顯示裝置之驅動器 ic電極片數目)。例如,當本發明驅動器ic之電極片係由 240個接頭所組成,而習用方法之隆突電極生長失敗率係 為1%時,本發明隆突電極“及灿兩者之生長失敗率係為 〇·〇1% X 1/240,其極度低於習用液晶顯示裝置。 根據習用液晶顯示裝置,於光阻曝光期間若光掩模 有塵粒,貝》】即使塵粒之大小僅有該開口大小之_半, 該開口不;L,而喪失隆突電極。另一方面,根據本發明, 因為各電極片4上開口之總面積大於習用液晶顯示 故生長中之隆突電極之失敗率較低。 圖8A及8B係為顯示隆突電極於本發明電極 實例之平面圖。 f列 -14-
裝 訂
線 476858 A7 --------- B7 五、發明説明(12 ) 如圖8 A所tf ’机鄰隆突電極5 a及5 b之間隔e調至約5微 米或更大’以防止其於電鍍步驟期間短路。因此,形成之 電極5 a及5 b彼此完全絕緣。當相鄰隆突電極5 a及5 b之間 隔E並非5微米或更大時,無法適當地形成於電鍍步騾中 用以形成隔離隆笑之抗蝕劑。此情況下,形成之隆突電極 5 a及5b無法彼此隔離。 根據本發明液晶顯示裝置,為了使相鄰電極片4之間距 更短’相鄰電極片4可於與電極片4之對正方向垂直之方向 父錯’而形成鋸齒狀排列,如圖8 a及8 B所示。隆突電極 5a及5b之形狀可為正方形,如圖8a所示。或者,如圖8B 所示’可裁切遠隆突電極5a及5b之邊角(故該隆突電極5a 及5 b之形狀係為六邊形),使隆突電極5 b位於一電極片4 上之經裁切邊角大體上平行於隆突電極5&位於相鄰電極片 4上之t裁切邊角。結果’位於對角之邊角之最近間距ρ 2 大杰圖8 A所示之距離F〗,優點係進一步降低隆突電極5 a 及5 b之間產生短路之可能,而進一步改善液晶顯示裝置之 可信度。此外,可增加隆突電極5a&5b之面積,藉著使 距離F2等於距離Fi而保持圖8B之隆突電極5a及5b之形 狀’使其大於圖8A所示隆突電極5a及5b之面積,而增加 電性連接之可信度。 或者’當隆突電極5a及5b經裁切使其形狀為五邊形或七 邊形時可得到相同效果,其中隆突電極5 b位於一電極片4 上<經裁切邊角大體上與隆突電極5&位於相鄰電極片4上 之經裁切邊角平行。 -15-
根據本發明液晶顯示裝置,如圖8Α及8Β所示,為了使 =鄰包極片4之間距更短,各電極片4之形狀可調整成矩 ^其中遠電極片4之短邊係對正於電極片4之對正方向。 此情況下,該隆突電極5&及51)可對正成使各電極片4對正 於^私極片4對正方向平行之方向。然而,隆突電極5 a及 5b之數目及位置不限於此,而視驅動器ic i之電極片$之 大小適當地選擇。 根據本發明,只要電極片4上之隆突電極5a及5b中之至 ^ w個私性連接於對應之結合片6,則液晶顯示面板及驅 、w C黾丨生連接。液晶顯示面板與驅動器I c間之電性連 接係藉著調整隆突電極之大小及導電性粒子7於異方性導 私ί'生黏著劑2中之充填密度而進一步確認,以於驅動器工c 之每個隆哭電極與液晶顯示面板之每個對應結合片之間提 供至少四個導電性粒子。 於前述實施例中,使用異方性導電性黏著劑ACF。然 而’本發明不限於此,亦可使用含有導電性粒子之各向同 性導電性黏著劑。已知ACF之優點係為可藉著使用單一 ACF層於多個電極片與多個結合片之間提供電性連接。此 種情況有利於在面朝下之方式下將方位晶片裝置於基板 上。 根據本發明,連接有電路元件而該電路元件連接於液晶 顯示裝置之玻璃基板之基板可由玻璃以外之材料製造。 根據本發明,於位在電路元件之多個電極片上各提供多 個隆突電極。此等隆突電極用以在位於電路元件上之各電 476858 A7 B7 五、發明説明(14 ) 極片與位於液晶顯示面板上之各結合片之間提供電性連 接。即使位於一電極片上之多個隆突電極中之一例如因為 電鍍無法持續而喪失或未具有預定高度,則其餘隆突電極 仍可於電路元件之電極片與液晶顯示面板之對應結合片之 間提供電性連接。換言之,除非所有該多個隆突電極皆無 法適當地形成,否則該電路元件之電極片及該液晶顯示面 板之結合片皆可電性連接。 因為位於各電極片上之相鄰隆突電極之間隔係約5微米 或更大,故相鄰隆突電極不會在持續電鍍期間彼此短路。 因此,形成隆突電極以使彼此完全絕緣,而進一步降低連 接失敗之危險。 若例如將電極片製成距形以使間距縮短,電極片之短邊 對正於對正方向,隆突電極以各電極片對正於與電極片長 軸平行之方向為佳。如此一來,隆突電極之總面積則夠大 而有效率。 此外,為了使相鄰電極片之間距更小,相鄰電極片可形 成鋸齒狀排列。此情況下,可裁切該隆突電極之邊角(故 該隆突電極之形狀係為五邊形、七邊形等),使隆突電極 位於一電極片上之經裁切邊角大體上平行於相鄰電極片之 隆突電極之經裁切邊角。是故,位置最接近之隆突電極之 間距可增長,而增加電路元件與液晶顯示面板間之電性連 接的可信度。或者,可藉著提供經裁切之邊角而增加各隆 突電極之面積,以增加電路元件與液晶顯示面板間之電性 連接的可信度。 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 裝 訂
線 476858 A7 B7 五、發明説明(15 ) 熟習此技藝者可於不偏離本發明範圍及精神下進行各種 其他改良。因此,申請專利範圍不限於前文描述,而為廣 義之申請專利範圍。 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)

Claims (1)

  1. 申請專利範圍 ι· 種液晶顯示裝置,並舍括且右續玫 /、包栝具有線路圖型之基板,及經 在=私,而電性連接於該線路圖型之電路元件,其特徵 孩線路圖型具有至少一個結合片; 該電路元件具有至少一個電極片; 該至少一個電極片上具有多個隆突電極;而 該至少一個電極片係經由導電層電性連接於該至少一 個結合片,該導電層係位於該多個隆突電極與面對於該 =突電極之結合片之間,其中該導電層係為整體上 有導電性粒子分散之絕緣材料。 裝 2.根據申請專利範圍第1項之液晶顯示裝置,其中相鄰隆 突電極之間隔係約5微米或更大。 訂 3·根據申請專利範圍第i項之液晶顯示裝置,其包括多個 電極片,其中: 該多個電極片各具有長邊及短邊; 忒多個電極片係對正於與電極片短邊平行之方向;而 孩多個隆突電極係對正於與該多個電極片之各個長 平行之方向。 4· 2據申請專利範圍第1項之液晶顯示裝置,其包括多個 笔桎片其中该多個電極片係排列成据齒狀,隆突電極 之邊角經裁切,使位於一電極片上之隆突電極之經裁切 又邊角大體上與位於相鄰電極片上之隆突電極之經裁切 之邊角平行。 5·根據申請專利範圍第1項之液晶顯示裝置,其中面對於 用中國國家標準(CNS)_ -19- A4規格(210X297公釐) 476858 A8 B8 C8 D8
    六、申請專利範圍 係排列成大體上與 該結合片之該多個隆突電極之表面, 結合片之表面平行。 6·根據申請專利範圍第1項之液晶顯示裝置 其包括多個
    製造之單一導電層而電性連接。 其中位於基 而彼此電性 根據申請專利範圍第6項之液晶顯示裝置, 板上之線路圖型及電路元件以面狀黏合方式 連接。 8·根據申請專利範圍第丨項之液晶顯示裝置,其中該基板 係為玻璃基板。 9·根據申請專利範圍第丨項之液晶顯示裝置,其中該多個 隆突電極中之任一者,皆係與其他多個隆突電極中之任 一者相互獨立的,足夠承載用以實行電性連接之電流, 孩電性連接係於至少一個電極片及至少一個結合片之 間’經由該導電層所實行者。 10·根據申請專利範圍第1項之液晶顯示裝置,其中該多個 隆突電極中之任一者,皆係與其他多個隆突電極中之任 一者相互獨立的,具有足夠的高度去實行電性連接,該 包性連接係於至少一個電極片及至少一個結合片之間, 經由該導電層所實行者。 11·根據申請專利範圍第1項之液晶顯示裝置,其中少於該 隆突電極之總數之多數個隆突電極,係足夠承載用以實 行卷f生連接之電流,該電性連接係於至少一個電極片及 本紙張尺度逋用中@ @家標準(CNS) A4規格(⑽X 297公爱) 476858 A8 B8 C8 D8 々、申請專利範圍 至少一個結合片之間,經由該導電層所實行者。 12. 根據申請專利範圍第1項之液晶顯示裝置,其中少於該 隆突電極之總數之多數個隆突電極,係具有足夠的高度 去實行電性連接,該電性連接係於至少一個電極片及至 少一個結合片之間,經由該導電層所實行者。 13. 根據申請專利範圍第1項之液晶顯示裝置,其中該多數 個隆突電極中之一個,具有與該多數個隆突電極中之至 少一個相異的高度。 -21 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐)
TW087102997A 1997-03-06 1998-03-02 Liquid crystal display device TW476858B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05215297A JP3328157B2 (ja) 1997-03-06 1997-03-06 液晶表示装置

Publications (1)

Publication Number Publication Date
TW476858B true TW476858B (en) 2002-02-21

Family

ID=12906898

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087102997A TW476858B (en) 1997-03-06 1998-03-02 Liquid crystal display device

Country Status (6)

Country Link
US (1) US6111628A (zh)
EP (4) EP1408364B1 (zh)
JP (1) JP3328157B2 (zh)
KR (1) KR100294778B1 (zh)
DE (4) DE69837796T2 (zh)
TW (1) TW476858B (zh)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998012597A1 (en) * 1996-09-20 1998-03-26 Hitachi, Ltd. Liquid crystal display device, production method thereof and mobile telephone
AU1174197A (en) * 1996-12-26 1998-07-31 Hitachi Limited Semiconductor device and method of manufacturing the same
TW424171B (en) * 1998-11-03 2001-03-01 Ind Tech Res Inst Device of compensation-type tape and method for making the same
JP3660175B2 (ja) * 1998-11-25 2005-06-15 セイコーエプソン株式会社 実装構造体及び液晶装置の製造方法
US6556268B1 (en) * 1999-03-31 2003-04-29 Industrial Technology Research Institute Method for forming compact LCD packages and devices formed in which first bonding PCB to LCD panel and second bonding driver chip to PCB
JP3892650B2 (ja) * 2000-07-25 2007-03-14 株式会社日立製作所 液晶表示装置
TW464927B (en) * 2000-08-29 2001-11-21 Unipac Optoelectronics Corp Metal bump with an insulating sidewall and method of fabricating thereof
WO2003098338A1 (fr) * 2002-05-22 2003-11-27 Sharp Kabushiki Kaisha Materiau de transfert commun, ecran a cristaux liquides, procede de fabrication d'ecran a cristaux liquides
KR20040075377A (ko) * 2003-02-20 2004-08-30 삼성전자주식회사 구동 아이씨 및 이를 갖는 디스플레이 장치
JP2004317924A (ja) * 2003-04-18 2004-11-11 Advanced Display Inc 表示装置および表示装置の製造方法
JP4004994B2 (ja) 2003-06-05 2007-11-07 株式会社アドバンスト・ディスプレイ 表示装置
JP2005062582A (ja) * 2003-08-18 2005-03-10 Hitachi Displays Ltd 表示装置
KR100637429B1 (ko) * 2003-10-24 2006-10-20 삼성에스디아이 주식회사 플라즈마 디스플레이 장치
US20050104180A1 (en) * 2003-11-14 2005-05-19 Vassoudevane Lebonheur Electronic device with reduced entrapment of material between die and substrate electrical connections
KR101016284B1 (ko) * 2004-04-28 2011-02-22 엘지디스플레이 주식회사 Cog 방식 액정표시소자 및 그 제조방법
KR101075599B1 (ko) * 2004-06-23 2011-10-20 삼성전자주식회사 표시장치
TWI262347B (en) * 2004-08-02 2006-09-21 Hannstar Display Corp Electrical conducting structure and liquid crystal display device comprising the same
KR100742376B1 (ko) * 2005-09-30 2007-07-24 삼성에스디아이 주식회사 패드부 및 그 제조 방법
TWI307132B (en) * 2006-03-24 2009-03-01 Via Tech Inc Chip package and fabricating method thereof
KR20080042282A (ko) * 2006-11-09 2008-05-15 삼성에스디아이 주식회사 플라즈마 디스플레이 장치
TW201121006A (en) * 2009-12-03 2011-06-16 Hannstar Display Corp Connection structure for chip-on-glass driver IC and connection method therefor
CN103094737A (zh) * 2011-11-05 2013-05-08 宝宸(厦门)光学科技有限公司 引脚结构与引脚连接结构
CN102843858B (zh) * 2012-07-30 2014-12-10 友达光电(厦门)有限公司 用于固设一半导体芯片的线路基板及其制造方法
CN104737290B (zh) 2012-10-26 2017-09-19 奥林巴斯株式会社 固体摄像装置、摄像装置以及信号读出方法
KR20150139190A (ko) * 2014-06-03 2015-12-11 삼성전기주식회사 소자 및 소자 패키지
KR20160046977A (ko) * 2014-10-20 2016-05-02 삼성디스플레이 주식회사 이방성 도전입자
CN105261602A (zh) * 2015-09-16 2016-01-20 京东方科技集团股份有限公司 一种显示面板的封装结构、转接板、封装方法及显示装置
CN107632472B (zh) * 2017-10-12 2019-03-12 深圳市华星光电半导体显示技术有限公司 液晶显示面板及其配向方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0682672B2 (ja) * 1984-04-23 1994-10-19 沖電気工業株式会社 半導体装置
JPH0812352B2 (ja) * 1985-03-20 1996-02-07 松下電器産業株式会社 液晶表示装置
US4949224A (en) * 1985-09-20 1990-08-14 Sharp Kabushiki Kaisha Structure for mounting a semiconductor device
JPS648647A (en) * 1987-07-01 1989-01-12 Toshiba Corp Manufacture of semiconductor device
JPH01215034A (ja) * 1988-02-24 1989-08-29 Matsushita Electric Ind Co Ltd 半導体装置
JP2596960B2 (ja) * 1988-03-07 1997-04-02 シャープ株式会社 接続構造
US5016986A (en) * 1988-04-12 1991-05-21 Sharp Kabushiki Kaisha Display device having an improvement in insulating between conductors connected to electronic components
JP2642433B2 (ja) * 1988-08-22 1997-08-20 株式会社東芝 暗号化鍵生成装置
JPH0384929A (ja) * 1989-08-28 1991-04-10 Fujitsu Ltd 半導体装置の製造方法
JPH03125443A (ja) * 1989-10-09 1991-05-28 Sharp Corp 実装基板の電極及び該実装基板の電極を有する液晶表示装置
WO1992006402A1 (en) * 1990-09-29 1992-04-16 Sekisui Fine Chemical Co., Ltd. A fine sphere, a spherical spacer for a liquid crystal display element and a liquid crystal display element using the same
JPH04242939A (ja) * 1990-12-13 1992-08-31 Citizen Watch Co Ltd 半導体装置の実装構造およびその製造方法
KR920022482A (ko) * 1991-05-09 1992-12-19 가나이 쯔도무 전자부품 탑재모듈
JPH04364051A (ja) * 1991-06-11 1992-12-16 Rohm Co Ltd 半導体装置
JPH0513418A (ja) * 1991-07-04 1993-01-22 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3363924B2 (ja) * 1992-10-02 2003-01-08 シチズン時計株式会社 液晶表示パネルのicの実装方法
JPH0758112A (ja) * 1993-08-20 1995-03-03 Rohm Co Ltd 半導体装置
JPH07115096A (ja) * 1993-10-18 1995-05-02 Fujitsu Ltd バンプ電極
TW340192B (en) * 1993-12-07 1998-09-11 Sharp Kk A display board having wiring with three-layered structure and a display device including the display board
JPH07281203A (ja) * 1994-04-11 1995-10-27 Citizen Watch Co Ltd 液晶パネル
JP2581017B2 (ja) * 1994-09-30 1997-02-12 日本電気株式会社 半導体装置及びその製造方法
JP3487524B2 (ja) * 1994-12-20 2004-01-19 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP3688801B2 (ja) * 1996-04-25 2005-08-31 株式会社日立製作所 半導体装置及びその製造方法並びにその実装方法
JP2825083B2 (ja) * 1996-08-20 1998-11-18 日本電気株式会社 半導体素子の実装構造

Also Published As

Publication number Publication date
EP0863426B1 (en) 2004-09-22
KR100294778B1 (ko) 2001-07-12
DE69826349D1 (de) 2004-10-28
JP3328157B2 (ja) 2002-09-24
EP1403685B1 (en) 2005-11-09
EP0863426A1 (en) 1998-09-09
EP1403685A2 (en) 2004-03-31
DE69826349T2 (de) 2005-09-29
DE69832308D1 (de) 2005-12-15
DE69837796D1 (de) 2007-06-28
JPH10246894A (ja) 1998-09-14
EP1403686A2 (en) 2004-03-31
EP1403686B1 (en) 2007-05-16
EP1403686A3 (en) 2004-04-14
DE69840837D1 (de) 2009-06-25
DE69832308T2 (de) 2006-08-03
KR19980079910A (ko) 1998-11-25
EP1403685A3 (en) 2004-04-14
DE69837796T2 (de) 2008-03-06
EP1408364B1 (en) 2009-05-13
EP1408364A1 (en) 2004-04-14
US6111628A (en) 2000-08-29

Similar Documents

Publication Publication Date Title
TW476858B (en) Liquid crystal display device
JP3671192B2 (ja) 絶縁層付角柱状バンプ及びそのバンプを用いたチップオングラス製品並びにicチップ表面への絶縁層付角柱状バンプの製造方法
US20020067457A1 (en) Liquid crystal device and manufacturing method therefor
WO1996007196A1 (en) Tiled panel display assembly
CN101395975A (zh) 电子部件安装结构体及其制造方法
JP2796070B2 (ja) プローブカードの製造方法
KR100499107B1 (ko) 액정디스플레이 및 전기모듈
JPH05290946A (ja) 電子部品実装方法
JP2807838B2 (ja) 半導体集積素子の樹脂封止用孔版および樹脂封止方法
TWI287091B (en) Flat-type probe apparatus for inspecting flat panel display device
JP3256659B2 (ja) 異方性導電薄膜および該異方性導電薄膜を使用したポリマー基板接続方法
JP2000165022A (ja) 電極端子接続構造
TW573337B (en) Apparatus and method for fixing integrated circuit chip
TW538659B (en) Printed circuit board with notch
JPS61244035A (ja) バンプ電極の接続方法
JPH05190580A (ja) 微細粒子の分散配置方法
JP3272889B2 (ja) 半導体装置の製造方法
JPH1090307A (ja) プローブカードの製造方法
JPH09160064A (ja) 異方性シートおよび配線基板
KR100875840B1 (ko) 액정디스플레이 패널 검사용 프로브핀의 정렬 가이드 및 그제조방법
JPH02259624A (ja) 表示装置
TW556231B (en) Method for making anisotropic conductive board
JP2002228684A (ja) コンタクトプローブ
JPH0622084B2 (ja) 電極端子転移用異方性導電膜の形成方法
JPS63233545A (ja) 接続方法

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent