TW457584B - Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings - Google Patents

Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings Download PDF

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Publication number
TW457584B
TW457584B TW089106468A TW89106468A TW457584B TW 457584 B TW457584 B TW 457584B TW 089106468 A TW089106468 A TW 089106468A TW 89106468 A TW89106468 A TW 89106468A TW 457584 B TW457584 B TW 457584B
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TW
Taiwan
Prior art keywords
etching
gas
silicon layer
reactor
plasma
Prior art date
Application number
TW089106468A
Other languages
English (en)
Chinese (zh)
Inventor
Darrell Mcreynolds
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application granted granted Critical
Publication of TW457584B publication Critical patent/TW457584B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
TW089106468A 1999-04-20 2000-04-07 Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings TW457584B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/295,634 US6191043B1 (en) 1999-04-20 1999-04-20 Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings

Publications (1)

Publication Number Publication Date
TW457584B true TW457584B (en) 2001-10-01

Family

ID=23138562

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089106468A TW457584B (en) 1999-04-20 2000-04-07 Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings

Country Status (5)

Country Link
US (2) US6191043B1 (enExample)
JP (1) JP4852196B2 (enExample)
KR (1) KR20020010605A (enExample)
TW (1) TW457584B (enExample)
WO (1) WO2000063960A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI630655B (zh) * 2015-12-04 2018-07-21 日立全球先端科技股份有限公司 Dry etching method

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US6544860B1 (en) * 2000-03-06 2003-04-08 Koninklijke Philips Electronics N.V. Shallow trench isolation method for forming rounded bottom trench corners
US6743732B1 (en) * 2001-01-26 2004-06-01 Taiwan Semiconductor Manufacturing Company Organic low K dielectric etch with NH3 chemistry
US6451673B1 (en) * 2001-02-15 2002-09-17 Advanced Micro Devices, Inc. Carrier gas modification for preservation of mask layer during plasma etching
US6746961B2 (en) 2001-06-19 2004-06-08 Lam Research Corporation Plasma etching of dielectric layer with etch profile control
WO2003037497A2 (en) * 2001-10-31 2003-05-08 Tokyo Electron Limited Method of etching high aspect ratio features
US20040171260A1 (en) * 2002-06-14 2004-09-02 Lam Research Corporation Line edge roughness control
US7547635B2 (en) * 2002-06-14 2009-06-16 Lam Research Corporation Process for etching dielectric films with improved resist and/or etch profile characteristics
WO2005055303A1 (ja) * 2003-12-01 2005-06-16 Matsushita Electric Industrial Co., Ltd. プラズマエッチング方法
JP4098225B2 (ja) * 2003-12-01 2008-06-11 松下電器産業株式会社 プラズマエッチング方法
DE10331526A1 (de) * 2003-07-11 2005-02-03 Infineon Technologies Ag Verfahren zum anisotropen Ätzen einer Ausnehmung in ein Siliziumsubstrat und Verwendung einer Plasmaätzanlage
US20050280674A1 (en) 2004-06-17 2005-12-22 Mcreynolds Darrell L Process for modifying the surface profile of an ink supply channel in a printhead
US7309641B2 (en) * 2004-11-24 2007-12-18 United Microelectronics Corp. Method for rounding bottom corners of trench and shallow trench isolation process
US7202178B2 (en) * 2004-12-01 2007-04-10 Lexmark International, Inc. Micro-fluid ejection head containing reentrant fluid feed slots
JP5041696B2 (ja) * 2005-11-15 2012-10-03 パナソニック株式会社 ドライエッチング方法
US7985688B2 (en) * 2005-12-16 2011-07-26 Lam Research Corporation Notch stop pulsing process for plasma processing system
JP2009525604A (ja) * 2006-02-01 2009-07-09 アルカテル−ルーセント 異方性エッチングの方法
US7608195B2 (en) * 2006-02-21 2009-10-27 Micron Technology, Inc. High aspect ratio contacts
US7517804B2 (en) * 2006-08-31 2009-04-14 Micron Technologies, Inc. Selective etch chemistries for forming high aspect ratio features and associated structures
US7927966B2 (en) 2006-12-12 2011-04-19 Nxp B.V. Method of manufacturing openings in a substrate, a via in substrate, and a semiconductor device comprising such a via
KR100838399B1 (ko) 2007-05-17 2008-06-13 주식회사 하이닉스반도체 반도체 소자의 트렌치 형성 방법
JP5135879B2 (ja) * 2007-05-21 2013-02-06 富士電機株式会社 炭化珪素半導体装置の製造方法
US8500913B2 (en) * 2007-09-06 2013-08-06 Micron Technology, Inc. Methods for treating surfaces, and methods for removing one or more materials from surfaces
US8263497B2 (en) * 2009-01-13 2012-09-11 International Business Machines Corporation High-yield method of exposing and contacting through-silicon vias
JP5305973B2 (ja) * 2009-02-20 2013-10-02 ラピスセミコンダクタ株式会社 トレンチ形成方法
WO2011066668A1 (en) * 2009-12-02 2011-06-09 C Sun Mfg. Ltd. Method of etching features into substrate
US8802571B2 (en) 2011-07-28 2014-08-12 Lam Research Corporation Method of hard mask CD control by Ar sputtering
JP2013110139A (ja) * 2011-11-17 2013-06-06 Tokyo Electron Ltd 半導体装置の製造方法
US20140199833A1 (en) * 2013-01-11 2014-07-17 Applied Materials, Inc. Methods for performing a via reveal etching process for forming through-silicon vias in a substrate
CN104347390B (zh) * 2013-07-31 2017-06-27 中微半导体设备(上海)有限公司 一种等离子体刻蚀基片的方法
JP6328703B2 (ja) * 2016-08-15 2018-05-23 東京エレクトロン株式会社 半導体装置の製造方法
WO2020131793A1 (en) * 2018-12-20 2020-06-25 Mattson Technology, Inc. Silicon mandrel etch after native oxide punch-through
CN112285828A (zh) * 2020-09-30 2021-01-29 中国科学院微电子研究所 一种端面耦合器及其封装方法、应用
CN114678270B (zh) * 2020-12-24 2025-08-08 中微半导体设备(上海)股份有限公司 一种电感耦合等离子处理装置及其刻蚀方法

Family Cites Families (10)

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US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4726879A (en) 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
FR2616030A1 (fr) * 1987-06-01 1988-12-02 Commissariat Energie Atomique Procede de gravure ou de depot par plasma et dispositif pour la mise en oeuvre du procede
US4992134A (en) * 1989-11-14 1991-02-12 Advanced Micro Devices, Inc. Dopant-independent polysilicon plasma etch
US5356515A (en) * 1990-10-19 1994-10-18 Tokyo Electron Limited Dry etching method
US5296095A (en) * 1990-10-30 1994-03-22 Matsushita Electric Industrial Co., Ltd. Method of dry etching
US5933748A (en) * 1996-01-22 1999-08-03 United Microelectronics Corp. Shallow trench isolation process
US5843226A (en) * 1996-07-16 1998-12-01 Applied Materials, Inc. Etch process for single crystal silicon
JP3907087B2 (ja) * 1996-10-28 2007-04-18 キヤノンアネルバ株式会社 プラズマ処理装置
US6033991A (en) * 1997-09-29 2000-03-07 Cypress Semiconductor Corporation Isolation scheme based on recessed locos using a sloped Si etch and dry field oxidation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI630655B (zh) * 2015-12-04 2018-07-21 日立全球先端科技股份有限公司 Dry etching method

Also Published As

Publication number Publication date
US6191043B1 (en) 2001-02-20
WO2000063960A1 (en) 2000-10-26
KR20020010605A (ko) 2002-02-04
JP2002542623A (ja) 2002-12-10
US20010001743A1 (en) 2001-05-24
JP4852196B2 (ja) 2012-01-11

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