TW445589B - Semiconductor device and manufacture of semiconductor device - Google Patents

Semiconductor device and manufacture of semiconductor device Download PDF

Info

Publication number
TW445589B
TW445589B TW089104363A TW89104363A TW445589B TW 445589 B TW445589 B TW 445589B TW 089104363 A TW089104363 A TW 089104363A TW 89104363 A TW89104363 A TW 89104363A TW 445589 B TW445589 B TW 445589B
Authority
TW
Taiwan
Prior art keywords
semiconductor
resin
width
semiconductor substrate
electrode pad
Prior art date
Application number
TW089104363A
Other languages
English (en)
Inventor
Akio Nakamura
Original Assignee
Oki Electric Ind Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=13278777&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=TW445589(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Oki Electric Ind Co Ltd filed Critical Oki Electric Ind Co Ltd
Application granted granted Critical
Publication of TW445589B publication Critical patent/TW445589B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10157—Shape being other than a cuboid at the active surface

Description

4 4 5 5 Β Γ A7 6 Ο Ο 6 p i f. d 〇 c / Ο Ο 8 B7 五、發明說明（/ ) 枝術領域 本發明是有關於一種半導體元件及其製造方法，特別 是有關於一種封裝。 背景說明 近年來，半導體元件之高密度封裝持續在進步，晶片 尺寸構裝等半導體元件也受到重視。 習知此種晶片尺寸構裝如第6圖所繪示。第6圖其所 繪示半導體元件係於半導體基底1形成電極墊2，藉由電 極墊2中電氣連接之Cu等形成導線3。半導體基底表面及 導線3係藉樹脂4灌封。藉露出於樹脂表面之導線3上之 焊劑等形成凸塊5。 以下，藉第7圖說明習知半導體元件之製造方法。首 先於半導體基底之晶片70上形成Cu等導線71(第7-A圖）。 於此狀態將樹脂72充塡於晶片全體(第7-B圖）。接著，硏 磨全表面使導線71露出表面（第7-C圖）。於樹脂72表面 藉焊劑等形成凸電極73(第7-D圖）。分別於半導體元件切 斷晶片，藉由分割，結束半導體元件之形成(第7-E圖）。 發明之槪沭 然而，習知之結構與製造方法具有，分割各個半導體 元件時，於半導體元件表面與樹脂之介面因應力使半導體 元件產生缺角，封裝半導體元件時因熱應力，使樹脂與半 導體元件產生剝離等問題。 本發明之主要目的就是在解決上述課題，而提出一種 半導體元件，其具有一半導體基底，其具備第一厚度之中 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝---- 訂---------綉 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 4 5 5 8 A7 600 6pif.doc/0 0 8 β7 五、發明說明（飞） 央部份與較第一厚度薄之第二厚度的周圍部份，及形成於 半導體基底上之電極墊，及灌封半導體基底之灌封樹脂， 及形成於灌封樹脂上之突起電極，及電氣連接電極墊與突 起電極之導線。 而且，本發明之半導體元件製造方法包含，於半導體 晶片上形成電極墊之作業，及形成與電極墊連接之導線的 工程，及於半導體晶片之特定領域形成具有第一寬度之作 業，及樹脂灌封半導體晶片與上述導線之作業，及於樹脂 上形成與上述導線電氣連接之突起電極的作業，及使用具 有較第1厚度狹窄之刀刃的刀切斷特定領域，分割各個半 導體元件之作業。 圖式之簡單說明： 第1^_繪示爲本發明第1實施形態半導體元件之構 造圖。/4¾) 第i圖所繪示爲本發明第1實施形態半導體元件之製 造方法作業:示意圖。 \ ：... 第> #爲本發明第2實施形態半導體元件之構 造圖。 第4$所繪示爲本發明第2實施形態半導體元件之製 造方法作;圖。 第5圖所繪示爲本發明第2實施形態半導體元件之製 造方法作業示意圖。 第6 _所繪示爲習知半導體元件之構造圖。 ^ (Λ.)+ v ^ ) 第7 斯轉.示爲習知半導體元件之製造方法作業示意 ； ·， \ \ · t \ > \·· \ 5 __'____ 本紙張尺度適用中國國家標準（CNS)A4規格（210X 297公釐） ------------采--—---I I --------1 (請先閱讀背面之注意事項再填寫本頁> ^455 8 ' 600 6pif.doc/00 8 五、發明說明（>) 圖。 A7 經濟部智慧財產局員工消費合作社印製 圖式標號說明： 1 :半導體基底 2 :電極墊 3 :導線 4 :樹脂 5 :凸塊 6 :段差部份 11 :中央部份 12 :周圍部份 20 :半導體晶片 21 :導線 22 :刀 23 :溝槽 24 :樹脂 25 :硏磨刀 26 :凸電極 27 :刀 31 =段差部份 32 :段差部份 70 :晶片 71 :導線 72 :樹脂 ----------- r 裝--------訂--------I (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS)A4規格（2丨Ox 297公釐） A7 B7 445 5 6 006pif.doc/0 0 8 i、發明說明（α) 73 :凸電極 管施本發明之齡佳方忒 (第1實施形態） 第1-A圖其所繪示爲本發明由背面所視之半導體元件 圖。第1-B圖所繪示爲第1-A圖線AB部份之剖面圖。以 下使用第1圖說明本發明之第]實施形態。而關於與第6 圖共通之部份將使用共通符號說明。 半導體基底1中央部份11具有特定厚度。半導體元 件周圍部份12之半導體基底1厚度較其中央部份u薄， 而形成段差部份6(第1圖中以圓圈住表示）。此段差部份6 係半導體基底被形成於樹脂灌封側之面。此段差部份6之 深度’及自中央部份表面至周圍部份12上方之距離最好 在10ym以上(第1-B圖中以Y表示）。半導體元件端部至 中央部份之距離，即此段差部份6之寬度最好在3//m以 上（桌1-B圖中以X表不）。半導體基底]表面部份之特定 處形成有錦電極墊2。半導體基底上藉Cu形成導線3。導 線3與鋁電極墊2電氣連接。半導體基底1表面與導線3 被藉樹脂4灌封。樹脂4上形成有凸塊5。本實施形態中 露出於樹脂4表面之導線3上藉焊劑等形成&塊5。 本發明之半導體元件中，半導體基底丨周圍部份12 較中央部份11薄而形成段差部份6。此段差部份6係包圍 半導體元件中央部份11而分別形成於其四邊(第圖）。 因爲有此段差部份，故半導體元件周圍部份12與樹 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閲讀背面之注意事項再填寫本頁) 裝.！ l!i訂---------線 I - 經濟部智慧財產局貝Η消费合作社印製 A7 B7 445589 6006pif.d〇c/008 五、發明說明) 脂4 之半導體基底1部份里對增如，而增強錨定效果。 因爲錨定效果增強’半導體基底1不易由樹脂4剝離。 因此，本發明之半導體元件，藉封裝元件時之熱應力， 可減少產生樹脂與半導體基底親邏之問題，而成爲安定之 半導體元件。 接著使用第2圖說明本發明第1實施形態之半導體元 件製造方法。 首先藉由半導體晶片20上之電鍍束等，形成Cu導線 21(第2-A圖）。此導線被電氣連接於無圖示而形成於晶片 上之電極墊。 其後’藉由使其高速迴轉之外周刀22而於半導體晶 片20表面形成溝槽23。此溝槽23係由各個半導體元件周 圍部份之部份形成。被利用於形成此溝槽之刀22刀厚35-150" m。溝槽23之形成寬度較刀厚寬約1-5/i m，此深度 在10μ m以上（第2-B圖）。藉由10// m以上之深度，可不 必依刀刃之形狀，而以安定之寬度形成溝槽。 其後，對於半導體晶片20表面充塡樹脂24。此時所 充塡之樹脂24也會進入溝槽23(第2-C圖）。 直至被樹脂埋沒之導線露出，藉硏磨刀25硏磨樹脂24 表面（第2-D圖）。其後，於露出之導線21上藉焊球等形成 凸電極26(第2-E圖）。 其後，藉高速迴轉之外周刀27，切斷於上述作業形成 之溝槽23部份。藉此切斷，半導體晶片20被分割爲各個 半導體元件。被利用於此切斷之刀27之厚度較上述形成 8 ------------ .裝---I ----訂·----！線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 445 Γ 6006pif. doc/008 4455 8 9 A7 B7 經濟部智慧財產局員工消费合作杜印製 五、發明說明（‘） 溝槽23時使用之刀22薄，最好薄至6//m以上（第2-F圖）。 本發明之製造方法中’於半導體晶片20表面形成溝 槽23 ’藉樹脂灌封後切斷溝槽23部份以分割各個元件。 於半導體晶片20表面部份加上應力係於，當表面部 份直接接觸刀時。用以分割之刀27並不直接接觸半導體 晶片20表面部份，而是接觸事先形成之溝槽23底部。在 半導體晶片20表面部份施加應力並非於切斷時，而是於 形成溝槽23時^ 因爲形成溝槽23時之切斷深度較淺，故相較於分割 切斷時，刀22接觸半導體晶片20表面之時間較短。因此 施加於半導體晶片20表面之應力也較小，也可減少於各 個半導體元件表面產生缺角。而且即使形成溝槽23時於 表面部份產生缺角，也可藉樹脂灌封於缺角部份充塡樹脂 24 ° 如上所述藉本發明第1實施形態之半導體元件及其製 造方法，可提供一種半導體元件，其可消除樹脂部份與半 導體基底部份之剝離危機，並減少半導體元件表面產生之 缺角。 (第2實施形態） 第3-A圖其所繪示爲本發明由背面所視之半導體元件 圖。第3-B圖所繪示爲第3-A圖線Α-0-Β部份之剖面圖。 以下使用第3圖說明本發明之第2實施形態。而關於與第 1圖共通之部份將使用共通符號說明。 關於在半導體基底1上形成段差部份6之處與第1實 9 本紙張尺度適用中國國家標準（CNS)A4規格（21〇 X 297公爱） I -----------^^i — ίιι— 訂 *--— ！11線 I (請先間讀背面之注意事項再填寫本頁) A7 B7 445589 6 006pif+d〇c/008 五、發明說明（1 ) 施形態相同。 第2實施形態之段差部份6如第3-A圖所繪示之點線， 其寬度（圖中以X表示）係如脈衝波形般進行週期性變化。 因爲如此之形狀而更加強了其錨定效果。而沿半導體元件 一邊而形成之段差部份並非僅單一方向。尙有垂直於與半 導體元件邊緣平行之段差部份31方向上的段差部份32存 在。 因此不論由切斷應力或熱應力施加之力，皆可充分防 止基底與樹脂之剝離。 因此第2實施形態係較第1實施形態具有更優良之錨 定效果的半導體元件。 接著使用第4圖說明本發明第2實施形態之半導體元 件製造方法。而關於與第2圖共同之部份將使用共通符號 說明。 首先於半導體晶片20上，藉電鍍束等形成Cu導線 21(第 4-A 圖 p 藉雷射照射於半導體晶片20表面形成溝槽23。此溝 槽23係由各個半導體元件形成周圍的部份所形成。溝槽23 寬度係於下限値寬度XI μ m與上限値寬度X2em之間進 行週期性變化。而溝槽23深度係i〇A m(第4-B圖）。第5 圖其所繪示爲由上方看此溝槽23之放大圖。其後，於半 導體晶片20表面充塡樹脂24。此時所充塡之樹脂24也會 進入溝槽23中（第4-C圖）。 直至被樹脂24埋沒之導線21露出，藉硏磨刀25硏 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------------^--I I----訂·------— ·線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 A7 B7 445589 6 006pif. doc/00 8 五、發明說明（g ) 磨樹脂表面(第4-D圖）。其後，於露出之半導體晶片20上 藉焊球等形成凸電極26(第4-E圖）。 其後，藉高速迴轉之外周刀27，分割切斷各個半導體 元件。被利用於此切斷之刀27之厚度較上述溝槽之最小 寬度XI薄，最好薄至6μ m以上(第4-F圖）。 其可減低施加於半導體晶片表面部份之應力部份係與 第1實施形態相同。本實施例中藉由使段差部份之形狀更 接近脈衝波形，而使樹脂24硬化收縮時之應力，也可被 段差部吸收。如上述詳細說明中，藉本發明第2實施形態 之半導體元件及其製造方法，可提供一種可消除樹脂部份 與半導體基底部份之剝離危機的安定半導體元件。 本發明之實施形態係，硏磨灌封樹脂露出導線，然而 硏磨並非必要，控制樹脂之量在灌封樹脂時約可露出導線 即可。 而且，本發明第2實施例中，段差部份並不一定非爲 如脈衝波形之形狀不可，其寬度於特定之上限値與下限値 之範圍內變化，使用具有較下限値寬度小之刀刃的刀分割 各個元件，即具效果。 ------------ 装|-----訂------------1 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）

Claims (1)

  1. 灿劭"808 445589 6006pif.doc/008 六、申請專利範圍 1. 一種半導體元件，包含： 一半導體基底，其具備第一厚度之中央部份與較第一 厚度薄之第二厚度的周圍部份； 一電極墊，其形成於上述半導體基底上： 一灌封樹脂，用以灌封上述半導體基底； 一突起電極，其形成於上述灌封樹脂上：以及 一導線，用以電氣連接上述電極墊與上述突起電極。 2. —種半導體元件，包含： 一半導體基底，其具備一中央部份，以及一周圍部份， 其形成於目該中央部份表面至具有特定段差之處； 一電極墊，其形成於上述半導體基底中央部份； 一突起電極，介由導線與上述電極墊呈電氣連接；； 以及 一灌封樹脂，用以灌封上述半導體基底中央部份、周 圍部份及導線。 3. 如申請專利範圍第1項或第2項所述之半導體元 件，上述半導體基底周圍部份具有自上述半導體元件端 部至上述中央部份距離之寬度，該周圍部份寬度於第1 値與第2値之範圍內變化。 4. 一種半導體元件之製造方法，包含： 於一半導體晶片上形成一電極墊的作業； 形成用以與上述電極墊連接之導線的作業； 形成於上述半導體晶片之特定領域中，具有第1寬度 之溝槽的作業； (請先閱讀背面之注意事項再填寫本頁) 表--------訂---------線' 姆濟部智慧財產局員工消費合作杜印製 本紙張尺度洎用中國國家標準（CNS)Al規格（210 X 297公釐） 4 45 5 8 c ： ' AS R8 C8 6 0 0 6 p i f ‘ d 〇 c") 0 8 D8 六、申請專利範圍 樹脂灌封上述半導體晶片與上述導線之作業； 形成用以於該樹脂上與上述導線電氣連接之突起電極 的作業；以及 藉具有較上述第1寬度小之之刀刃的刀切斷上述特定 領域，而分割各個半導體元件的作業。 5.—種半導體元件之製造方法，包含： 於一半導體晶片上形成一電極墊的作業； 形成與上述電極墊連接之導線的作業； 形成於上述半導體晶片之特定領域中，於用以作爲上 限値之第1寬度與用以作爲下限値之第2寬度間，變化其 寬度之溝槽的作業； 樹脂灌封上述半導體晶片與上述導線之作業； 形成可於該樹脂上與上述導線電氣連接之突起電極的 作業；以及 藉具有較上述第2寬度小之之刀刃的刀切斷上述特定 領域，而分割各個半導體元件的作業。 (請先閱讀背面之注意事項再填寫本頁) -· 士，衣.—J -----訂·--------I 經濟部智慧財產局員工消費合作社印製 13 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）
TW089104363A 1999-03-11 2000-03-10 Semiconductor device and manufacture of semiconductor device TW445589B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11065157A JP3128548B2 (ja) 1999-03-11 1999-03-11 半導体装置および半導体装置の製造方法

Publications (1)

Publication Number Publication Date
TW445589B true TW445589B (en) 2001-07-11

Family

ID=13278777

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089104363A TW445589B (en) 1999-03-11 2000-03-10 Semiconductor device and manufacture of semiconductor device

Country Status (4)

Country Link
US (3) US6281591B1 (zh)
JP (1) JP3128548B2 (zh)
KR (1) KR100659954B1 (zh)
TW (1) TW445589B (zh)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
JP4691787B2 (ja) * 2001-01-15 2011-06-01 パナソニック株式会社 Ｓａｗデバイス
JP4856328B2 (ja) * 2001-07-13 2012-01-18 ローム株式会社 半導体装置の製造方法
US6734568B2 (en) * 2001-08-29 2004-05-11 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP4439151B2 (ja) 2001-10-31 2010-03-24 株式会社リコー Ｉｃソケット
JP3775499B2 (ja) 2002-01-08 2006-05-17 株式会社リコー 半導体装置及びその製造方法、並びにｄｃ−ｄｃコンバータ
US20030218246A1 (en) * 2002-05-22 2003-11-27 Hirofumi Abe Semiconductor device passing large electric current
US20040023439A1 (en) 2002-07-03 2004-02-05 Kazunari Kimino Apparatus and method for manufacturing semiconductor device
JP3639272B2 (ja) * 2002-08-30 2005-04-20 株式会社東芝 半導体装置、半導体装置の製造方法
US7042065B2 (en) 2003-03-05 2006-05-09 Ricoh Company, Ltd. Semiconductor device and method of manufacturing the same
JP2004288816A (ja) * 2003-03-20 2004-10-14 Seiko Epson Corp 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP4537702B2 (ja) * 2003-12-26 2010-09-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP4290088B2 (ja) 2004-07-14 2009-07-01 株式会社リコー Ｉｃソケット
JP4653447B2 (ja) * 2004-09-09 2011-03-16 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
JP2006196701A (ja) 2005-01-13 2006-07-27 Oki Electric Ind Co Ltd 半導体装置の製造方法
US20060258051A1 (en) * 2005-05-10 2006-11-16 Texas Instruments Incorporated Method and system for solder die attach
TW200717743A (en) * 2005-10-03 2007-05-01 Rohm Co Ltd Semiconductor device
JP5116250B2 (ja) * 2006-04-11 2013-01-09 キヤノン株式会社 積層圧電素子及びその製造方法、並びに振動波駆動装置
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
DE102006060629A1 (de) * 2006-12-21 2008-06-26 Robert Bosch Gmbh Elektrisches Bauelement
JP5081037B2 (ja) 2008-03-31 2012-11-21 ラピスセミコンダクタ株式会社 半導体装置
US7517726B1 (en) * 2008-04-25 2009-04-14 Shanghai Kaihong Technology Co., Ltd Wire bonded chip scale package fabrication methods
US8421201B2 (en) 2009-06-22 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with underfill and methods of manufacture thereof
JP5475363B2 (ja) 2009-08-07 2014-04-16 ラピスセミコンダクタ株式会社 半導体装置およびその製造方法
JP5003802B2 (ja) * 2010-07-22 2012-08-15 パナソニック株式会社 Ｓａｗデバイスとその製造方法
KR20130128227A (ko) * 2012-05-16 2013-11-26 삼성전자주식회사 전자소자 탑재용 기판의 제조방법
US9358580B1 (en) 2013-03-12 2016-06-07 BTD Wood Powder Coating, Inc. Method for preparing and top coating a powder coated wood substrate
TWI581676B (zh) * 2016-04-27 2017-05-01 矽品精密工業股份有限公司 電子封裝件及基板結構
JP7433020B2 (ja) 2019-11-07 2024-02-19 ローム株式会社 チップ部品およびその製造方法

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51137378A (en) 1975-05-22 1976-11-27 Mitsubishi Electric Corp Semi conductor wafer
DE4133820A1 (de) * 1991-10-12 1993-04-15 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterelementen
US5379187A (en) * 1993-03-25 1995-01-03 Vlsi Technology, Inc. Design for encapsulation of thermally enhanced integrated circuits
EP0678904A1 (en) * 1994-04-12 1995-10-25 Lsi Logic Corporation Multicut wafer saw process
US5701034A (en) * 1994-05-03 1997-12-23 Amkor Electronics, Inc. Packaged semiconductor die including heat sink with locking feature
JPH0868705A (ja) * 1994-08-30 1996-03-12 Mitsubishi Electric Corp 半導体圧力検出装置及びその樹脂封止に用いる樹脂封止金型
JP3542677B2 (ja) * 1995-02-27 2004-07-14 セイコーエプソン株式会社 樹脂封止型半導体装置およびその製造方法
JP2763020B2 (ja) * 1995-04-27 1998-06-11 日本電気株式会社 半導体パッケージ及び半導体装置
US5786631A (en) * 1995-10-04 1998-07-28 Lsi Logic Corporation Configurable ball grid array package
KR0178255B1 (ko) * 1995-11-17 1999-03-20 황인길 Bga 반도체 패키지의 pcb캐리어 프레임 및 그 제조방법
KR100274333B1 (ko) * 1996-01-19 2001-01-15 모기 쥰이찌 도체층부착 이방성 도전시트 및 이를 사용한 배선기판
CA2180807C (en) * 1996-07-09 2002-11-05 Lynda Boutin Integrated circuit chip package and encapsulation process
CN1110846C (zh) 1996-07-12 2003-06-04 富士通株式会社 半导体装置的制造方法
JP3137322B2 (ja) * 1996-07-12 2001-02-19 富士通株式会社 半導体装置の製造方法及び半導体装置製造用金型及び半導体装置
JP3143081B2 (ja) * 1996-07-31 2001-03-07 シャープ株式会社 半導体パッケ−ジ用チップ支持基板、半導体装置及び半導体装置の製造法
JP3577848B2 (ja) * 1996-09-30 2004-10-20 ソニー株式会社 半導体装置の外形カット方法及びそれに用いる半導体製造装置
JP3351706B2 (ja) 1997-05-14 2002-12-03 株式会社東芝 半導体装置およびその製造方法
JP3152180B2 (ja) 1997-10-03 2001-04-03 日本電気株式会社 半導体装置及びその製造方法
JP3526731B2 (ja) 1997-10-08 2004-05-17 沖電気工業株式会社 半導体装置およびその製造方法
JPH11224890A (ja) 1997-12-01 1999-08-17 Mitsui High Tec Inc 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US6281591B1 (en) 2001-08-28
KR100659954B1 (ko) 2006-12-22
KR20000071421A (ko) 2000-11-25
JP2000260910A (ja) 2000-09-22
US20010039110A1 (en) 2001-11-08
JP3128548B2 (ja) 2001-01-29
US20040161910A1 (en) 2004-08-19
US6770543B2 (en) 2004-08-03

Similar Documents

Publication Publication Date Title
TW445589B (en) Semiconductor device and manufacture of semiconductor device
US8497587B2 (en) Thermally enhanced expanded wafer level package ball grid array structure and method of making the same
US7112874B2 (en) Forming a multi segment integrated circuit with isolated substrates
US6022758A (en) Process for manufacturing solder leads on a semiconductor device package
US20090166895A1 (en) Circuit substrate, circuit device and manufacturing process thereof
TW200917391A (en) Three-dimensional circuitry formed on integrated circuit device using two-dimensional fabrication
US10141264B2 (en) Method and structure for wafer level packaging with large contact area
CN105990507B (zh) 侧照式发光二极管结构及其制造方法
JP2001085361A (ja) 半導体装置およびその製造方法
US3964157A (en) Method of mounting semiconductor chips
US11742331B2 (en) Method of manufacturing a semiconductor package including a dam structure surrounding a semiconductor chip mounting region
JP2003086762A (ja) 半導体装置及びその製造方法
JP2004304081A (ja) 半導体チップ、半導体装置及びその製造方法
TW200841403A (en) Sensor-type semiconductor device and manufacturing method thereof
EP0988650A2 (en) Method of manufacturing semiconductor devices with "chip size package"
CN107093579A (zh) 半导体圆片级封装方法、器件及封装用刀具
US7514769B1 (en) Micro surface mount die package and method
JPH1197616A (ja) マルチチップモジュールおよびその製造方法
CN108389957A (zh) 一种滤波器芯片封装结构和封装方法
TW448522B (en) Structure body of semiconductor chips with stacked connection in a flip chip manner and its manufacturing method
CN207651470U (zh) 芯片的封装结构
CN208093592U (zh) 一种滤波器芯片封装结构
JPS56148857A (en) Semiconductor device
CN106158762A (zh) 电子封装件及其制法
TW586169B (en) Semiconductor die package with semiconductor die having side electrical connection

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent