TW429409B - Alignment method - Google Patents

Alignment method

Info

Publication number
TW429409B
TW429409B TW087112786A TW87112786A TW429409B TW 429409 B TW429409 B TW 429409B TW 087112786 A TW087112786 A TW 087112786A TW 87112786 A TW87112786 A TW 87112786A TW 429409 B TW429409 B TW 429409B
Authority
TW
Taiwan
Prior art keywords
alignment
group
chip
alignment method
decided
Prior art date
Application number
TW087112786A
Other languages
English (en)
Inventor
Seiji Matsuura
Original Assignee
Nippon Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co filed Critical Nippon Electric Co
Application granted granted Critical
Publication of TW429409B publication Critical patent/TW429409B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW087112786A 1997-08-04 1998-08-03 Alignment method TW429409B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9208999A JP3047863B2 (ja) 1997-08-04 1997-08-04 アライメント方法

Publications (1)

Publication Number Publication Date
TW429409B true TW429409B (en) 2001-04-11

Family

ID=16565640

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087112786A TW429409B (en) 1997-08-04 1998-08-03 Alignment method

Country Status (5)

Country Link
US (1) US6084678A (zh)
JP (1) JP3047863B2 (zh)
KR (1) KR100271048B1 (zh)
CN (1) CN1115719C (zh)
TW (1) TW429409B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002289507A (ja) 2001-03-28 2002-10-04 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3609761B2 (ja) 2001-07-19 2005-01-12 三洋電機株式会社 半導体装置の製造方法
KR100519789B1 (ko) * 2003-03-20 2005-10-10 삼성전자주식회사 반도체 기판의 얼라인 방법
US6948254B2 (en) * 2003-10-27 2005-09-27 Micronic Laser Systems Ab Method for calibration of a metrology stage
CN100406846C (zh) * 2006-03-20 2008-07-30 友达光电股份有限公司 对准检测装置及对准偏移量的检测方法
CN101465311B (zh) * 2007-12-19 2011-12-07 北京北方微电子基地设备工艺研究中心有限责任公司 基片偏移的诊断及校正方法和诊断及校正装置
CN103097956B (zh) * 2010-02-26 2016-01-27 密克罗尼克麦达塔公司 用于执行图案对准的方法和装置
US20120049186A1 (en) * 2010-08-31 2012-03-01 Li Calvin K Semiconductor structures
CN103811298B (zh) * 2012-11-15 2016-11-09 上海华虹宏力半导体制造有限公司 测试对准使用芯片的制作方法
KR102237751B1 (ko) 2014-12-08 2021-04-12 삼성디스플레이 주식회사 표시 장치
CN105449054B (zh) * 2015-11-11 2017-09-08 海迪科（南通）光电科技有限公司 Led芯片的精确定位方法
US10115687B2 (en) * 2017-02-03 2018-10-30 Applied Materials, Inc. Method of pattern placement correction
WO2019067809A2 (en) * 2017-09-29 2019-04-04 Rudolph Technologies, Inc. SYSTEM AND METHOD FOR OPTIMIZING LITHOGRAPHIC EXPOSURE METHOD
CN108681623A (zh) * 2018-04-11 2018-10-19 上海华虹宏力半导体制造有限公司 放置划片槽图形的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568189A (en) * 1983-09-26 1986-02-04 The United States Of America As Represented By The Secretary Of The Navy Apparatus and method for aligning a mask and wafer in the fabrication of integrated circuits
US4991962A (en) * 1989-01-04 1991-02-12 Kantilal Jain High precision alignment system for microlithography
EP0824225A3 (en) * 1989-09-26 1998-03-04 Canon Kabushiki Kaisha Alignment method
US5521036A (en) * 1992-07-27 1996-05-28 Nikon Corporation Positioning method and apparatus
US5559601A (en) * 1994-01-24 1996-09-24 Svg Lithography Systems, Inc. Mask and wafer diffraction grating alignment system wherein the diffracted light beams return substantially along an incident angle
JPH08233555A (ja) * 1994-12-28 1996-09-13 Matsushita Electric Ind Co Ltd レジストパターンの測定方法及びレジストパターンの測定装置

Also Published As

Publication number Publication date
JPH1154404A (ja) 1999-02-26
CN1115719C (zh) 2003-07-23
CN1209643A (zh) 1999-03-03
KR100271048B1 (ko) 2000-12-01
US6084678A (en) 2000-07-04
JP3047863B2 (ja) 2000-06-05
KR19990023339A (ko) 1999-03-25

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees