JPS6453545A - Semiconductor substrate having alignment mark and alignment using said mark - Google Patents

Semiconductor substrate having alignment mark and alignment using said mark

Info

Publication number
JPS6453545A
JPS6453545A JP62210606A JP21060687A JPS6453545A JP S6453545 A JPS6453545 A JP S6453545A JP 62210606 A JP62210606 A JP 62210606A JP 21060687 A JP21060687 A JP 21060687A JP S6453545 A JPS6453545 A JP S6453545A
Authority
JP
Japan
Prior art keywords
alignment
alignment marks
mark
wafer
marks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62210606A
Other languages
Japanese (ja)
Inventor
Koichiro Tsujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62210606A priority Critical patent/JPS6453545A/en
Publication of JPS6453545A publication Critical patent/JPS6453545A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

PURPOSE:To correct a position to be aligned by a method wherein, in a semiconductor substrate where an alignment mark used for alignment of a wafer with a reticle has been formed, at least three alignment marks are arranged inside a region on the water to be aligned with the reticle. CONSTITUTION:Four wafer alignment marks 6a, 6b, 6c, 6d are arranged symmetrically; however, it is enough if at least three or more wafer alignment marks are arranged inside one shot on a wafer. The alignment marks refer to the marks with which both a position in X coordinates and a position in Y coordinates can be identified by referring to one mark. Accordingly, if the alignment marks for X coordinates use are separated from those for Y coordinates use, at least three marks are required for X use and for Y use, respectively. It is preferable that a position of the wafer alignment marks is away from the center of a shot from a viewpoint that an error in a reduction magnification and an error in a reticle rotation are measured; the measuring accuracy of the errors is enhanced. In addition, the wafer alignment marks are situated at an edge inside the shot, it becomes easy to manufacture a reticle of a semiconductor device.
JP62210606A 1987-08-25 1987-08-25 Semiconductor substrate having alignment mark and alignment using said mark Pending JPS6453545A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210606A JPS6453545A (en) 1987-08-25 1987-08-25 Semiconductor substrate having alignment mark and alignment using said mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210606A JPS6453545A (en) 1987-08-25 1987-08-25 Semiconductor substrate having alignment mark and alignment using said mark

Publications (1)

Publication Number Publication Date
JPS6453545A true JPS6453545A (en) 1989-03-01

Family

ID=16592109

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210606A Pending JPS6453545A (en) 1987-08-25 1987-08-25 Semiconductor substrate having alignment mark and alignment using said mark

Country Status (1)

Country Link
JP (1) JPS6453545A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122473A (en) * 1993-10-21 1995-05-12 Nikon Corp Exposure method
JPH0875542A (en) * 1994-09-05 1996-03-22 Otsuka Denshi Kk Method for measuring quantity of light for display pixel, and method and apparatus for inspecting display screen
JP2020506433A (en) * 2017-02-03 2020-02-27 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Pattern placement correction method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07122473A (en) * 1993-10-21 1995-05-12 Nikon Corp Exposure method
JPH0875542A (en) * 1994-09-05 1996-03-22 Otsuka Denshi Kk Method for measuring quantity of light for display pixel, and method and apparatus for inspecting display screen
JP2020506433A (en) * 2017-02-03 2020-02-27 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Pattern placement correction method

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