JPS5730330A - Mask aligner - Google Patents

Mask aligner

Info

Publication number
JPS5730330A
JPS5730330A JP10531380A JP10531380A JPS5730330A JP S5730330 A JPS5730330 A JP S5730330A JP 10531380 A JP10531380 A JP 10531380A JP 10531380 A JP10531380 A JP 10531380A JP S5730330 A JPS5730330 A JP S5730330A
Authority
JP
Japan
Prior art keywords
wafer
alignment
tolerance
flatness
5mum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10531380A
Other languages
Japanese (ja)
Inventor
Yasuo Katsuyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP10531380A priority Critical patent/JPS5730330A/en
Publication of JPS5730330A publication Critical patent/JPS5730330A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To improve the effect of flatness correction of a water when an alignment is performed by a method wherein the warpage of the wafer is measured using a flatness measuring device when a noncontact type alignment is performed, an exposing work is performed after vacuum attraction has been adjusted in accordance with the data obtained from said measurement. CONSTITUTION:The deformation and warpage of the wafer 3 placed on a wafer cluck 2 are measured by the flatness measuring instrument 1. On the other hand, the tolerance of alignment accuracy is inputted to an arithmetic operational unit and if the tolerance is within +5mum it will be all right and requires no action to be taken, but if the tolerance exceeds 5mum, a corrective action should be taken by adjusting the vacuum attraction controlling a leak valve 4 in accordance with the signal sent from arithmetic operational device. Through these procedures, the effect of the flatness correction of the wafer when performing an alignment using the noncontact system can be improved.
JP10531380A 1980-07-31 1980-07-31 Mask aligner Pending JPS5730330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10531380A JPS5730330A (en) 1980-07-31 1980-07-31 Mask aligner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10531380A JPS5730330A (en) 1980-07-31 1980-07-31 Mask aligner

Publications (1)

Publication Number Publication Date
JPS5730330A true JPS5730330A (en) 1982-02-18

Family

ID=14404209

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10531380A Pending JPS5730330A (en) 1980-07-31 1980-07-31 Mask aligner

Country Status (1)

Country Link
JP (1) JPS5730330A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140248A (en) * 1984-12-11 1986-06-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Switchgear for communication
JP2007123872A (en) * 2005-10-18 2007-05-17 Asml Netherlands Bv Lithography apparatus
US20160048087A1 (en) * 2014-08-12 2016-02-18 Macronix International Co., Ltd. Scanner and method for performing exposure process on wafer

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140248A (en) * 1984-12-11 1986-06-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Switchgear for communication
JPH0473822B2 (en) * 1984-12-11 1992-11-24
JP2007123872A (en) * 2005-10-18 2007-05-17 Asml Netherlands Bv Lithography apparatus
JP4588010B2 (en) * 2005-10-18 2010-11-24 エーエスエムエル ネザーランズ ビー．ブイ． Lithographic apparatus
US20160048087A1 (en) * 2014-08-12 2016-02-18 Macronix International Co., Ltd. Scanner and method for performing exposure process on wafer

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