JPS5463680A - Production of mask for integrated circuit - Google Patents

Production of mask for integrated circuit

Info

Publication number
JPS5463680A
JPS5463680A JP12922777A JP12922777A JPS5463680A JP S5463680 A JPS5463680 A JP S5463680A JP 12922777 A JP12922777 A JP 12922777A JP 12922777 A JP12922777 A JP 12922777A JP S5463680 A JPS5463680 A JP S5463680A
Authority
JP
Japan
Prior art keywords
mask
compounded
negatives
marks
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12922777A
Other languages
Japanese (ja)
Inventor
Hiroshi Otsuka
Hideo Nagata
Masanori Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP12922777A priority Critical patent/JPS5463680A/en
Publication of JPS5463680A publication Critical patent/JPS5463680A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching

Abstract

PURPOSE: To make it possible to control exactly mutual relative positions of masks by making it possible to detect individual factors such as rotation error and positional slippage when plural masks for IC are compounded to produce a master mask.
CONSTITUTION: Marks 33 for checking split chip 32 are provided on intermediate negative (mask for IC) 31 and are formed on the outside circumference of chip 32 and are arranged on both center lines and corners in the position adjacent to another intermediate negative split chip. When plural intermediate negatives like this are compounded to produce master mask 41 for large-scale LSI chips, mutual relative positions of intermediate negatives 31 are measured and controlled by check marks 43. By arranging marks 33, rotation error and positional slippage can be detected individually, and negatives can be compounded with a high precision.
COPYRIGHT: (C)1979,JPO&Japio
JP12922777A 1977-10-29 1977-10-29 Production of mask for integrated circuit Pending JPS5463680A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12922777A JPS5463680A (en) 1977-10-29 1977-10-29 Production of mask for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12922777A JPS5463680A (en) 1977-10-29 1977-10-29 Production of mask for integrated circuit

Publications (1)

Publication Number Publication Date
JPS5463680A true JPS5463680A (en) 1979-05-22

Family

ID=15004291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12922777A Pending JPS5463680A (en) 1977-10-29 1977-10-29 Production of mask for integrated circuit

Country Status (1)

Country Link
JP (1) JPS5463680A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584927A (en) * 1981-06-30 1983-01-12 Nec Ic Microcomput Syst Ltd Formation of pattern
JPS6244740A (en) * 1985-08-23 1987-02-26 Hoya Corp Formation of pattern
JPS6247642A (en) * 1985-08-27 1987-03-02 Hoya Corp Pattern forming method
JPS63151948A (en) * 1986-12-15 1988-06-24 Nec Corp Exposing mask
JPS63223750A (en) * 1987-03-13 1988-09-19 Nec Corp Mask for exposure
JPH01193743A (en) * 1988-01-28 1989-08-03 Nec Kyushu Ltd Reticle mask
JPH02127641A (en) * 1988-11-08 1990-05-16 Nec Corp Reticle for semiconductor integrated circuit
JPH04177348A (en) * 1990-11-13 1992-06-24 Nec Yamaguchi Ltd Reticule for reduction projection aligner
WO1999034255A1 (en) * 1997-12-25 1999-07-08 Nikon Corporation Method and apparatus for manufacturing photomask and method of fabricating device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040752A (en) * 1973-08-10 1975-04-14
JPS513878A (en) * 1974-07-01 1976-01-13 Hitachi Ltd
JPS5236825A (en) * 1975-09-19 1977-03-22 Nippon Kokan Kk Method of outer panel wall for building

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040752A (en) * 1973-08-10 1975-04-14
JPS513878A (en) * 1974-07-01 1976-01-13 Hitachi Ltd
JPS5236825A (en) * 1975-09-19 1977-03-22 Nippon Kokan Kk Method of outer panel wall for building

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS584927A (en) * 1981-06-30 1983-01-12 Nec Ic Microcomput Syst Ltd Formation of pattern
JPS6244740A (en) * 1985-08-23 1987-02-26 Hoya Corp Formation of pattern
JPH0355815B2 (en) * 1985-08-23 1991-08-26
JPS6247642A (en) * 1985-08-27 1987-03-02 Hoya Corp Pattern forming method
JPS63151948A (en) * 1986-12-15 1988-06-24 Nec Corp Exposing mask
JPS63223750A (en) * 1987-03-13 1988-09-19 Nec Corp Mask for exposure
JPH01193743A (en) * 1988-01-28 1989-08-03 Nec Kyushu Ltd Reticle mask
JPH02127641A (en) * 1988-11-08 1990-05-16 Nec Corp Reticle for semiconductor integrated circuit
JPH04177348A (en) * 1990-11-13 1992-06-24 Nec Yamaguchi Ltd Reticule for reduction projection aligner
WO1999034255A1 (en) * 1997-12-25 1999-07-08 Nikon Corporation Method and apparatus for manufacturing photomask and method of fabricating device
US6677088B2 (en) 1997-12-25 2004-01-13 Nikon Corporation Photomask producing method and apparatus and device manufacturing method

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