JPS57170531A - Projection exposing method - Google Patents

Projection exposing method

Info

Publication number
JPS57170531A
JPS57170531A JP56055776A JP5577681A JPS57170531A JP S57170531 A JPS57170531 A JP S57170531A JP 56055776 A JP56055776 A JP 56055776A JP 5577681 A JP5577681 A JP 5577681A JP S57170531 A JPS57170531 A JP S57170531A
Authority
JP
Japan
Prior art keywords
pattern
exposed
chip
wafer
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56055776A
Other languages
Japanese (ja)
Inventor
Takashi Aoyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56055776A priority Critical patent/JPS57170531A/en
Publication of JPS57170531A publication Critical patent/JPS57170531A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Projection-Type Copiers In General (AREA)

Abstract

PURPOSE:To eliminate the production of a defect due to a dust existing on a reticle by employing a reticle formed by aligning two same IC pattern in parallel and exposing it while performing steps and repeat to project two pattern on the same position on a wafer. CONSTITUTION:IC patterns A, A' of the same content are formed in a reticle 1, and the patterns A, A' are simultaneously contraction-projected and edposed by one exposure on a wafer 2. After the wafer 2 is then moved in the amount corresponding to one chip, the A, A' are simultaneously projected and exposed in the state that the pattern A' is double exposed on the chip of the pattern A exposed on the wafer 2. Thereafter, the pattern is exposed while sequentially moving the wafter 2 in the amount corresponding to one chip. In this manner, the patterns A, A' are double exposed for one chip except two columns at both sides of the matrix of the exposed chip, and no defect remains even after a development even if a dust 3 exists on the pattern A or A'.
JP56055776A 1981-04-14 1981-04-14 Projection exposing method Pending JPS57170531A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56055776A JPS57170531A (en) 1981-04-14 1981-04-14 Projection exposing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56055776A JPS57170531A (en) 1981-04-14 1981-04-14 Projection exposing method

Publications (1)

Publication Number Publication Date
JPS57170531A true JPS57170531A (en) 1982-10-20

Family

ID=13008279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56055776A Pending JPS57170531A (en) 1981-04-14 1981-04-14 Projection exposing method

Country Status (1)

Country Link
JP (1) JPS57170531A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59143324A (en) * 1983-02-03 1984-08-16 Oki Electric Ind Co Ltd Formation of pattern
CN102445855A (en) * 2010-10-14 2012-05-09 中芯国际集成电路制造(上海)有限公司 Double-layer exposure compensation method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59143324A (en) * 1983-02-03 1984-08-16 Oki Electric Ind Co Ltd Formation of pattern
CN102445855A (en) * 2010-10-14 2012-05-09 中芯国际集成电路制造(上海)有限公司 Double-layer exposure compensation method

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