TW418492B - Method of manufacturing a semiconductor integrated circuit device - Google Patents

Method of manufacturing a semiconductor integrated circuit device Download PDF

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Publication number
TW418492B
TW418492B TW087106611A TW87106611A TW418492B TW 418492 B TW418492 B TW 418492B TW 087106611 A TW087106611 A TW 087106611A TW 87106611 A TW87106611 A TW 87106611A TW 418492 B TW418492 B TW 418492B
Authority
TW
Taiwan
Prior art keywords
silicon oxide
oxide film
film
groove
semiconductor substrate
Prior art date
Application number
TW087106611A
Other languages
English (en)
Chinese (zh)
Inventor
Yasushi Matsuda
Hirohiko Yamamoto
Hirofumi Shimizu
Masamichi Kobayashi
Shuji Ikeda
Original Assignee
Hitachi Ulsi Sys Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ulsi Sys Co Ltd, Hitachi Ltd filed Critical Hitachi Ulsi Sys Co Ltd
Application granted granted Critical
Publication of TW418492B publication Critical patent/TW418492B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0148—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0151—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0143—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations comprising concurrently refilling multiple trenches having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H10W10/0145—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape
    • H10W10/0147—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations of trenches having shapes other than rectangular or V-shape the shapes being altered by a local oxidation of silicon process, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations

Landscapes

  • Element Separation (AREA)
TW087106611A 1997-04-30 1998-04-29 Method of manufacturing a semiconductor integrated circuit device TW418492B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9112467A JPH10303289A (ja) 1997-04-30 1997-04-30 半導体集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
TW418492B true TW418492B (en) 2001-01-11

Family

ID=14587379

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087106611A TW418492B (en) 1997-04-30 1998-04-29 Method of manufacturing a semiconductor integrated circuit device

Country Status (4)

Country Link
US (1) US6057241A (https=)
JP (1) JPH10303289A (https=)
KR (1) KR19980081825A (https=)
TW (1) TW418492B (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP2000082808A (ja) * 1998-09-04 2000-03-21 Toshiba Corp 半導体装置及びその製造方法
US6599812B1 (en) * 1998-10-23 2003-07-29 Stmicroelectronics S.R.L. Manufacturing method for a thick oxide layer
JP3571236B2 (ja) * 1998-11-09 2004-09-29 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3955404B2 (ja) * 1998-12-28 2007-08-08 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP4012350B2 (ja) * 1999-10-06 2007-11-21 株式会社ルネサステクノロジ 半導体集積回路装置およびその製造方法
KR100345400B1 (ko) * 1999-10-08 2002-07-26 한국전자통신연구원 가장자리에 두꺼운 산화막을 갖는 트렌치 형성방법
JP2001144170A (ja) * 1999-11-11 2001-05-25 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2001332613A (ja) * 2000-05-24 2001-11-30 Nec Corp 半導体装置の製造方法
JP2001345375A (ja) * 2000-05-31 2001-12-14 Miyazaki Oki Electric Co Ltd 半導体装置および半導体装置の製造方法
US6406976B1 (en) * 2000-09-18 2002-06-18 Motorola, Inc. Semiconductor device and process for forming the same
JP4285899B2 (ja) 2000-10-10 2009-06-24 三菱電機株式会社 溝を有する半導体装置
US6451704B1 (en) * 2001-05-07 2002-09-17 Chartered Semiconductor Manufacturing Ltd. Method for forming PLDD structure with minimized lateral dopant diffusion
ITTO20011038A1 (it) * 2001-10-30 2003-04-30 St Microelectronics Srl Procedimento per la fabbricazione di una fetta semiconduttrice integrante dispositivi elettronici e una struttura per il disaccoppiamento el
JP4173672B2 (ja) * 2002-03-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置及びその製造方法
DE10259728B4 (de) * 2002-12-19 2008-01-17 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung einer Grabenisolationsstruktur und Verfahren zum Steuern eines Grades an Kantenrundung einer Grabenisolationsstruktur in einem Halbleiterbauelement
JP2003249546A (ja) * 2003-01-06 2003-09-05 Seiko Epson Corp 半導体ウエハおよびその処理方法ならびに半導体装置の製造方法
JP2005347636A (ja) * 2004-06-04 2005-12-15 Az Electronic Materials Kk トレンチ・アイソレーション構造の形成方法
JP2006332404A (ja) * 2005-05-27 2006-12-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
KR100698085B1 (ko) * 2005-12-29 2007-03-23 동부일렉트로닉스 주식회사 트랜치 형성방법
JP2009283494A (ja) * 2008-05-19 2009-12-03 Seiko Epson Corp 半導体装置の製造方法
JP2009283493A (ja) * 2008-05-19 2009-12-03 Seiko Epson Corp 半導体装置の製造方法
JP2009283492A (ja) * 2008-05-19 2009-12-03 Seiko Epson Corp 半導体装置の製造方法
WO2020098738A1 (en) * 2018-11-16 2020-05-22 Changxin Memory Technologies, Inc. Semiconductor device and fabricating method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576834A (en) * 1985-05-20 1986-03-18 Ncr Corporation Method for forming trench isolation structures
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process
JPH07105436B2 (ja) * 1986-07-18 1995-11-13 株式会社東芝 半導体装置の製造方法
US4906585A (en) * 1987-08-04 1990-03-06 Siemens Aktiengesellschaft Method for manufacturing wells for CMOS transistor circuits separated by insulating trenches

Also Published As

Publication number Publication date
US6057241A (en) 2000-05-02
JPH10303289A (ja) 1998-11-13
KR19980081825A (ko) 1998-11-25

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