TW363256B - Semiconductor integrated circuit, design and manufacturing method thereof - Google Patents

Semiconductor integrated circuit, design and manufacturing method thereof

Info

Publication number
TW363256B
TW363256B TW086118618A TW86118618A TW363256B TW 363256 B TW363256 B TW 363256B TW 086118618 A TW086118618 A TW 086118618A TW 86118618 A TW86118618 A TW 86118618A TW 363256 B TW363256 B TW 363256B
Authority
TW
Taiwan
Prior art keywords
integrated circuit
source
semiconductor integrated
relay
drain
Prior art date
Application number
TW086118618A
Other languages
English (en)
Inventor
Kenichiro Mimoto
Motohiro Enkaku
Takehiko Hojo
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW363256B publication Critical patent/TW363256B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
TW086118618A 1996-12-25 1997-12-10 Semiconductor integrated circuit, design and manufacturing method thereof TW363256B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34572096A JP3352895B2 (ja) 1996-12-25 1996-12-25 半導体集積回路、半導体集積回路の設計方法および製造方法

Publications (1)

Publication Number Publication Date
TW363256B true TW363256B (en) 1999-07-01

Family

ID=18378514

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086118618A TW363256B (en) 1996-12-25 1997-12-10 Semiconductor integrated circuit, design and manufacturing method thereof

Country Status (3)

Country Link
US (1) US5929469A (zh)
JP (1) JP3352895B2 (zh)
TW (1) TW363256B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753611B1 (en) 1999-09-10 2004-06-22 Kabushiki Kaisha Toshiba Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program
TWI707414B (zh) * 2015-12-16 2020-10-11 美商Ｐｄｆ對策公司 包含啟用ncem之填充單元格之doe的積體電路

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DE19740904B4 (de) * 1997-09-17 2004-10-28 Infineon Technologies Ag Verfahren zum Beseitigen von Sauerstoff-Restverunreinigungen aus tiegelgezogenen Siliziumwafern
JP2000077609A (ja) 1998-08-28 2000-03-14 Hitachi Ltd 半導体集積回路装置
US6844600B2 (en) * 1998-09-03 2005-01-18 Micron Technology, Inc. ESD/EOS protection structure for integrated circuit devices
JP3349989B2 (ja) * 1999-06-18 2002-11-25 エヌイーシーマイクロシステム株式会社 半導体集積回路装置及びそのレイアウト方法及び装置
US6823499B1 (en) * 2001-09-18 2004-11-23 Lsi Logic Corporation Method for designing application specific integrated circuit structure
JP2004342757A (ja) * 2003-05-14 2004-12-02 Toshiba Corp 半導体集積回路及びその設計方法
JP4683833B2 (ja) * 2003-10-31 2011-05-18 株式会社半導体エネルギー研究所 機能回路及びその設計方法
US7328417B2 (en) * 2003-12-09 2008-02-05 Lsi Logic Corporation Cell-based method for creating slotted metal in semiconductor designs
JP2005197428A (ja) * 2004-01-07 2005-07-21 Toshiba Microelectronics Corp 半導体集積回路
KR100599431B1 (ko) * 2004-07-14 2006-07-14 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
WO2006041142A1 (en) * 2004-10-13 2006-04-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit and designing method of the same, and electronic apparatus using the same
JP2006147961A (ja) * 2004-11-22 2006-06-08 Elpida Memory Inc 半導体集積回路
US20060108616A1 (en) * 2004-11-22 2006-05-25 Himax Technologies, Inc. High-voltage metal-oxide-semiconductor transistor
US20060208317A1 (en) * 2005-03-17 2006-09-21 Tsuoe-Hsiang Liao Layout structure of semiconductor cells
US9035359B2 (en) 2006-03-09 2015-05-19 Tela Innovations, Inc. Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods
US7956421B2 (en) 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US8245180B2 (en) 2006-03-09 2012-08-14 Tela Innovations, Inc. Methods for defining and using co-optimized nanopatterns for integrated circuit design and apparatus implementing same
US8448102B2 (en) 2006-03-09 2013-05-21 Tela Innovations, Inc. Optimizing layout of irregular structures in regular layout context
US8247846B2 (en) 2006-03-09 2012-08-21 Tela Innovations, Inc. Oversized contacts and vias in semiconductor chip defined by linearly constrained topology
US8839175B2 (en) 2006-03-09 2014-09-16 Tela Innovations, Inc. Scalable meta-data objects
US8653857B2 (en) 2006-03-09 2014-02-18 Tela Innovations, Inc. Circuitry and layouts for XOR and XNOR logic
US7763534B2 (en) 2007-10-26 2010-07-27 Tela Innovations, Inc. Methods, structures and designs for self-aligning local interconnects used in integrated circuits
US9230910B2 (en) 2006-03-09 2016-01-05 Tela Innovations, Inc. Oversized contacts and vias in layout defined by linearly constrained topology
US8225261B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining contact grid in dynamic array architecture
US8658542B2 (en) 2006-03-09 2014-02-25 Tela Innovations, Inc. Coarse grid design methods and structures
US7446352B2 (en) 2006-03-09 2008-11-04 Tela Innovations, Inc. Dynamic array architecture
US8225239B2 (en) 2006-03-09 2012-07-17 Tela Innovations, Inc. Methods for defining and utilizing sub-resolution features in linear topology
US9563733B2 (en) 2009-05-06 2017-02-07 Tela Innovations, Inc. Cell circuit and layout with linear finfet structures
US8541879B2 (en) 2007-12-13 2013-09-24 Tela Innovations, Inc. Super-self-aligned contacts and method for making the same
US9009641B2 (en) 2006-03-09 2015-04-14 Tela Innovations, Inc. Circuits with linear finfet structures
US8286107B2 (en) 2007-02-20 2012-10-09 Tela Innovations, Inc. Methods and systems for process compensation technique acceleration
US7888705B2 (en) 2007-08-02 2011-02-15 Tela Innovations, Inc. Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same
US8667443B2 (en) 2007-03-05 2014-03-04 Tela Innovations, Inc. Integrated circuit cell library for multiple patterning
US8453094B2 (en) 2008-01-31 2013-05-28 Tela Innovations, Inc. Enforcement of semiconductor structure regularity for localized transistors and interconnect
US7939443B2 (en) 2008-03-27 2011-05-10 Tela Innovations, Inc. Methods for multi-wire routing and apparatus implementing same
US20110089141A1 (en) * 2008-06-17 2011-04-21 Ulvac,Inc. Method for the production of multi-stepped substrate
KR101903975B1 (ko) 2008-07-16 2018-10-04 텔라 이노베이션스, 인코포레이티드 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현
US9122832B2 (en) 2008-08-01 2015-09-01 Tela Innovations, Inc. Methods for controlling microloading variation in semiconductor wafer layout and fabrication
US20100187611A1 (en) * 2009-01-27 2010-07-29 Roberto Schiwon Contacts in Semiconductor Devices
US8661392B2 (en) 2009-10-13 2014-02-25 Tela Innovations, Inc. Methods for cell boundary encroachment and layouts implementing the Same
US8815667B2 (en) * 2009-12-16 2014-08-26 Micron Technology, Inc. Transistors with an extension region having strips of differing conductivity type and methods of forming the same
US9159627B2 (en) 2010-11-12 2015-10-13 Tela Innovations, Inc. Methods for linewidth modification and apparatus implementing the same
US8507957B2 (en) * 2011-05-02 2013-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit layouts with power rails under bottom metal layer
JP6084922B2 (ja) 2011-06-23 2017-02-22 パナソニック株式会社 固体撮像装置
US9292649B2 (en) * 2013-11-18 2016-03-22 Taiwan Semiconductor Manufacturing Co., Ltd. Different scaling ratio in FEOL / MOL/ BEOL
CN109037342A (zh) * 2018-08-29 2018-12-18 广东工业大学 一种晶体管、堆叠晶体管及射频开关芯片
US11164794B2 (en) * 2019-08-04 2021-11-02 Globalfoundries U.S. Inc. Semiconductor structures in a wide gate pitch region of semiconductor devices

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EP0523967B1 (en) * 1991-07-18 1999-09-22 Fujitsu Limited Transistor arrangement for forming basic cell of master-slice type semiconductor integrated circuit device and master-slice type semiconductor integrated circuit device
JP3061928B2 (ja) * 1992-03-30 2000-07-10 日本電気株式会社 半導体装置
TW306054B (en) * 1996-07-16 1997-05-21 Winbond Electronics Corp Bit line pull up circuit of static random access memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6753611B1 (en) 1999-09-10 2004-06-22 Kabushiki Kaisha Toshiba Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program
US6826742B2 (en) 1999-09-10 2004-11-30 Kabushiki Kaisha Toshiba Semiconductor device, designing method thereof, and recording medium storing semiconductor designing program
US7444614B2 (en) 1999-09-10 2008-10-28 Kabushiki Kaisha Toshiba Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal
TWI707414B (zh) * 2015-12-16 2020-10-11 美商Ｐｄｆ對策公司 包含啟用ncem之填充單元格之doe的積體電路

Also Published As

Publication number Publication date
US5929469A (en) 1999-07-27
JPH10189600A (ja) 1998-07-21
JP3352895B2 (ja) 2002-12-03

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MM4A Annulment or lapse of patent due to non-payment of fees