TW322553B - - Google Patents
Download PDFInfo
- Publication number
- TW322553B TW322553B TW085106605A TW85106605A TW322553B TW 322553 B TW322553 B TW 322553B TW 085106605 A TW085106605 A TW 085106605A TW 85106605 A TW85106605 A TW 85106605A TW 322553 B TW322553 B TW 322553B
- Authority
- TW
- Taiwan
- Prior art keywords
- signal
- input
- circuit
- amplitude
- clock signal
- Prior art date
Links
- 239000000872 buffer Substances 0.000 claims description 57
- 239000004065 semiconductor Substances 0.000 claims description 37
- 230000001360 synchronised effect Effects 0.000 claims description 36
- 230000005540 biological transmission Effects 0.000 claims description 27
- 230000004044 response Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 27
- 230000000875 corresponding effect Effects 0.000 description 25
- 230000009471 action Effects 0.000 description 15
- 230000006870 function Effects 0.000 description 9
- 230000003321 amplification Effects 0.000 description 8
- 230000000295 complement effect Effects 0.000 description 8
- 238000003199 nucleic acid amplification method Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 230000000630 rising effect Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 101100113692 Caenorhabditis elegans clk-2 gene Proteins 0.000 description 3
- 230000010365 information processing Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- VUDQSRFCCHQIIU-UHFFFAOYSA-N 1-(3,5-dichloro-2,6-dihydroxy-4-methoxyphenyl)hexan-1-one Chemical compound CCCCCC(=O)C1=C(O)C(Cl)=C(OC)C(Cl)=C1O VUDQSRFCCHQIIU-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000002079 cooperative effect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002023 wood Substances 0.000 description 2
- 101100420776 Arabidopsis thaliana SYN1 gene Proteins 0.000 description 1
- 101100443238 Caenorhabditis elegans dif-1 gene Proteins 0.000 description 1
- 101150001108 DIF1 gene Proteins 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 230000002496 gastric effect Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4082—Address Buffers; level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19422995A JP3724654B2 (ja) | 1995-07-06 | 1995-07-06 | 半導体集積回路装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW322553B true TW322553B (https=) | 1997-12-11 |
Family
ID=16321116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW085106605A TW322553B (https=) | 1995-07-06 | 1996-06-03 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US5801554A (https=) |
| JP (1) | JP3724654B2 (https=) |
| KR (1) | KR100398165B1 (https=) |
| TW (1) | TW322553B (https=) |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0158762B1 (ko) * | 1994-02-17 | 1998-12-01 | 세키자와 다다시 | 반도체 장치 |
| JP4042069B2 (ja) * | 1996-12-26 | 2008-02-06 | 聯華電子股▲分▼有限公司 | 積分入力型入力回路およびそのテスト方法 |
| KR100265591B1 (ko) * | 1997-05-19 | 2000-11-01 | 김영환 | 클럭입력버퍼를분리시킨반도체메모리장치 |
| US5912567A (en) * | 1997-10-22 | 1999-06-15 | Sun Microsystems, Inc. | Dual differential comparator with weak equalization and narrow metastability region |
| US8598332B1 (en) * | 1998-04-08 | 2013-12-03 | Bayer Cropscience N.V. | Methods and means for obtaining modified phenotypes |
| KR100272167B1 (ko) * | 1998-07-13 | 2000-11-15 | 윤종용 | 동기식 반도체 메모리 장치의 기준 신호 발생 회로 |
| JP3725715B2 (ja) | 1998-11-27 | 2005-12-14 | 株式会社東芝 | クロック同期システム |
| US6218863B1 (en) | 1999-04-12 | 2001-04-17 | Intel Corporation | Dual mode input/output interface circuit |
| US6552716B1 (en) * | 1999-05-05 | 2003-04-22 | Logitech Europe, S.A. | Transmission of differential optical detector signal over a single line |
| JP4216415B2 (ja) | 1999-08-31 | 2009-01-28 | 株式会社ルネサステクノロジ | 半導体装置 |
| JP4263818B2 (ja) | 1999-09-20 | 2009-05-13 | 富士通マイクロエレクトロニクス株式会社 | 半導体集積回路 |
| US6392448B1 (en) | 2000-02-03 | 2002-05-21 | Teradyne, Inc. | Common-mode detection circuit with cross-coupled compensation |
| US6300804B1 (en) | 2000-02-09 | 2001-10-09 | Teradyne, Inc. | Differential comparator with dispersion reduction circuitry |
| JP4704541B2 (ja) * | 2000-04-27 | 2011-06-15 | エルピーダメモリ株式会社 | 半導体集積回路装置 |
| JP4190706B2 (ja) | 2000-07-03 | 2008-12-03 | Ｎｅｃエレクトロニクス株式会社 | 半導体装置 |
| JP2002023710A (ja) * | 2000-07-06 | 2002-01-25 | Hitachi Ltd | 液晶表示装置 |
| KR100374641B1 (ko) * | 2000-11-24 | 2003-03-04 | 삼성전자주식회사 | 스탠바이 모드에서 지연동기 루프회로의 전력소모를감소시키기 위한 제어회로를 구비하는 반도체 메모리장치및 이의 파우워 다운 제어방법 |
| JP2002246891A (ja) * | 2001-02-16 | 2002-08-30 | Mitsubishi Electric Corp | 入力バッファ回路および半導体装置 |
| DE10108820A1 (de) * | 2001-02-23 | 2002-09-12 | Infineon Technologies Ag | Verfahren zum Betrieb eines integrierten Speichers |
| JP4726334B2 (ja) * | 2001-06-13 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US6977529B2 (en) * | 2002-03-01 | 2005-12-20 | Ics Technologies, Inc. | Differential clock signal detection circuit |
| JP3667700B2 (ja) | 2002-03-06 | 2005-07-06 | エルピーダメモリ株式会社 | 入力バッファ回路及び半導体記憶装置 |
| US6798711B2 (en) * | 2002-03-19 | 2004-09-28 | Micron Technology, Inc. | Memory with address management |
| US7155630B2 (en) * | 2002-06-25 | 2006-12-26 | Micron Technology, Inc. | Method and unit for selectively enabling an input buffer based on an indication of a clock transition |
| KR100528789B1 (ko) * | 2003-08-01 | 2005-11-15 | 주식회사 하이닉스반도체 | 셀프 리프래쉬 모드 진입을 위한 클럭 인에이블 버퍼 |
| US7942901B2 (en) * | 2006-04-24 | 2011-05-17 | Warsaw Orthopedic, Inc. | Connector apparatus |
| KR100801032B1 (ko) * | 2006-11-15 | 2008-02-04 | 삼성전자주식회사 | 비휘발성 반도체 메모리 장치의 입력회로 및 비휘발성반도체 메모리 장치의 데이터 입력방법 |
| JP2009020953A (ja) * | 2007-07-11 | 2009-01-29 | Elpida Memory Inc | 同期式半導体装置及びこれを有するデータ処理システム |
| JP5600235B2 (ja) * | 2007-10-11 | 2014-10-01 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置、およびアドレスラッチの高速化方法 |
| KR102393425B1 (ko) * | 2015-10-20 | 2022-05-03 | 에스케이하이닉스 주식회사 | 반도체장치 및 반도체시스템 |
| KR102312446B1 (ko) * | 2017-09-19 | 2021-10-15 | 에스케이하이닉스 주식회사 | 반도체장치 |
| US12380047B2 (en) * | 2023-07-14 | 2025-08-05 | Qualcomm Incorporated | Expanded data link width for main band chip module connection in alternate modes |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4288706A (en) * | 1978-10-20 | 1981-09-08 | Texas Instruments Incorporated | Noise immunity in input buffer circuit for semiconductor memory |
| JPS628614A (ja) * | 1985-07-05 | 1987-01-16 | Nec Corp | 入力インバ−タ回路 |
| US5019729A (en) * | 1988-07-27 | 1991-05-28 | Kabushiki Kaisha Toshiba | TTL to CMOS buffer circuit |
| JPH04297119A (ja) * | 1990-09-28 | 1992-10-21 | Toshiba Corp | 半導体集積回路 |
| JP2523998B2 (ja) * | 1991-01-31 | 1996-08-14 | 株式会社東芝 | コンパレ―タ |
| KR930009702B1 (ko) * | 1991-04-17 | 1993-10-08 | 삼성전자 주식회사 | 외부 바이어스를 이용한 광대역 선형 이득 조절증폭기 |
-
1995
- 1995-07-06 JP JP19422995A patent/JP3724654B2/ja not_active Expired - Lifetime
-
1996
- 1996-06-03 TW TW085106605A patent/TW322553B/zh not_active IP Right Cessation
- 1996-07-03 US US08/674,917 patent/US5801554A/en not_active Expired - Lifetime
- 1996-07-04 KR KR1019960027010A patent/KR100398165B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP3724654B2 (ja) | 2005-12-07 |
| JPH0927192A (ja) | 1997-01-28 |
| KR970008609A (ko) | 1997-02-24 |
| US5801554A (en) | 1998-09-01 |
| KR100398165B1 (ko) | 2004-07-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW322553B (https=) | ||
| US6707756B2 (en) | System and method for translation of SDRAM and DDR signals | |
| US6504789B2 (en) | Semiconductor memory device | |
| JP3209485B2 (ja) | 自動プリチャージ機能を有する同期式メモリ装置 | |
| US5666324A (en) | Clock synchronous semiconductor memory device having current consumption reduced | |
| TW310430B (https=) | ||
| JPH08278916A (ja) | マルチチャネルメモリシステム、転送情報同期化方法及び信号転送回路 | |
| JPH07201172A (ja) | 半導体記憶装置 | |
| JPH1116346A (ja) | 半導体記憶装置 | |
| JPH0373495A (ja) | 半導体メモリ装置 | |
| US8036058B2 (en) | Symmetrically operating single-ended input buffer devices and methods | |
| EP0665484A2 (en) | Power reducing circuit for synchronous semiconductor device | |
| JP2003283322A (ja) | インターフェイス回路および半導体装置 | |
| JP3846764B2 (ja) | 同期式半導体メモリ装置及びそのデータ入出力線のプリチャージ方法 | |
| JP2000215663A (ja) | 同期式半導体記憶装置 | |
| JP4220621B2 (ja) | 半導体集積回路 | |
| JPH08204161A (ja) | 半導体メモリ装置 | |
| US6310825B1 (en) | Data writing method for semiconductor memory device | |
| US9412424B2 (en) | Noise tolerant sense circuit | |
| USRE36532E (en) | Synchronous semiconductor memory device having an auto-precharge function | |
| US6385108B2 (en) | Voltage differential sensing circuit and methods of using same | |
| TWI285312B (en) | Data latch circuit and semiconductor device using the same | |
| CN101071625B (zh) | 在高速低耗能存储器中用以防止噪声干扰的方法及系统 | |
| US6560133B2 (en) | Content addressable memory device with advanced precharge timing | |
| JPH0831180A (ja) | 半導体記憶装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |