JP3724654B2 - 半導体集積回路装置 - Google Patents

半導体集積回路装置 Download PDF

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Publication number
JP3724654B2
JP3724654B2 JP19422995A JP19422995A JP3724654B2 JP 3724654 B2 JP3724654 B2 JP 3724654B2 JP 19422995 A JP19422995 A JP 19422995A JP 19422995 A JP19422995 A JP 19422995A JP 3724654 B2 JP3724654 B2 JP 3724654B2
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JP
Japan
Prior art keywords
signal
circuit
input
mosfet
node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP19422995A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0927192A (ja
Inventor
敦子 門馬
美紀 松本
貫時 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP19422995A priority Critical patent/JP3724654B2/ja
Priority to TW085106605A priority patent/TW322553B/zh
Priority to US08/674,917 priority patent/US5801554A/en
Priority to KR1019960027010A priority patent/KR100398165B1/ko
Publication of JPH0927192A publication Critical patent/JPH0927192A/ja
Application granted granted Critical
Publication of JP3724654B2 publication Critical patent/JP3724654B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4082—Address Buffers; level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Logic Circuits (AREA)
JP19422995A 1995-07-06 1995-07-06 半導体集積回路装置 Expired - Lifetime JP3724654B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP19422995A JP3724654B2 (ja) 1995-07-06 1995-07-06 半導体集積回路装置
TW085106605A TW322553B (https=) 1995-07-06 1996-06-03
US08/674,917 US5801554A (en) 1995-07-06 1996-07-03 Semiconductor Integrated circuit device for handling low amplitude signals
KR1019960027010A KR100398165B1 (ko) 1995-07-06 1996-07-04 반도체집적회로장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19422995A JP3724654B2 (ja) 1995-07-06 1995-07-06 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPH0927192A JPH0927192A (ja) 1997-01-28
JP3724654B2 true JP3724654B2 (ja) 2005-12-07

Family

ID=16321116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19422995A Expired - Lifetime JP3724654B2 (ja) 1995-07-06 1995-07-06 半導体集積回路装置

Country Status (4)

Country Link
US (1) US5801554A (https=)
JP (1) JP3724654B2 (https=)
KR (1) KR100398165B1 (https=)
TW (1) TW322553B (https=)

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KR0158762B1 (ko) * 1994-02-17 1998-12-01 세키자와 다다시 반도체 장치
JP4042069B2 (ja) * 1996-12-26 2008-02-06 聯華電子股▲分▼有限公司 積分入力型入力回路およびそのテスト方法
KR100265591B1 (ko) * 1997-05-19 2000-11-01 김영환 클럭입력버퍼를분리시킨반도체메모리장치
US5912567A (en) * 1997-10-22 1999-06-15 Sun Microsystems, Inc. Dual differential comparator with weak equalization and narrow metastability region
US8598332B1 (en) * 1998-04-08 2013-12-03 Bayer Cropscience N.V. Methods and means for obtaining modified phenotypes
KR100272167B1 (ko) * 1998-07-13 2000-11-15 윤종용 동기식 반도체 메모리 장치의 기준 신호 발생 회로
JP3725715B2 (ja) 1998-11-27 2005-12-14 株式会社東芝 クロック同期システム
US6218863B1 (en) 1999-04-12 2001-04-17 Intel Corporation Dual mode input/output interface circuit
US6552716B1 (en) * 1999-05-05 2003-04-22 Logitech Europe, S.A. Transmission of differential optical detector signal over a single line
JP4216415B2 (ja) 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
JP4263818B2 (ja) 1999-09-20 2009-05-13 富士通マイクロエレクトロニクス株式会社 半導体集積回路
US6392448B1 (en) 2000-02-03 2002-05-21 Teradyne, Inc. Common-mode detection circuit with cross-coupled compensation
US6300804B1 (en) 2000-02-09 2001-10-09 Teradyne, Inc. Differential comparator with dispersion reduction circuitry
JP4704541B2 (ja) * 2000-04-27 2011-06-15 エルピーダメモリ株式会社 半導体集積回路装置
JP4190706B2 (ja) 2000-07-03 2008-12-03 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP2002023710A (ja) * 2000-07-06 2002-01-25 Hitachi Ltd 液晶表示装置
KR100374641B1 (ko) * 2000-11-24 2003-03-04 삼성전자주식회사 스탠바이 모드에서 지연동기 루프회로의 전력소모를감소시키기 위한 제어회로를 구비하는 반도체 메모리장치및 이의 파우워 다운 제어방법
JP2002246891A (ja) * 2001-02-16 2002-08-30 Mitsubishi Electric Corp 入力バッファ回路および半導体装置
DE10108820A1 (de) * 2001-02-23 2002-09-12 Infineon Technologies Ag Verfahren zum Betrieb eines integrierten Speichers
JP4726334B2 (ja) * 2001-06-13 2011-07-20 ルネサスエレクトロニクス株式会社 半導体装置
US6977529B2 (en) * 2002-03-01 2005-12-20 Ics Technologies, Inc. Differential clock signal detection circuit
JP3667700B2 (ja) 2002-03-06 2005-07-06 エルピーダメモリ株式会社 入力バッファ回路及び半導体記憶装置
US6798711B2 (en) * 2002-03-19 2004-09-28 Micron Technology, Inc. Memory with address management
US7155630B2 (en) * 2002-06-25 2006-12-26 Micron Technology, Inc. Method and unit for selectively enabling an input buffer based on an indication of a clock transition
KR100528789B1 (ko) * 2003-08-01 2005-11-15 주식회사 하이닉스반도체 셀프 리프래쉬 모드 진입을 위한 클럭 인에이블 버퍼
US7942901B2 (en) * 2006-04-24 2011-05-17 Warsaw Orthopedic, Inc. Connector apparatus
KR100801032B1 (ko) * 2006-11-15 2008-02-04 삼성전자주식회사 비휘발성 반도체 메모리 장치의 입력회로 및 비휘발성반도체 메모리 장치의 데이터 입력방법
JP2009020953A (ja) * 2007-07-11 2009-01-29 Elpida Memory Inc 同期式半導体装置及びこれを有するデータ処理システム
JP5600235B2 (ja) * 2007-10-11 2014-10-01 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置、およびアドレスラッチの高速化方法
KR102393425B1 (ko) * 2015-10-20 2022-05-03 에스케이하이닉스 주식회사 반도체장치 및 반도체시스템
KR102312446B1 (ko) * 2017-09-19 2021-10-15 에스케이하이닉스 주식회사 반도체장치
US12380047B2 (en) * 2023-07-14 2025-08-05 Qualcomm Incorporated Expanded data link width for main band chip module connection in alternate modes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4288706A (en) * 1978-10-20 1981-09-08 Texas Instruments Incorporated Noise immunity in input buffer circuit for semiconductor memory
JPS628614A (ja) * 1985-07-05 1987-01-16 Nec Corp 入力インバ−タ回路
US5019729A (en) * 1988-07-27 1991-05-28 Kabushiki Kaisha Toshiba TTL to CMOS buffer circuit
JPH04297119A (ja) * 1990-09-28 1992-10-21 Toshiba Corp 半導体集積回路
JP2523998B2 (ja) * 1991-01-31 1996-08-14 株式会社東芝 コンパレ―タ
KR930009702B1 (ko) * 1991-04-17 1993-10-08 삼성전자 주식회사 외부 바이어스를 이용한 광대역 선형 이득 조절증폭기

Also Published As

Publication number Publication date
JPH0927192A (ja) 1997-01-28
KR970008609A (ko) 1997-02-24
US5801554A (en) 1998-09-01
KR100398165B1 (ko) 2004-07-14
TW322553B (https=) 1997-12-11

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