TW255059B - Synchronous memory having parallel output data paths - Google Patents

Synchronous memory having parallel output data paths

Info

Publication number
TW255059B
TW255059B TW083111639A TW83111639A TW255059B TW 255059 B TW255059 B TW 255059B TW 083111639 A TW083111639 A TW 083111639A TW 83111639 A TW83111639 A TW 83111639A TW 255059 B TW255059 B TW 255059B
Authority
TW
Taiwan
Prior art keywords
data
parallel
output
path
output data
Prior art date
Application number
TW083111639A
Other languages
English (en)
Inventor
T Flannagan Stephen
W Jones Kenneth
Kung Roger
Chang Ray
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of TW255059B publication Critical patent/TW255059B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Static Random-Access Memory (AREA)
  • Pulse Circuits (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
TW083111639A 1994-03-08 1994-12-13 Synchronous memory having parallel output data paths TW255059B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/207,513 US5402389A (en) 1994-03-08 1994-03-08 Synchronous memory having parallel output data paths

Publications (1)

Publication Number Publication Date
TW255059B true TW255059B (en) 1995-08-21

Family

ID=22770901

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083111639A TW255059B (en) 1994-03-08 1994-12-13 Synchronous memory having parallel output data paths

Country Status (6)

Country Link
US (1) US5402389A (zh)
EP (1) EP0671744B1 (zh)
JP (1) JPH07262780A (zh)
KR (1) KR100341944B1 (zh)
DE (1) DE69528916T2 (zh)
TW (1) TW255059B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7586797B2 (en) 2005-06-10 2009-09-08 Hynix Semiconductor Inc. Data output circuit of synchronous memory device

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Cited By (1)

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Publication number Priority date Publication date Assignee Title
US7586797B2 (en) 2005-06-10 2009-09-08 Hynix Semiconductor Inc. Data output circuit of synchronous memory device

Also Published As

Publication number Publication date
KR950034253A (ko) 1995-12-26
DE69528916T2 (de) 2003-05-28
EP0671744B1 (en) 2002-11-27
EP0671744A2 (en) 1995-09-13
EP0671744A3 (en) 1998-11-18
KR100341944B1 (ko) 2002-11-22
JPH07262780A (ja) 1995-10-13
US5402389A (en) 1995-03-28
DE69528916D1 (de) 2003-01-09

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