DE69528916D1 - Synchroner Speicher mit parallelen Ausgangsdatenwegen - Google Patents
Synchroner Speicher mit parallelen AusgangsdatenwegenInfo
- Publication number
- DE69528916D1 DE69528916D1 DE69528916T DE69528916T DE69528916D1 DE 69528916 D1 DE69528916 D1 DE 69528916D1 DE 69528916 T DE69528916 T DE 69528916T DE 69528916 T DE69528916 T DE 69528916T DE 69528916 D1 DE69528916 D1 DE 69528916D1
- Authority
- DE
- Germany
- Prior art keywords
- output data
- data paths
- parallel output
- synchronous memory
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/207,513 US5402389A (en) | 1994-03-08 | 1994-03-08 | Synchronous memory having parallel output data paths |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69528916D1 true DE69528916D1 (de) | 2003-01-09 |
DE69528916T2 DE69528916T2 (de) | 2003-05-28 |
Family
ID=22770901
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69528916T Expired - Lifetime DE69528916T2 (de) | 1994-03-08 | 1995-03-06 | Synchroner Speicher mit parallelen Ausgangsdatenwegen |
Country Status (6)
Country | Link |
---|---|
US (1) | US5402389A (de) |
EP (1) | EP0671744B1 (de) |
JP (1) | JPH07262780A (de) |
KR (1) | KR100341944B1 (de) |
DE (1) | DE69528916T2 (de) |
TW (1) | TW255059B (de) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0180578B1 (ko) * | 1994-06-07 | 1999-05-15 | 모리시다 요이치 | 데이터처리장치 |
US5546354A (en) * | 1994-07-01 | 1996-08-13 | Digital Equipment Corporation | Static random access memory having tunable-self-timed control logic circuits |
JP3184096B2 (ja) * | 1995-08-31 | 2001-07-09 | 株式会社東芝 | 半導体記憶装置 |
JP3351692B2 (ja) * | 1995-09-12 | 2002-12-03 | 株式会社東芝 | シンクロナス半導体メモリ装置 |
US5701275A (en) * | 1996-01-19 | 1997-12-23 | Sgs-Thomson Microelectronics, Inc. | Pipelined chip enable control circuitry and methodology |
JP3768608B2 (ja) * | 1996-01-30 | 2006-04-19 | 株式会社日立製作所 | 半導体装置および半導体記憶装置 |
JPH09231743A (ja) * | 1996-02-22 | 1997-09-05 | Mitsubishi Electric Corp | 同期型半導体記憶装置および試験方法 |
JP3410922B2 (ja) * | 1996-04-23 | 2003-05-26 | 株式会社東芝 | クロック制御回路 |
US5784705A (en) * | 1996-07-15 | 1998-07-21 | Mosys, Incorporated | Method and structure for performing pipeline burst accesses in a semiconductor memory |
JPH1050958A (ja) * | 1996-08-05 | 1998-02-20 | Toshiba Corp | 半導体記憶装置、半導体記憶装置のレイアウト方法、半導体記憶装置の動作方法および半導体記憶装置の回路配置パターン |
TW340262B (en) * | 1996-08-13 | 1998-09-11 | Fujitsu Ltd | Semiconductor device, system consisting of semiconductor devices and digital delay circuit |
US5901086A (en) * | 1996-12-26 | 1999-05-04 | Motorola, Inc. | Pipelined fast-access floating gate memory architecture and method of operation |
JPH10208470A (ja) * | 1997-01-17 | 1998-08-07 | Nec Corp | 同期型半導体記憶装置 |
US6912680B1 (en) | 1997-02-11 | 2005-06-28 | Micron Technology, Inc. | Memory system with dynamic timing correction |
US5940608A (en) | 1997-02-11 | 1999-08-17 | Micron Technology, Inc. | Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal |
US5946244A (en) * | 1997-03-05 | 1999-08-31 | Micron Technology, Inc. | Delay-locked loop with binary-coupled capacitor |
US5892777A (en) * | 1997-05-05 | 1999-04-06 | Motorola, Inc. | Apparatus and method for observing the mode of a memory device |
US6173432B1 (en) * | 1997-06-20 | 2001-01-09 | Micron Technology, Inc. | Method and apparatus for generating a sequence of clock signals |
US5995424A (en) * | 1997-07-16 | 1999-11-30 | Tanisys Technology, Inc. | Synchronous memory test system |
US6182253B1 (en) * | 1997-07-16 | 2001-01-30 | Tanisys Technology, Inc. | Method and system for automatic synchronous memory identification |
US5812472A (en) * | 1997-07-16 | 1998-09-22 | Tanisys Technology, Inc. | Nested loop method of identifying synchronous memories |
KR100257865B1 (ko) * | 1997-09-04 | 2000-06-01 | 윤종용 | 데이터 입/출력 제어 회로를 구비한 동기형 메모리장치 |
US6101197A (en) | 1997-09-18 | 2000-08-08 | Micron Technology, Inc. | Method and apparatus for adjusting the timing of signals over fine and coarse ranges |
KR100252054B1 (ko) * | 1997-12-04 | 2000-04-15 | 윤종용 | 웨이브 파이프라이닝 제어구조를 가지는 동기식 반도체 메모리장치 및 데이터 출력방법 |
KR100265599B1 (ko) * | 1997-12-31 | 2000-10-02 | 김영환 | 데이터 윈도우 제어장치 및 그 방법 |
JP3789222B2 (ja) * | 1998-01-16 | 2006-06-21 | 富士通株式会社 | Dll回路及びそれを内蔵するメモリデバイス |
US6433607B2 (en) | 1998-01-21 | 2002-08-13 | Fujitsu Limited | Input circuit and semiconductor integrated circuit having the input circuit |
US6269451B1 (en) | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US5923615A (en) * | 1998-04-17 | 1999-07-13 | Motorlola | Synchronous pipelined burst memory and method for operating same |
US6067649A (en) * | 1998-06-10 | 2000-05-23 | Compaq Computer Corporation | Method and apparatus for a low power self test of a memory subsystem |
US6338127B1 (en) | 1998-08-28 | 2002-01-08 | Micron Technology, Inc. | Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same |
US6349399B1 (en) | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
US6430696B1 (en) | 1998-11-30 | 2002-08-06 | Micron Technology, Inc. | Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same |
US6374360B1 (en) | 1998-12-11 | 2002-04-16 | Micron Technology, Inc. | Method and apparatus for bit-to-bit timing correction of a high speed memory bus |
US6285216B1 (en) * | 1998-12-17 | 2001-09-04 | United Microelectronics Corporation | High speed output enable path and method for an integrated circuit device |
US6470060B1 (en) * | 1999-03-01 | 2002-10-22 | Micron Technology, Inc. | Method and apparatus for generating a phase dependent control signal |
US6064600A (en) | 1999-03-01 | 2000-05-16 | Micron Technology, Inc. | Methods and apparatus for reading memory device register data |
US6956920B1 (en) * | 1999-03-22 | 2005-10-18 | Altera Corporation | Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system |
JP4266436B2 (ja) * | 1999-04-28 | 2009-05-20 | 富士通マイクロエレクトロニクス株式会社 | 半導体記憶装置 |
JP2001023372A (ja) * | 1999-05-06 | 2001-01-26 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
KR100328594B1 (ko) * | 1999-07-12 | 2002-03-14 | 윤종용 | 늦은 라이트 타입 반도체 메모리 장치에서의 바이패스 동작 에러방지 및 사이클 타임구간 개선방법과 그에 따른 멀티플렉서 회로 |
US6516363B1 (en) | 1999-08-06 | 2003-02-04 | Micron Technology, Inc. | Output data path having selectable data rates |
US6694416B1 (en) | 1999-09-02 | 2004-02-17 | Micron Technology, Inc. | Double data rate scheme for data output |
US6421280B1 (en) * | 2000-05-31 | 2002-07-16 | Intel Corporation | Method and circuit for loading data and reading data |
US6801989B2 (en) | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
US6779074B2 (en) * | 2001-07-13 | 2004-08-17 | Micron Technology, Inc. | Memory device having different burst order addressing for read and write operations |
KR100427037B1 (ko) | 2001-09-24 | 2004-04-14 | 주식회사 하이닉스반도체 | 적응적 출력 드라이버를 갖는 반도체 기억장치 |
US7051264B2 (en) * | 2001-11-14 | 2006-05-23 | Monolithic System Technology, Inc. | Error correcting memory and method of operating same |
US6930949B2 (en) * | 2002-08-26 | 2005-08-16 | Micron Technology, Inc. | Power savings in active standby mode |
US7168027B2 (en) | 2003-06-12 | 2007-01-23 | Micron Technology, Inc. | Dynamic synchronization of data capture on an optical or other high speed communications link |
US7234070B2 (en) * | 2003-10-27 | 2007-06-19 | Micron Technology, Inc. | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
US7430140B1 (en) | 2004-09-24 | 2008-09-30 | Cypress Semiconductor Corporation | Method and device for improved data valid window in response to temperature variation |
US7392456B2 (en) * | 2004-11-23 | 2008-06-24 | Mosys, Inc. | Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory |
US7385860B2 (en) * | 2005-06-10 | 2008-06-10 | Hynix Semiconductor Inc. | Data output circuit of synchronous memory device |
US7245552B2 (en) * | 2005-06-22 | 2007-07-17 | Infineon Technologies Ag | Parallel data path architecture |
KR100694978B1 (ko) * | 2006-05-12 | 2007-03-14 | 주식회사 하이닉스반도체 | 데이터 입출력 속도를 증가시키는 구조를 가지는 플래시메모리 장치 및 그 데이터 입출력 동작 방법 |
JP5142868B2 (ja) * | 2008-07-17 | 2013-02-13 | 株式会社東芝 | キャッシュメモリ制御回路及びプロセッサ |
US10170166B1 (en) * | 2017-09-08 | 2019-01-01 | Winbond Electronics Corp. | Data transmission apparatus for memory and data transmission method thereof |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59180871A (ja) * | 1983-03-31 | 1984-10-15 | Fujitsu Ltd | 半導体メモリ装置 |
US5018111A (en) * | 1988-12-27 | 1991-05-21 | Intel Corporation | Timing circuit for memory employing reset function |
JPH0373495A (ja) * | 1989-02-15 | 1991-03-28 | Ricoh Co Ltd | 半導体メモリ装置 |
JP2519580B2 (ja) * | 1990-06-19 | 1996-07-31 | 三菱電機株式会社 | 半導体集積回路 |
US5155703A (en) * | 1990-07-06 | 1992-10-13 | Motorola, Inc. | Bicmos bit line load for a memory with improved reliability |
US5111455A (en) * | 1990-08-24 | 1992-05-05 | Avantek, Inc. | Interleaved time-division multiplexor with phase-compensated frequency doublers |
US5121015A (en) * | 1990-11-14 | 1992-06-09 | Zenith Electronics Corporation | Voltage controlled delay element |
US5105108A (en) * | 1990-11-14 | 1992-04-14 | Zenith Electronics Corporation | Delay circuit with phase locked loop control |
US5223755A (en) * | 1990-12-26 | 1993-06-29 | Xerox Corporation | Extended frequency range variable delay locked loop for clock synchronization |
JP2740097B2 (ja) * | 1992-03-19 | 1998-04-15 | 株式会社東芝 | クロック同期型半導体記憶装置およびそのアクセス方法 |
JPH05274862A (ja) * | 1992-03-24 | 1993-10-22 | Mitsubishi Electric Corp | 半導体メモリ装置 |
US5337285A (en) * | 1993-05-21 | 1994-08-09 | Rambus, Inc. | Method and apparatus for power control in devices |
-
1994
- 1994-03-08 US US08/207,513 patent/US5402389A/en not_active Expired - Lifetime
- 1994-12-13 TW TW083111639A patent/TW255059B/zh not_active IP Right Cessation
-
1995
- 1995-02-24 JP JP7060140A patent/JPH07262780A/ja active Pending
- 1995-02-28 KR KR1019950004342A patent/KR100341944B1/ko active IP Right Grant
- 1995-03-06 DE DE69528916T patent/DE69528916T2/de not_active Expired - Lifetime
- 1995-03-06 EP EP95103141A patent/EP0671744B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
KR100341944B1 (ko) | 2002-11-22 |
US5402389A (en) | 1995-03-28 |
KR950034253A (ko) | 1995-12-26 |
DE69528916T2 (de) | 2003-05-28 |
EP0671744A3 (de) | 1998-11-18 |
JPH07262780A (ja) | 1995-10-13 |
TW255059B (en) | 1995-08-21 |
EP0671744A2 (de) | 1995-09-13 |
EP0671744B1 (de) | 2002-11-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US |