DE69415759D1 - Ausgangschaltung für Speicherschaltung mit mehreren Bits - Google Patents
Ausgangschaltung für Speicherschaltung mit mehreren BitsInfo
- Publication number
- DE69415759D1 DE69415759D1 DE69415759T DE69415759T DE69415759D1 DE 69415759 D1 DE69415759 D1 DE 69415759D1 DE 69415759 T DE69415759 T DE 69415759T DE 69415759 T DE69415759 T DE 69415759T DE 69415759 D1 DE69415759 D1 DE 69415759D1
- Authority
- DE
- Germany
- Prior art keywords
- circuit
- several bits
- output circuit
- memory circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5250272A JP2570984B2 (ja) | 1993-10-06 | 1993-10-06 | 出力回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69415759D1 true DE69415759D1 (de) | 1999-02-18 |
DE69415759T2 DE69415759T2 (de) | 1999-07-29 |
Family
ID=17205433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69415759T Expired - Lifetime DE69415759T2 (de) | 1993-10-06 | 1994-10-05 | Ausgangschaltung für Speicherschaltung mit mehreren Bits |
Country Status (5)
Country | Link |
---|---|
US (1) | US5467054A (de) |
EP (1) | EP0647944B1 (de) |
JP (1) | JP2570984B2 (de) |
KR (1) | KR0135477B1 (de) |
DE (1) | DE69415759T2 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0154157B1 (ko) * | 1994-04-29 | 1998-12-15 | 김주용 | 반도체 소자의 부스트랩 회로 |
EP0821362B1 (de) * | 1996-07-24 | 2004-05-26 | STMicroelectronics S.r.l. | Ausgabestufe für Speicheranlage und für Niederspannungsanwendungen |
US6066977A (en) * | 1998-05-21 | 2000-05-23 | Lattice Semiconductor Corporation | Programmable output voltage levels |
KR20010111787A (ko) * | 2000-06-13 | 2001-12-20 | 유인균 | 프리캐스트 콘크리트 기둥용 거푸집 및 이를 이용한기둥시공방법 |
KR100736396B1 (ko) * | 2006-02-13 | 2007-07-09 | 삼성전자주식회사 | 저전력 소모를 위한 소 신호 수신기 및 이를 구비하는반도체 장치 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57166726A (en) * | 1981-04-06 | 1982-10-14 | Nec Corp | Output circuit for boosted signal |
JPS594223A (ja) * | 1982-06-30 | 1984-01-11 | Fujitsu Ltd | クロツク発生回路 |
US4698789A (en) * | 1984-11-30 | 1987-10-06 | Kabushiki Kaisha Toshiba | MOS semiconductor device |
JP2541317B2 (ja) * | 1988-11-25 | 1996-10-09 | 三菱電機株式会社 | 半導体装置のための出力回路 |
JPH0812754B2 (ja) * | 1990-08-20 | 1996-02-07 | 富士通株式会社 | 昇圧回路 |
US5323067A (en) * | 1993-04-14 | 1994-06-21 | National Semiconductor Corporation | Self-disabling power-up detection circuit |
-
1993
- 1993-10-06 JP JP5250272A patent/JP2570984B2/ja not_active Expired - Lifetime
-
1994
- 1994-10-05 US US08/318,087 patent/US5467054A/en not_active Expired - Lifetime
- 1994-10-05 DE DE69415759T patent/DE69415759T2/de not_active Expired - Lifetime
- 1994-10-05 EP EP94115671A patent/EP0647944B1/de not_active Expired - Lifetime
- 1994-10-06 KR KR1019940025524A patent/KR0135477B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
US5467054A (en) | 1995-11-14 |
JP2570984B2 (ja) | 1997-01-16 |
KR950012459A (ko) | 1995-05-16 |
JPH07106933A (ja) | 1995-04-21 |
KR0135477B1 (ko) | 1998-04-25 |
DE69415759T2 (de) | 1999-07-29 |
EP0647944A2 (de) | 1995-04-12 |
EP0647944B1 (de) | 1999-01-07 |
EP0647944A3 (de) | 1995-08-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC CORP., TOKIO/TOKYO, JP Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: ELPIDA MEMORY, INC., TOKYO, JP |