DE69018105D1 - Statische Speicherschaltung mit verbesserter Bitleitungs-Vorladeschaltung. - Google Patents

Statische Speicherschaltung mit verbesserter Bitleitungs-Vorladeschaltung.

Info

Publication number
DE69018105D1
DE69018105D1 DE69018105T DE69018105T DE69018105D1 DE 69018105 D1 DE69018105 D1 DE 69018105D1 DE 69018105 T DE69018105 T DE 69018105T DE 69018105 T DE69018105 T DE 69018105T DE 69018105 D1 DE69018105 D1 DE 69018105D1
Authority
DE
Germany
Prior art keywords
circuit
bit line
static memory
line precharge
improved bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69018105T
Other languages
English (en)
Other versions
DE69018105T2 (de
Inventor
Takayuki Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69018105D1 publication Critical patent/DE69018105D1/de
Publication of DE69018105T2 publication Critical patent/DE69018105T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)
DE1990618105 1989-01-25 1990-01-25 Statische Speicherschaltung mit verbesserter Bitleitungs-Vorladeschaltung. Expired - Lifetime DE69018105T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1016773A JPH02198097A (ja) 1989-01-25 1989-01-25 半導体スタチックメモリ

Publications (2)

Publication Number Publication Date
DE69018105D1 true DE69018105D1 (de) 1995-05-04
DE69018105T2 DE69018105T2 (de) 1995-11-23

Family

ID=11925528

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1990618105 Expired - Lifetime DE69018105T2 (de) 1989-01-25 1990-01-25 Statische Speicherschaltung mit verbesserter Bitleitungs-Vorladeschaltung.

Country Status (3)

Country Link
EP (1) EP0380091B1 (de)
JP (1) JPH02198097A (de)
DE (1) DE69018105T2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02252194A (ja) * 1989-03-25 1990-10-09 Sony Corp 半導体メモリ装置
US5036492A (en) * 1990-02-15 1991-07-30 Advanced Micro Devices, Inc. CMOS precharge and equalization circuit

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132492A (ja) * 1982-12-22 1984-07-30 Fujitsu Ltd 半導体記憶装置
JPS59178685A (ja) * 1983-03-30 1984-10-09 Toshiba Corp 半導体記憶回路
US4639898A (en) * 1984-12-21 1987-01-27 Rca Corporation Bit-line pull-up circuit
US4774691A (en) * 1985-11-13 1988-09-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
JPS63144488A (ja) * 1986-12-06 1988-06-16 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
DE69018105T2 (de) 1995-11-23
JPH02198097A (ja) 1990-08-06
EP0380091A1 (de) 1990-08-01
EP0380091B1 (de) 1995-03-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP