DE69427929T2 - Halbleiterspeicher mit eingebautem parallelen Bitprüfmodus - Google Patents

Halbleiterspeicher mit eingebautem parallelen Bitprüfmodus

Info

Publication number
DE69427929T2
DE69427929T2 DE69427929T DE69427929T DE69427929T2 DE 69427929 T2 DE69427929 T2 DE 69427929T2 DE 69427929 T DE69427929 T DE 69427929T DE 69427929 T DE69427929 T DE 69427929T DE 69427929 T2 DE69427929 T2 DE 69427929T2
Authority
DE
Germany
Prior art keywords
built
semiconductor memory
check mode
parallel bit
bit check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69427929T
Other languages
English (en)
Other versions
DE69427929D1 (de
Inventor
Takashi Ohsawa
Shuso Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69427929D1 publication Critical patent/DE69427929D1/de
Application granted granted Critical
Publication of DE69427929T2 publication Critical patent/DE69427929T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/40—Response verification devices using compression techniques
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
DE69427929T 1993-03-12 1994-01-03 Halbleiterspeicher mit eingebautem parallelen Bitprüfmodus Expired - Fee Related DE69427929T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05171393A JP3293935B2 (ja) 1993-03-12 1993-03-12 並列ビットテストモード内蔵半導体メモリ

Publications (2)

Publication Number Publication Date
DE69427929D1 DE69427929D1 (de) 2001-09-20
DE69427929T2 true DE69427929T2 (de) 2002-04-04

Family

ID=12894541

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69427929T Expired - Fee Related DE69427929T2 (de) 1993-03-12 1994-01-03 Halbleiterspeicher mit eingebautem parallelen Bitprüfmodus

Country Status (5)

Country Link
US (1) US5809225A (de)
EP (2) EP0615251B1 (de)
JP (1) JP3293935B2 (de)
KR (1) KR960016805B1 (de)
DE (1) DE69427929T2 (de)

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DE69505806T2 (de) * 1994-04-29 1999-05-12 Texas Instruments Inc Verfahren und vorrichtung zur prüfung eines speichers mit einer parallelen block-schreib-operation
DE19607724A1 (de) * 1996-02-29 1997-09-04 Siemens Ag Schaltungsanordnung für einen programmierbaren nichtflüchtigen Speicher
US5781486A (en) * 1996-04-16 1998-07-14 Micron Technology Corporation Apparatus for testing redundant elements in a packaged semiconductor memory device
US5706292A (en) 1996-04-25 1998-01-06 Micron Technology, Inc. Layout for a semiconductor memory device having redundant elements
US5734617A (en) * 1996-08-01 1998-03-31 Micron Technology Corporation Shared pull-up and selection circuitry for programmable cells such as antifuse cells
JP3313591B2 (ja) * 1996-10-02 2002-08-12 株式会社東芝 半導体装置、半導体装置の検査方法及び半導体装置の検査装置
JPH10177496A (ja) * 1996-12-13 1998-06-30 Hitachi Ltd エラー検出機能を有する論理回路およびエラー検出機能を有する論理回路を備えるプロセッサ
US6104209A (en) 1998-08-27 2000-08-15 Micron Technology, Inc. Low skew differential receiver with disable feature
KR100269319B1 (ko) * 1997-12-29 2000-10-16 윤종용 동시칼럼선택라인활성화회로를구비하는반도체메모리장치및칼럼선택라인제어방법
US6212482B1 (en) 1998-03-06 2001-04-03 Micron Technology, Inc. Circuit and method for specifying performance parameters in integrated circuits
KR100322525B1 (ko) * 1998-03-23 2002-06-22 윤종용 출력드라이버를공유하는병렬비트테스트회로및이를이용한병렬비트테스트방법
US6452845B1 (en) 1999-01-07 2002-09-17 Micron Technology, Inc. Apparatus for testing redundant elements in a packaged semiconductor memory device
KR100520217B1 (ko) * 1999-02-03 2005-10-12 삼성전자주식회사 패러럴 비트 테스트 기능을 갖는 반도체 메모리 장치
US6357027B1 (en) * 1999-05-17 2002-03-12 Infineon Technologies Ag On chip data comparator with variable data and compare result compression
KR100402103B1 (ko) * 2001-09-20 2003-10-17 주식회사 하이닉스반도체 웨이퍼 번-인 테스트 모드 및 웨이퍼 테스트 모드 회로
US6915467B2 (en) * 2001-12-11 2005-07-05 International Business Machines Corporation System and method for testing a column redundancy of an integrated circuit memory
US6700142B1 (en) 2001-12-31 2004-03-02 Hyperchip Inc. Semiconductor wafer on which is fabricated an integrated circuit including an array of discrete functional modules
US20030212935A1 (en) * 2002-05-09 2003-11-13 Roark Rodney W. Circuit and method for accelerating the test time of a serial access memory device
JP2004079072A (ja) * 2002-08-16 2004-03-11 Oki Electric Ind Co Ltd 半導体記憶装置のテスト方法及び半導体記憶装置
US7003704B2 (en) * 2002-11-12 2006-02-21 International Business Machines Corporation Two-dimensional redundancy calculation
KR100464436B1 (ko) * 2002-11-20 2004-12-31 삼성전자주식회사 병렬비트 테스트시 데이터 입출력 포맷을 변환하는 회로및 방법
KR100541048B1 (ko) * 2003-06-16 2006-01-11 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 테스트 방법
KR100535251B1 (ko) * 2004-06-12 2005-12-08 삼성전자주식회사 내부 데이터 확인이 가능한 반도체 메모리 장치 내부의병렬 비트 테스트 회로 및 이를 이용한 병렬 비트 테스트방법.
US7373573B2 (en) * 2005-06-06 2008-05-13 International Business Machines Corporation Apparatus and method for using a single bank of eFuses to successively store testing data from multiple stages of testing
US20070109888A1 (en) * 2005-11-14 2007-05-17 Ronald Baker Integrated circuit with test circuit
KR101468026B1 (ko) * 2007-05-14 2014-12-02 삼성전자주식회사 메모리 셀 프로그래밍 방법 및 반도체 장치
KR101929983B1 (ko) 2012-07-18 2018-12-17 삼성전자주식회사 저항성 메모리 셀을 갖는 반도체 메모리 장치 및 그 테스트 방법
US10522206B2 (en) * 2017-04-06 2019-12-31 SK Hynix Inc. Semiconductor device and system
KR20220048735A (ko) 2020-10-13 2022-04-20 삼성전자주식회사 테스트 시간을 줄이는 메모리 장치의 테스트 방법, 메모리 빌트-인 셀프 테스트(mbist) 회로 및 메모리 장치

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US4611299A (en) * 1982-02-22 1986-09-09 Hitachi, Ltd. Monolithic storage device
JPS60115099A (ja) * 1983-11-25 1985-06-21 Fujitsu Ltd 半導体記憶装置
JPS62293598A (ja) * 1986-06-12 1987-12-21 Toshiba Corp 半導体記憶装置
EP0257987B1 (de) * 1986-08-22 1991-11-06 Fujitsu Limited Halbleiter-Speicheranordnung
EP0264893B1 (de) * 1986-10-20 1995-01-18 Nippon Telegraph And Telephone Corporation Halbleiterspeicher
US4954992A (en) * 1987-12-24 1990-09-04 Mitsubishi Denki Kabushiki Kaisha Random access memory having separate read out and write in bus lines for reduced access time and operating method therefor
GB2222461B (en) * 1988-08-30 1993-05-19 Mitsubishi Electric Corp On chip testing of semiconductor memory devices
KR920001082B1 (ko) * 1989-06-13 1992-02-01 삼성전자 주식회사 반도체 메모리장치에 있어서 메모리 테스트용 멀티바이트 광역 병렬 라이트회로
US5264743A (en) * 1989-12-08 1993-11-23 Hitachi, Ltd. Semiconductor memory operating with low supply voltage
JP3112019B2 (ja) * 1989-12-08 2000-11-27 株式会社日立製作所 半導体装置
US5301155A (en) * 1990-03-20 1994-04-05 Mitsubishi Denki Kabushiki Kaisha Multiblock semiconduction storage device including simultaneous operation of a plurality of block defect determination circuits
ATE104465T1 (de) * 1990-05-10 1994-04-15 Siemens Ag Integrierter halbleiterspeicher mit paralleltestmoeglichkeit und redundanzverfahren.
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JPH04362592A (ja) * 1991-06-08 1992-12-15 Hitachi Ltd 半導体記憶装置
JP2812004B2 (ja) * 1991-06-27 1998-10-15 日本電気株式会社 スタティック型ランダムアクセスメモリ装置
KR950001293B1 (ko) * 1992-04-22 1995-02-15 삼성전자주식회사 반도체 메모리칩의 병렬테스트 회로

Also Published As

Publication number Publication date
EP0929077A2 (de) 1999-07-14
EP0615251B1 (de) 2001-08-16
US5809225A (en) 1998-09-15
DE69427929D1 (de) 2001-09-20
EP0929077A3 (de) 2000-06-07
KR940022583A (ko) 1994-10-21
JPH06267295A (ja) 1994-09-22
JP3293935B2 (ja) 2002-06-17
KR960016805B1 (ko) 1996-12-21
EP0615251A2 (de) 1994-09-14
EP0615251A3 (de) 1997-02-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee