DE69905418T2 - Halbleiterspeicheranordnung mit Redundanz - Google Patents

Halbleiterspeicheranordnung mit Redundanz

Info

Publication number
DE69905418T2
DE69905418T2 DE69905418T DE69905418T DE69905418T2 DE 69905418 T2 DE69905418 T2 DE 69905418T2 DE 69905418 T DE69905418 T DE 69905418T DE 69905418 T DE69905418 T DE 69905418T DE 69905418 T2 DE69905418 T2 DE 69905418T2
Authority
DE
Germany
Prior art keywords
redundancy
memory device
semiconductor memory
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69905418T
Other languages
English (en)
Other versions
DE69905418D1 (de
Inventor
Yasuji Koshikawa
Tomoko Nobutoki
Kouji Mine
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69905418D1 publication Critical patent/DE69905418D1/de
Publication of DE69905418T2 publication Critical patent/DE69905418T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/84—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability
    • G11C29/846—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved access time or stability by choosing redundant lines at an output stage
DE69905418T 1998-04-30 1999-04-28 Halbleiterspeicheranordnung mit Redundanz Expired - Lifetime DE69905418T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10121369A JPH11317091A (ja) 1998-04-30 1998-04-30 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69905418D1 DE69905418D1 (de) 2003-03-27
DE69905418T2 true DE69905418T2 (de) 2003-12-24

Family

ID=14809541

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69905418T Expired - Lifetime DE69905418T2 (de) 1998-04-30 1999-04-28 Halbleiterspeicheranordnung mit Redundanz

Country Status (6)

Country Link
US (1) US6122207A (de)
EP (1) EP0953912B1 (de)
JP (1) JPH11317091A (de)
KR (1) KR100334143B1 (de)
DE (1) DE69905418T2 (de)
TW (1) TW420805B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3307360B2 (ja) * 1999-03-10 2002-07-24 日本電気株式会社 半導体集積回路装置
KR100322538B1 (ko) * 1999-07-05 2002-03-18 윤종용 래치 셀을 채용하는 리던던시 회로
US9900734B2 (en) 1999-10-28 2018-02-20 Lightwaves Systems, Inc. Method for routing data packets using an IP address based on geo position
US8085813B2 (en) * 1999-10-28 2011-12-27 Lightwaves Systems, Inc. Method for routing data packets using an IP address based on geo position
US8766773B2 (en) * 2001-03-20 2014-07-01 Lightwaves Systems, Inc. Ultra wideband radio frequency identification system, method, and apparatus
US7545868B2 (en) * 2001-03-20 2009-06-09 Lightwaves Systems, Inc. High bandwidth data transport system
KR100492907B1 (ko) 2003-05-30 2005-06-02 주식회사 하이닉스반도체 글로벌 입출력 스킴을 변경한 메모리 소자
JP2010140579A (ja) * 2008-12-15 2010-06-24 Elpida Memory Inc 半導体記憶装置
JP2011113620A (ja) 2009-11-27 2011-06-09 Elpida Memory Inc 半導体装置及びこれを備えるデータ処理システム
US10509577B2 (en) * 2014-06-05 2019-12-17 Pure Storage, Inc. Reliable storage in a dispersed storage network
KR20160001097A (ko) * 2014-06-26 2016-01-06 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4473895A (en) * 1979-06-15 1984-09-25 Fujitsu Limited Semiconductor memory device
US4471472A (en) * 1982-02-05 1984-09-11 Advanced Micro Devices, Inc. Semiconductor memory utilizing an improved redundant circuitry configuration
JP2629697B2 (ja) * 1987-03-27 1997-07-09 日本電気株式会社 半導体記憶装置
NL8900026A (nl) * 1989-01-06 1990-08-01 Philips Nv Matrixgeheugen, bevattende standaardblokken, standaardsubblokken, een redundant blok, en redundante subblokken, alsmede geintegreerde schakeling bevattende meerdere van zulke matrixgeheugens.
JP2730375B2 (ja) * 1992-01-31 1998-03-25 日本電気株式会社 半導体メモリ
US5257229A (en) * 1992-01-31 1993-10-26 Sgs-Thomson Microelectronics, Inc. Column redundancy architecture for a read/write memory
US5377146A (en) * 1993-07-23 1994-12-27 Alliance Semiconductor Corporation Hierarchical redundancy scheme for high density monolithic memories
US5701270A (en) * 1994-05-09 1997-12-23 Cirrus Logic, Inc. Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
ATE220228T1 (de) * 1995-08-09 2002-07-15 Infineon Technologies Ag Integrierte halbleiter-speichervorrichtung mit redundanzschaltungsanordnung
JP3437689B2 (ja) * 1995-10-12 2003-08-18 株式会社東芝 半導体記憶装置
JP3862330B2 (ja) * 1996-05-22 2006-12-27 富士通株式会社 半導体記憶装置

Also Published As

Publication number Publication date
TW420805B (en) 2001-02-01
KR19990083157A (ko) 1999-11-25
EP0953912A2 (de) 1999-11-03
EP0953912B1 (de) 2003-02-19
KR100334143B1 (ko) 2002-04-25
DE69905418D1 (de) 2003-03-27
US6122207A (en) 2000-09-19
JPH11317091A (ja) 1999-11-16
EP0953912A3 (de) 2000-02-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP