DE69934621D1 - Nichtflüchtige Halbleiterspeicheranordnung - Google Patents

Nichtflüchtige Halbleiterspeicheranordnung

Info

Publication number
DE69934621D1
DE69934621D1 DE69934621T DE69934621T DE69934621D1 DE 69934621 D1 DE69934621 D1 DE 69934621D1 DE 69934621 T DE69934621 T DE 69934621T DE 69934621 T DE69934621 T DE 69934621T DE 69934621 D1 DE69934621 D1 DE 69934621D1
Authority
DE
Germany
Prior art keywords
memory device
semiconductor memory
volatile semiconductor
volatile
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69934621T
Other languages
English (en)
Other versions
DE69934621T2 (de
Inventor
Hidekazu Takata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Application granted granted Critical
Publication of DE69934621D1 publication Critical patent/DE69934621D1/de
Publication of DE69934621T2 publication Critical patent/DE69934621T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE69934621T 1998-03-18 1999-03-16 Nichtflüchtige Halbleiterspeicheranordnung Expired - Fee Related DE69934621T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP6802598A JPH11273362A (ja) 1998-03-18 1998-03-18 不揮発性半導体記憶装置
JP06802598 1998-03-18

Publications (2)

Publication Number Publication Date
DE69934621D1 true DE69934621D1 (de) 2007-02-15
DE69934621T2 DE69934621T2 (de) 2007-10-25

Family

ID=13361871

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69934621T Expired - Fee Related DE69934621T2 (de) 1998-03-18 1999-03-16 Nichtflüchtige Halbleiterspeicheranordnung

Country Status (6)

Country Link
US (1) US6046928A (de)
EP (1) EP0944092B1 (de)
JP (1) JPH11273362A (de)
KR (1) KR100315933B1 (de)
DE (1) DE69934621T2 (de)
TW (1) TW446948B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4019615B2 (ja) 2000-03-10 2007-12-12 富士ゼロックス株式会社 光磁気素子、光磁気ヘッドおよび磁気ディスク装置
US7082046B2 (en) * 2003-02-27 2006-07-25 Fujitsu Limited Semiconductor memory device and method of reading data
US7193880B2 (en) * 2004-06-14 2007-03-20 Texas Instruments Incorporated Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory
US7009864B2 (en) * 2003-12-29 2006-03-07 Texas Instruments Incorporated Zero cancellation scheme to reduce plateline voltage in ferroelectric memory
US7133304B2 (en) * 2004-03-22 2006-11-07 Texas Instruments Incorporated Method and apparatus to reduce storage node disturbance in ferroelectric memory
US6970371B1 (en) * 2004-05-17 2005-11-29 Texas Instruments Incorporated Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages
KR100682366B1 (ko) 2005-02-03 2007-02-15 후지쯔 가부시끼가이샤 반도체 기억 장치 및 데이터 판독 방법
US7463504B2 (en) * 2005-09-15 2008-12-09 Texas Instruments Incorporated Active float for the dummy bit lines in FeRAM
US7561458B2 (en) * 2006-12-26 2009-07-14 Texas Instruments Incorporated Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory
US7920404B2 (en) * 2007-12-31 2011-04-05 Texas Instruments Incorporated Ferroelectric memory devices with partitioned platelines

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873664A (en) * 1987-02-12 1989-10-10 Ramtron Corporation Self restoring ferroelectric memory
US5262982A (en) * 1991-07-18 1993-11-16 National Semiconductor Corporation Nondestructive reading of a ferroelectric capacitor
JP3189540B2 (ja) * 1992-12-02 2001-07-16 松下電器産業株式会社 半導体メモリ装置
US5539279A (en) * 1993-06-23 1996-07-23 Hitachi, Ltd. Ferroelectric memory
JPH08203266A (ja) * 1995-01-27 1996-08-09 Nec Corp 強誘電体メモリ装置
JP3622304B2 (ja) * 1995-12-27 2005-02-23 株式会社日立製作所 半導体記憶装置
JP3196824B2 (ja) * 1997-07-16 2001-08-06 日本電気株式会社 強誘電体メモリ装置

Also Published As

Publication number Publication date
KR100315933B1 (ko) 2001-12-12
TW446948B (en) 2001-07-21
US6046928A (en) 2000-04-04
DE69934621T2 (de) 2007-10-25
JPH11273362A (ja) 1999-10-08
KR19990077765A (ko) 1999-10-25
EP0944092B1 (de) 2007-01-03
EP0944092A3 (de) 2000-12-20
EP0944092A2 (de) 1999-09-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee