DE69810050T2 - Halbleiterspeicheranordnung mit Schieberedundanzschaltungen - Google Patents

Halbleiterspeicheranordnung mit Schieberedundanzschaltungen

Info

Publication number
DE69810050T2
DE69810050T2 DE69810050T DE69810050T DE69810050T2 DE 69810050 T2 DE69810050 T2 DE 69810050T2 DE 69810050 T DE69810050 T DE 69810050T DE 69810050 T DE69810050 T DE 69810050T DE 69810050 T2 DE69810050 T2 DE 69810050T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
redundancy circuits
shift redundancy
shift
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69810050T
Other languages
English (en)
Other versions
DE69810050D1 (de
Inventor
Yoshinori Ueno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69810050D1 publication Critical patent/DE69810050D1/de
Publication of DE69810050T2 publication Critical patent/DE69810050T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
DE69810050T 1997-09-30 1998-09-29 Halbleiterspeicheranordnung mit Schieberedundanzschaltungen Expired - Fee Related DE69810050T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26559197A JP3157753B2 (ja) 1997-09-30 1997-09-30 半導体記憶回路

Publications (2)

Publication Number Publication Date
DE69810050D1 DE69810050D1 (de) 2003-01-23
DE69810050T2 true DE69810050T2 (de) 2003-10-09

Family

ID=17419257

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69810050T Expired - Fee Related DE69810050T2 (de) 1997-09-30 1998-09-29 Halbleiterspeicheranordnung mit Schieberedundanzschaltungen

Country Status (7)

Country Link
US (1) US6021075A (de)
EP (1) EP0905625B1 (de)
JP (1) JP3157753B2 (de)
KR (1) KR100313203B1 (de)
CN (1) CN1135475C (de)
DE (1) DE69810050T2 (de)
TW (1) TW544681B (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6972612B2 (en) * 1999-06-22 2005-12-06 Samsung Electronics Co., Ltd. Semiconductor device with malfunction control circuit and controlling method thereof
US6134159A (en) * 1999-08-24 2000-10-17 Oki Electric Industry Co., Ltd. Semiconductor memory and redundant circuit
KR100376265B1 (ko) * 1999-12-29 2003-03-17 주식회사 하이닉스반도체 모스 구조의 안티퓨즈를 이용한 메모리 리페어 회로
JP2001210093A (ja) * 2000-01-25 2001-08-03 Mitsubishi Electric Corp リペア信号発生回路
US6278651B1 (en) * 2000-06-26 2001-08-21 Infineon Technologies Ag High voltage pump system for programming fuses
US6584022B2 (en) 2000-08-21 2003-06-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device with simultaneous data line selection and shift redundancy selection
KR100481175B1 (ko) * 2002-08-08 2005-04-07 삼성전자주식회사 시프트 리던던시 회로들을 가지는 반도체 메모리 장치
US6690193B1 (en) * 2002-08-26 2004-02-10 Analog Devices, Inc. One-time end-user-programmable fuse array circuit and method
US6819160B2 (en) * 2002-11-13 2004-11-16 International Business Machines Corporation Self-timed and self-tested fuse blow
JP4012474B2 (ja) 2003-02-18 2007-11-21 富士通株式会社 シフト冗長回路、シフト冗長回路の制御方法及び半導体記憶装置
DE10318771B4 (de) * 2003-04-25 2007-12-27 Infineon Technologies Ag Integrierte Speicherschaltung mit einer Redundanzschaltung sowie ein Verfahren zum Ersetzen eines Speicherbereichs
US20050050400A1 (en) * 2003-08-30 2005-03-03 Wuu John J. Shift redundancy encoding for use with digital memories
US7196570B2 (en) * 2004-05-05 2007-03-27 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-time programmable resistance circuit
JP2006331571A (ja) * 2005-05-27 2006-12-07 Matsushita Electric Ind Co Ltd 半導体装置
JP4750598B2 (ja) * 2006-03-28 2011-08-17 Ｏｋｉセミコンダクタ株式会社 冗長救済回路
WO2013002772A1 (en) * 2011-06-28 2013-01-03 Hewlett-Packard Development Company, L.P. Shiftable memory
CN103890856B (zh) 2011-10-27 2017-07-11 慧与发展有限责任合伙企业 支持内存储数据结构的可移位存储器
KR20140065477A (ko) 2011-10-27 2014-05-29 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. 원자적 동작을 지원하는 시프트 가능형 메모리
US9331700B2 (en) 2011-10-28 2016-05-03 Hewlett Packard Enterprise Development Lp Metal-insulator phase transition flip-flop
WO2013115779A1 (en) 2012-01-30 2013-08-08 Hewlett-Packard Development Company, L.P. Word shift static random access memory (ws-sram)
US9542307B2 (en) 2012-03-02 2017-01-10 Hewlett Packard Enterprise Development Lp Shiftable memory defragmentation
US9431074B2 (en) 2012-03-02 2016-08-30 Hewlett Packard Enterprise Development Lp Shiftable memory supporting bimodal storage
EP2873075A4 (de) 2012-07-10 2016-03-23 Hewlett Packard Development Co Statischer direktzugriffsspeicher mit listensortierung
CN105139891B (zh) * 2015-09-11 2023-04-18 四川易冲科技有限公司 一种用于校准模拟集成电路的方法及装置
TWI696078B (zh) * 2017-05-26 2020-06-11 旺宏電子股份有限公司 記憶體裝置及其操作方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB8926004D0 (en) * 1989-11-17 1990-01-10 Inmos Ltd Repairable memory circuit
JP2632076B2 (ja) * 1990-08-02 1997-07-16 三菱電機株式会社 半導体記憶装置
US5260902A (en) * 1991-05-30 1993-11-09 Integrated Device Technology, Inc. Efficient redundancy method for RAM circuit
US5255217A (en) * 1992-01-09 1993-10-19 Hewlett-Packard Company Integrated circuit memory device with a redundant memory block
US5508969A (en) * 1993-01-08 1996-04-16 Integrated Device Technology, Inc. Adjacent row shift redundancy circuit having signal restorer coupled to programmable links

Also Published As

Publication number Publication date
EP0905625A2 (de) 1999-03-31
DE69810050D1 (de) 2003-01-23
JPH11102596A (ja) 1999-04-13
US6021075A (en) 2000-02-01
JP3157753B2 (ja) 2001-04-16
KR100313203B1 (ko) 2001-12-20
EP0905625A3 (de) 1999-08-18
KR19990030262A (ko) 1999-04-26
TW544681B (en) 2003-08-01
EP0905625B1 (de) 2002-12-11
CN1135475C (zh) 2004-01-21
CN1214517A (zh) 1999-04-21

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee