DE69401556D1 - Dynamische Redundanzschaltung für integrierten Speicher - Google Patents

Dynamische Redundanzschaltung für integrierten Speicher

Info

Publication number
DE69401556D1
DE69401556D1 DE69401556T DE69401556T DE69401556D1 DE 69401556 D1 DE69401556 D1 DE 69401556D1 DE 69401556 T DE69401556 T DE 69401556T DE 69401556 T DE69401556 T DE 69401556T DE 69401556 D1 DE69401556 D1 DE 69401556D1
Authority
DE
Germany
Prior art keywords
integrated memory
redundancy circuit
dynamic redundancy
dynamic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69401556T
Other languages
English (en)
Other versions
DE69401556T2 (de
Inventor
Francois Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE69401556D1 publication Critical patent/DE69401556D1/de
Publication of DE69401556T2 publication Critical patent/DE69401556T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications
DE69401556T 1993-09-20 1994-09-20 Dynamische Redundanzschaltung für integrierten Speicher Expired - Fee Related DE69401556T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9311169A FR2710445B1 (fr) 1993-09-20 1993-09-20 Circuit de redondance dynamique pour mémoire en circuit intégré.

Publications (2)

Publication Number Publication Date
DE69401556D1 true DE69401556D1 (de) 1997-03-06
DE69401556T2 DE69401556T2 (de) 1997-05-22

Family

ID=9451028

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69401556T Expired - Fee Related DE69401556T2 (de) 1993-09-20 1994-09-20 Dynamische Redundanzschaltung für integrierten Speicher

Country Status (5)

Country Link
US (1) US5604702A (de)
EP (1) EP0645714B1 (de)
JP (1) JPH07201196A (de)
DE (1) DE69401556T2 (de)
FR (1) FR2710445B1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2728363A1 (fr) * 1994-12-20 1996-06-21 Sgs Thomson Microelectronics Dispositif de protection de l'acces a des mots memoires
JP2850953B2 (ja) * 1996-07-30 1999-01-27 日本電気株式会社 半導体装置
FR2775114B1 (fr) * 1998-02-19 2000-04-14 Sgs Thomson Microelectronics Memoire programmable non-volatile et procede de programmation d'une telle memoire
US6199177B1 (en) * 1998-08-28 2001-03-06 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6910152B2 (en) * 1998-08-28 2005-06-21 Micron Technology, Inc. Device and method for repairing a semiconductor memory
US6147904A (en) * 1999-02-04 2000-11-14 Tower Semiconductor Ltd. Redundancy method and structure for 2-bit non-volatile memory cells
DE19922920C1 (de) * 1999-05-19 2000-11-16 Siemens Ag Integrierter Speicher mit Redundanzfunktion
US6484271B1 (en) 1999-09-16 2002-11-19 Koninklijke Philips Electronics N.V. Memory redundancy techniques
US6363020B1 (en) * 1999-12-06 2002-03-26 Virage Logic Corp. Architecture with multi-instance redundancy implementation
KR100362702B1 (ko) * 2001-01-15 2002-11-29 삼성전자 주식회사 리던던트 디코더 회로
TW546664B (en) * 2001-01-17 2003-08-11 Toshiba Corp Semiconductor storage device formed to optimize test technique and redundancy technology
DE10128903C2 (de) * 2001-06-15 2003-04-24 Infineon Technologies Ag Schaltungsanordnung zur Speicherung digitaler Daten
FR2836736A1 (fr) * 2002-03-01 2003-09-05 Canal Plus Technologies Carte a puce et procede d'evitement de faille logique sur une telle carte a puce
TW574703B (en) * 2002-09-09 2004-02-01 High Bandwidth Access Taiwan I A memory structure with redundant memory for accessing data sequentially
JP3935139B2 (ja) 2002-11-29 2007-06-20 株式会社東芝 半導体記憶装置
KR100622349B1 (ko) 2004-08-04 2006-09-14 삼성전자주식회사 불량 블록 관리 기능을 가지는 플레시 메모리 장치 및플레시 메모리 장치의 불량 블록 관리 방법.
US7418683B1 (en) * 2005-09-21 2008-08-26 Cadence Design Systems, Inc Constraint assistant for circuit design
JP5002201B2 (ja) * 2006-06-30 2012-08-15 株式会社東芝 メモリシステム
WO2008023297A2 (en) 2006-08-21 2008-02-28 Nxp B.V. Circuit arrangement and method for data processing
US8190982B2 (en) 2006-09-29 2012-05-29 University Of Connecticut Error-tolerant multi-threaded memory systems with reduced error accumulation
KR101369226B1 (ko) * 2007-05-25 2014-03-06 삼성전자주식회사 Ｓｔｂｃ 신호의 복호화 장치 및 그 제어방법

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4051354A (en) * 1975-07-03 1977-09-27 Texas Instruments Incorporated Fault-tolerant cell addressable array
US4376300A (en) * 1981-01-02 1983-03-08 Intel Corporation Memory system employing mostly good memories
JPS58115828A (ja) * 1981-12-29 1983-07-09 Fujitsu Ltd 半導体集積回路
GB2136992A (en) * 1983-03-18 1984-09-26 Georg V Coza Method and System of Ensuring Integrity of Data in an Electronic Memory
JPS6148200A (ja) * 1984-08-14 1986-03-08 Fujitsu Ltd 半導体記憶装置
EP0198935A1 (de) * 1985-04-23 1986-10-29 Deutsche ITT Industries GmbH Elektrisch umprogrammierbarer Halbleiterspeicher mit Redundanz
JP2530610B2 (ja) * 1986-02-27 1996-09-04 富士通株式会社 半導体記憶装置
JP2700640B2 (ja) * 1986-09-24 1998-01-21 日立超エル・エス・アイ・エンジニアリング 株式会社 半導体記憶装置
JPH0283899A (ja) * 1988-09-20 1990-03-23 Fujitsu Ltd 半導体記憶装置
DE69033262T2 (de) * 1989-04-13 2000-02-24 Sandisk Corp EEPROM-Karte mit Austauch von fehlerhaften Speicherzellen und Zwischenspeicher
JP2830308B2 (ja) * 1990-02-26 1998-12-02 日本電気株式会社 情報処理装置

Also Published As

Publication number Publication date
FR2710445A1 (fr) 1995-03-31
EP0645714A1 (de) 1995-03-29
US5604702A (en) 1997-02-18
FR2710445B1 (fr) 1995-11-03
DE69401556T2 (de) 1997-05-22
EP0645714B1 (de) 1997-01-22
JPH07201196A (ja) 1995-08-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee