JPS57146347A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS57146347A
JPS57146347A JP3131281A JP3131281A JPS57146347A JP S57146347 A JPS57146347 A JP S57146347A JP 3131281 A JP3131281 A JP 3131281A JP 3131281 A JP3131281 A JP 3131281A JP S57146347 A JPS57146347 A JP S57146347A
Authority
JP
Japan
Prior art keywords
machine cycle
clocks
confirmed
clock
timing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3131281A
Other languages
Japanese (ja)
Inventor
Yoshinori Fujioka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3131281A priority Critical patent/JPS57146347A/en
Publication of JPS57146347A publication Critical patent/JPS57146347A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To increase a substantial machine cycle with less amount of hardware, by reducing a waiting time through the difference of confirming timing of branch conditions, in a data processor of a microprogramming control system. CONSTITUTION:A timing control circuit 10 controls an operating timing of each device, and three phase fundamental clocks T0, T1 and T2 and a dummy clock TX are outputted. When branching is confirmed for establishment/unestablishment before a point A, one machine cycle is finished with three clocks of T0, T1, and T2 (S type machine cycle 11), and when not confirmed before the pint A but confirmed at a point B, one machine cycle is finished with 4 clocks of T0, T1, T2 and T3 (L type machine cycle 12). The both machine cycles are determined with a value of a conditional branching field 5, and when the circuit 10 takes the L type machine cycle, the clock TX is inserted after the clock T1 to give a delay to the generation of the T2.
JP3131281A 1981-03-06 1981-03-06 Data processing device Pending JPS57146347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3131281A JPS57146347A (en) 1981-03-06 1981-03-06 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3131281A JPS57146347A (en) 1981-03-06 1981-03-06 Data processing device

Publications (1)

Publication Number Publication Date
JPS57146347A true JPS57146347A (en) 1982-09-09

Family

ID=12327765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3131281A Pending JPS57146347A (en) 1981-03-06 1981-03-06 Data processing device

Country Status (1)

Country Link
JP (1) JPS57146347A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6195260B1 (en) 1997-11-27 2001-02-27 Nec Corporation Flexible printed circuit board unit having electronic parts mounted thereon

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6195260B1 (en) 1997-11-27 2001-02-27 Nec Corporation Flexible printed circuit board unit having electronic parts mounted thereon

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