JPS5629730A - Interface control system - Google Patents

Interface control system

Info

Publication number
JPS5629730A
JPS5629730A JP10399379A JP10399379A JPS5629730A JP S5629730 A JPS5629730 A JP S5629730A JP 10399379 A JP10399379 A JP 10399379A JP 10399379 A JP10399379 A JP 10399379A JP S5629730 A JPS5629730 A JP S5629730A
Authority
JP
Japan
Prior art keywords
operand
cycle
hsa11
cpu10
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10399379A
Other languages
Japanese (ja)
Inventor
Kiyoshi Yada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10399379A priority Critical patent/JPS5629730A/en
Publication of JPS5629730A publication Critical patent/JPS5629730A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To eliminate the time loss for the synchronization and thus enhancing the efficiency of data transmission, by providing the timing extending means to actuate it with every cycle during the operation and then performing the synchronization of the clock.
CONSTITUTION: The timing pulse TP extending FF13 is provided. The synchronous process is started between the CPU10 and the high-speed arithmetic unit HSA11 with the transfer of the operand on the instruction word from the CPU10 to the unit HSA11. And in the case of the instruction of multiplication, the 4-byte multiplier and the 4-byte multiplicand are necessary for the operand. Thus the transfer of the operand is carried out with every 4 bytes in twice with the CPU cycle and in 4 times with the HSA cycle each. At the starting time of the operand transfer, the synchronous mode FF12 is set by the SETHSA signal, and then the FF13 which controls the clock extension of the CPU10 is set by the output signal SYCHSA. After this, the clock extension is continued until the arrival of the RSTTPEXT signal from the HSA11. When the synchronization is once obtained, the CPU and the HSA has one cycle and two cycles each hereafter to avoid occurrence of the synchronous loss.
COPYRIGHT: (C)1981,JPO&Japio
JP10399379A 1979-08-17 1979-08-17 Interface control system Pending JPS5629730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10399379A JPS5629730A (en) 1979-08-17 1979-08-17 Interface control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10399379A JPS5629730A (en) 1979-08-17 1979-08-17 Interface control system

Publications (1)

Publication Number Publication Date
JPS5629730A true JPS5629730A (en) 1981-03-25

Family

ID=14368813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10399379A Pending JPS5629730A (en) 1979-08-17 1979-08-17 Interface control system

Country Status (1)

Country Link
JP (1) JPS5629730A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60649U (en) * 1983-06-17 1985-01-07 日本電気株式会社 Multi-CPU system synchronization device
JPH10222243A (en) * 1997-01-22 1998-08-21 Internatl Business Mach Corp <Ibm> System containing processor having free travel clock which is temporarily synchronized with sub-system clock during data transfer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60649U (en) * 1983-06-17 1985-01-07 日本電気株式会社 Multi-CPU system synchronization device
JPH10222243A (en) * 1997-01-22 1998-08-21 Internatl Business Mach Corp <Ibm> System containing processor having free travel clock which is temporarily synchronized with sub-system clock during data transfer

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