JPS5595131A - Information bus controller - Google Patents

Information bus controller

Info

Publication number
JPS5595131A
JPS5595131A JP67679A JP67679A JPS5595131A JP S5595131 A JPS5595131 A JP S5595131A JP 67679 A JP67679 A JP 67679A JP 67679 A JP67679 A JP 67679A JP S5595131 A JPS5595131 A JP S5595131A
Authority
JP
Japan
Prior art keywords
signal
transfer
register
equipment
time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP67679A
Other languages
Japanese (ja)
Other versions
JPS5913762B2 (en
Inventor
Takeshi Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP67679A priority Critical patent/JPS5913762B2/en
Publication of JPS5595131A publication Critical patent/JPS5595131A/en
Publication of JPS5913762B2 publication Critical patent/JPS5913762B2/en
Expired legal-status Critical Current

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  • Bus Control (AREA)

Abstract

PURPOSE: To shorten the selection time by previously selecting an euipment to which a signal is to be transferred next by using a timing signal in transfer during the transfer operation of one equipment and then by outputting a bus use permission signal at the same time as the end of the transfer.
CONSTITUTION: Once requenst signals are generated by equipment AWC, the contents are set to register 5 to perform selection operation 6 and equipment number A is selected and set to register 10 to send selective signal A out from decoder 7. At the timing when signal A has been removed by transfer tag 2, the contents of request signal line 2 is set to register 5. To send a transfer end signal, signal B is sent out immediately since next selective signal B is determined as an input to register 10. The time when signal B is selected is zero because it is done in parallel to the transfer of signal A. Similarly, the selection time for signal C is zero. Even if register 5 would be set at the trailing edge of the transfer tag, a next transfer equipment number is only determined as an input to register 10 until the transfer end signal after the selection time.
COPYRIGHT: (C)1980,JPO&Japio
JP67679A 1979-01-10 1979-01-10 Information bus control device Expired JPS5913762B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP67679A JPS5913762B2 (en) 1979-01-10 1979-01-10 Information bus control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP67679A JPS5913762B2 (en) 1979-01-10 1979-01-10 Information bus control device

Publications (2)

Publication Number Publication Date
JPS5595131A true JPS5595131A (en) 1980-07-19
JPS5913762B2 JPS5913762B2 (en) 1984-03-31

Family

ID=11480341

Family Applications (1)

Application Number Title Priority Date Filing Date
JP67679A Expired JPS5913762B2 (en) 1979-01-10 1979-01-10 Information bus control device

Country Status (1)

Country Link
JP (1) JPS5913762B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPS63231664A (en) * 1987-03-20 1988-09-27 Fujitsu Ltd Input/output control adapter
JPS6478362A (en) * 1982-09-27 1989-03-23 Nixdorf Computer Ag One connection preparation of several data processors for central clock control multi-line system
JPH0219954A (en) * 1988-06-29 1990-01-23 Internatl Business Mach Corp <Ibm> Data communication bus system

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3307814B1 (en) 2015-06-10 2019-07-03 Borealis AG Multimodal copolymer of ethylene and at least two alpha-olefin comonomers and final articles made thereof
KR20200140930A (en) 2016-09-08 2020-12-16 요툰 에이/에스 Coatings
KR20230156177A (en) 2017-07-28 2023-11-13 주고꾸 도료 가부시키가이샤 Low-voc coating composition, anticorrosive coating film, base with coating film, and production method for base with coating film

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478362A (en) * 1982-09-27 1989-03-23 Nixdorf Computer Ag One connection preparation of several data processors for central clock control multi-line system
JPH0472262B2 (en) * 1982-09-27 1992-11-17 Jiimensu Nitsukusudorufu Infuomeeshon Shisutemu Ag
JPS6180352A (en) * 1984-09-27 1986-04-23 Fujitsu Ltd Multiprocessor control system
JPH0210980B2 (en) * 1984-09-27 1990-03-12 Fujitsu Ltd
JPS63231664A (en) * 1987-03-20 1988-09-27 Fujitsu Ltd Input/output control adapter
JPH0219954A (en) * 1988-06-29 1990-01-23 Internatl Business Mach Corp <Ibm> Data communication bus system

Also Published As

Publication number Publication date
JPS5913762B2 (en) 1984-03-31

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