TW202205594A - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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Publication number
TW202205594A
TW202205594A TW110110201A TW110110201A TW202205594A TW 202205594 A TW202205594 A TW 202205594A TW 110110201 A TW110110201 A TW 110110201A TW 110110201 A TW110110201 A TW 110110201A TW 202205594 A TW202205594 A TW 202205594A
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Taiwan
Prior art keywords
bump
semiconductor package
undercut
semiconductor
layer
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TW110110201A
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English (en)
Inventor
秦正起
宋乺智
鄭泰和
千鎭豪
崔朱逸
藤崎純史
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南韓商三星電子股份有限公司
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Publication of TW202205594A publication Critical patent/TW202205594A/zh

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Abstract

本發明提供一種半導體封裝，包含：半導體晶片；重佈層結構，設置於半導體晶片下方；凸塊墊，設置於重佈層結構下方且具有第一寬度的上部結構及小於第一寬度的第二寬度的下部結構；金屬晶種層，沿著上部結構的下表面及下部結構的側表面設置；絕緣層，環繞重佈層結構及凸塊墊；以及凸塊結構，設置於凸塊墊下方。第一底切設置於金屬晶種層的接觸上部結構的一個端部處，且第二底切設置於金屬晶種層的接觸下部結構的另一端部處。

Description

半導體封裝
本揭露內容是關於一種半導體封裝，且更特定言之，是關於一種包含重佈層的半導體封裝。
隨著電子行業的快速發展且為滿足使用者的需求，電子裝置變得更緊湊且多功能。因此，對用於電子裝置中的半導體晶片的小型化及多功能性的需求日益增長。因此需要具有精細間距連接端子的半導體晶片，且需要微型電極墊以在具有有限半導體封裝大小的結構中安裝高容量半導體晶片。因此，需要用於將外部連接端子電連接至包含於半導體封裝中的微型電極墊的重佈層。
本發明概念的實施例提供一種藉由減少由凸塊墊所導致的缺陷而具有改良的可靠性及製造生產率的半導體封裝及其製造方法。
本發明概念的實施例提供一種半導體封裝，所述半導體封裝包含：半導體晶片；重佈層結構，設置於半導體晶片下方；凸塊墊，設置於重佈層結構下方，凸塊墊具有第一寬度的上部結構及小於第一寬度的第二寬度的下部結構；金屬晶種層，沿著上部結構的下表面及下部結構的側表面設置；絕緣層，環繞重佈層結構及凸塊墊；以及凸塊結構，設置於凸塊墊下方。第一底切設置於金屬晶種層的接觸上部結構的一個端部處，且第二底切設置於金屬晶種層的接觸下部結構的另一端部處。
本發明概念的實施例進一步提供一種半導體封裝，所述半導體封裝包含：第一子封裝，包含第一半導體晶片；第二子封裝，設置於第一子封裝上且包含第二半導體晶片；以及封裝間連接結構，將第一子封裝連接至第二子封裝。第一子封裝及第二子封裝中的每一者包含：下部重佈層結構；凸塊墊，設置於下部重佈層結構下方；凸塊墊具有第一寬度的上部結構及小於第一寬度的第二寬度的下部結構；金屬晶種層，沿著上部結構的下表面及下部結構的側表面設置；下部絕緣層，環繞下部重佈層結構及凸塊墊；以及凸塊結構，設置於凸塊墊下方。第一底切設置於金屬晶種層的接觸上部結構的一個端部處，且第二底切設置於金屬晶種層的接觸下部結構的另一端部處。
本發明概念的實施例又另外提供一種半導體封裝，所述半導體封裝包含：凸塊結構；T形凸塊墊，設置於凸塊結構上，T形凸塊結構具有上部結構及下部結構，所述上部結構與所述下部結構之間具有階差；重佈層結構，設置於凸塊墊上且具有多個重佈層線；多個絕緣層，環繞重佈層結構及凸塊墊；金屬晶種層，共形地設置於上部結構的下表面與多個絕緣層的最低絕緣層之間及下部結構的側表面與最低絕緣層之間；以及半導體晶片，設置於重佈層結構上且電連接至凸塊結構。第一底切設置於金屬晶種層的一個端部處，第二底切設置於金屬晶種層的另一端部處，且第一底切與第二底切彼此正交延伸。
本發明概念的實施例亦提供一種半導體封裝，所述半導體封裝包含：重佈層結構，具有第一主表面及與第一主表面相對的第二主表面，重佈層結構包含重佈層線及絕緣層；半導體晶片，在重佈層結構的第一主表面上且連接至重佈層線；凸塊墊，在重佈層結構的第二主表面處，凸塊墊包含掩埋於重佈層結構中且連接至重佈層線的第一結構及自第一結構突出的第二結構，第二結構具有在重佈層結構的第二主表面處自絕緣層暴露的墊表面；以及金屬晶種層，設置於絕緣層與第一結構的底部表面之間及絕緣層與第二結構的側表面之間，金屬晶種層在其相對端部處具有第一底切及第二底切。
在下文中，將參考隨附圖式詳細地描述本發明概念的實施例。
圖1示出根據本發明概念的實施例的半導體封裝的橫截面圖。圖2示出圖1的區AA的放大橫截面圖。圖3示出繪示圖2的凸塊墊的仰視圖。圖4示出圖2的區BB的放大橫截面圖。
一起參考圖1至圖4，半導體封裝10包含：半導體晶片170，設置於半導體晶片170下方的重佈層結構140，設置於重佈層結構140下方的凸塊墊123，沿著凸塊墊123的側表面的一部分設置的金屬晶種層121，環繞重佈層結構140及凸塊墊123的絕緣層130，以及設置於凸塊墊123下方的凸塊結構191。
若半導體晶片170的大小減小或半導體晶片170的輸入/輸出端子的數目增加，則半導體封裝10可無法容納半導體晶片170的主表面內的所有外部連接端子（例如，輸入/輸出端子）。因此，可藉由將重佈層結構140延伸至形成應用於半導體封裝10的模製部件181來使半導體封裝10具有包含外部連接端子的扇出型晶圓級封裝（fan-out wafer level package；FO-WLP）或扇出型面板級封裝（fan-out panel level package；FO-PLP）結構。
另外，在FO-WLP中，根據本發明概念的實施例的半導體封裝10可經由後晶片製造方法實施，其中重佈層結構140首先形成於支撐基板101（參看圖13）上，且半導體晶片170隨後安裝於已形成的重佈層結構140上。然而，為方便理解起見，不管半導體晶片170相對於重佈層結構140的形成次序，將首先如下描述半導體晶片170。
半導體晶片170可包含例如邏輯晶片或記憶體晶片。邏輯晶片可包含例如微處理器、類比元件或數位信號處理器。此外，記憶體晶片可包含例如諸如動態隨機存取記憶體（dynamic random access memory；DRAM）或靜態RAM（static RAM；SRAM）的揮發性記憶體晶片，或諸如相變RAM（phase-change RAM；PRAM）、磁阻式RAM（magnetoresistive RAM；MRAM）、電阻式RAM（resistive RAM；RRAM）或鐵電RAM（ferroelectric RAM；FeRAM）的非揮發性記憶體晶片。在一些實施例中，半導體晶片170可包含高頻寬記憶體晶片。半導體封裝10可包含多個半導體晶片170。
半導體晶片170可理解為包含具有積體電路的半導體裝置。舉例而言，半導體晶片170可包含具有面向彼此的主動表面及非主動表面的半導體基板171。用於實施半導體晶片170的積體電路功能的電路部分可經由半導體製造製程形成於半導體基板171的主動表面上。亦即，諸如導電佈線、設置於其間的層間絕緣膜以及個別單元元件的配線層可形成於半導體基板171上。
此外，半導體晶片170可包含形成於半導體基板171中的電極墊173以將電路部分的功能延伸至外部。電極墊173的外圍部分（例如，側表面）可由形成於半導體基板171的主動表面上的保護層覆蓋，且電極墊173的中心部分可自保護層暴露。保護層可在實體上及化學上保護半導體基板171的主動表面上的半導體裝置。保護層可包含例如諸如氧化矽、氮化矽以及氮氧化矽的無機絕緣材料，或諸如絕緣聚合物的有機絕緣材料或由其組合構成的絕緣材料。
電極墊173可具有例如諸如正方形、六邊形或八邊形的多邊形的形狀，或可為圓形或橢圓形。電極墊173可形成為具有預定大小或大於預定大小以耐受電應力及機械應力。在下文中，其上形成有電極墊173的表面將稱為半導體晶片170的下表面。焊料凸塊175可設置於電極墊173下方。
模製部件181可保護半導體晶片170免受諸如污染及衝擊的外部影響。為了執行此作用，模製部件181可由環氧樹脂模製化合物、樹脂或類似物製成。另外，模製部件181可藉由諸如壓縮模製、層壓或網版印刷的製程形成。在一些實施例中，模製部件181可覆蓋半導體晶片170的側表面且可將半導體晶片170的上表面（亦即，與前述下表面相對的主表面）暴露於外部。模製部件181可構成半導體封裝10的外部形狀，且重佈層結構140可自模製部件181延伸。
上部墊161及環繞上部墊161的上部保護層151可設置於焊料凸塊175下方。上部墊161可位於上部保護層151的開口中。在一些實施例中，上部保護層151可包含無機絕緣材料、有機絕緣材料或由其組合構成的絕緣材料。
重佈層結構140可包含金屬佈線層的單層或多層。舉例而言，重佈層結構140可由銅（Cu）、鎳（Ni）、金（Au）、鉻（Cr）、鈦（Ti）或鈀（Pd）或其合金形成。在一些實施例中，重佈層結構140可藉由電鍍製程形成。
重佈層結構140可包含錐形倒置的梯形通孔及接觸通孔的上表面的重佈層線141至重佈層線144（例如，141、142、143以及144）。重佈層線141至重佈層線144中的每一者可沿著在第一方向（X方向）上及在垂直於第一方向（X方向）的第二方向（Y方向）上形成的平面設置。另外，重佈層線141至重佈層線144可在垂直於第一方向（X方向）及第二方向（Y方向）兩者的第三方向（Z方向）上配置為多個層。通孔的寬度可形成為沿著第三方向（Z方向）隨著遠離半導體晶片170而變窄的形狀。此可為根據其中半導體晶片170隨後安裝於重佈層結構140上的後晶片製造方法的特性。
重佈層結構140可包含由絕緣層130之間的四個層構成的重佈層線141至重佈層144。然而，重佈層結構140可包含比重佈層線141至重佈層線144更多或更少的層。
重佈層線141至重佈層線144可將凸塊墊123電連接至半導體晶片170的電極墊173。舉例而言，焊料凸塊175設置於電極墊173與半導體晶片170的上部墊161之間，使得電極墊173與上部墊161可彼此電連接。第一重佈層線141設置於上部墊161下方，且上部墊161與第一重佈層線141可直接連接至彼此。第二重佈層線142可設置於第一重佈層線141下方，且第一重佈層線141與第二重佈層線142可直接連接至彼此。以相同方式，第三重佈層線143設置於第二重佈層線142下方，且第四重佈層線144設置於第三重佈層線143下方以直接連接至彼此。此處，凸塊墊123設置於第四重佈層線144下方，且第四重佈層線144與凸塊墊123可直接連接至彼此。
另外，絕緣層130可在重佈層結構140周圍包含一或多個絕緣層。絕緣層130可例如由聚合物、苯并環丁烯或樹脂形成，且可由感光性聚醯亞胺形成。因此，絕緣層130可稱為聚合物層。然而，構成絕緣層130的材料不限於此。舉例而言，絕緣層130可由氧化矽或氮化矽製成。
相對於絕緣層130，第一絕緣層131設置於上部保護層151下方，且第一絕緣層131可包含暴露第一重佈層線141的上表面的一部分的開口。第二絕緣層132設置於第一絕緣層131下方，且第二絕緣層132可包含暴露第二重佈層線142的上表面的一部分的開口。類似地，第三絕緣層133可設置於第二絕緣層132下方，第四絕緣層134可設置於第三絕緣層133下方，且第五絕緣層135可設置於第四絕緣層134下方。下部保護層111設置於第五絕緣層135下方，且下部保護層111可包含暴露凸塊墊123的下表面的開口。
凸塊墊123經由重佈層結構140電連接至半導體晶片170的個別單元元件，使得半導體晶片170的電路部分的功能可電連接至凸塊結構191。亦即，凸塊墊123亦可稱為凸塊下金屬（under bump metal；UBM）。在一些實施例中，凸塊墊123可為銅（Cu）墊。此外，凸塊墊123的厚度123H可為約3微米至約15微米，但不限於此。半導體封裝10可包含多個凸塊墊123。
凸塊墊123可包含可接觸重佈層結構140的第四重佈層線144的上部結構123T及接觸凸塊結構191的下部結構123B。凸塊墊123中的上部結構123T的第一寬度W1可大於下部結構123B的第二寬度W2。亦即，凸塊墊123具有T形形狀，且凸塊墊123的側表面可具有階差。在一些實施例中，第一寬度W1的數值可判定為在滿足大於第二寬度W2加上約2微米的數值的數值且滿足小於第二寬度W2的數值的四倍的數值的範圍內。然而，第一寬度W1的數值不限於此。下部（第二）結構123B可表徵為自上部（第一）結構123T延伸或突出。
凸塊墊123的上部結構123T及下部結構123B可具有同一中心軸123C。亦即，上部結構123T的中心可在第三方向（Z方向）上與下部結構123B的中心對準。另外，下部結構123B的下表面的水平高度可與下部保護層111的最低表面的水平高度實質上相同。亦即，下部結構123B的下表面的水平高度與下部保護層111的最低表面的水平高度可實質上共面。在一些實施例中，凸塊墊123的上部結構123T及下部結構123B中的每一者可具有圓柱形形狀。在其他實施例中，凸塊墊123的上部結構123T及下部結構123B中的每一者可具有任何形狀，例如四邊形的柱形狀。
金屬晶種層121可設置於凸塊墊123與下部保護層111之間。具體而言，金屬晶種層121可共形地設置於凸塊墊123的側表面的一部分及下部保護層111的上表面的一部分上。金屬晶種層121可藉由物理氣相沈積製程形成以具有約100埃至約20,000埃的厚度。金屬晶種層121可由例如含有選自鈦（Ti）、鈦鎢（TiW）以及鉻（Cr）或其合金中的至少一者的金屬形成。
金屬晶種層121可充當用於形成凸塊墊123的晶種。亦即，金屬晶種層121提供在藉由電鍍製程形成凸塊墊123時電流可流經的路徑，使得凸塊墊123形成於金屬晶種層121上。在一些實施例中，金屬晶種層121及凸塊墊123可由不同材料製成。舉例而言，金屬晶種層121可由鈦（Ti）形成，且凸塊墊123可由銅（Cu）形成。在此情況下，金屬晶種層121及凸塊墊123可形成界面。
金屬晶種層121可沿著凸塊墊123的上部結構123T的下表面及下部結構123B的側表面設置。第一底切121C1可形成於金屬晶種層121的與上部結構123T接觸的一個端部處，且第二底切121C2可形成於金屬晶種層121的接觸下部結構123B的另一端部處。第一底切121C1可在第一方向（X方向）上（或沿著第一方向）形成，且第二底切121C2可在第三方向（Z方向）上（或沿著第三方向）形成。亦即，第一底切121C1及第二底切121C2可彼此垂直，或換言之相對於彼此正交延伸。此處，第一底切121C1的第一長度C1可長達約2微米，且第二底切121C2的第二長度C2可長達約3微米。然而，在其他實施例中，第一底切及第二底切可具有不同長度。
凸塊結構191可包含焊球或焊料凸塊。在一些實施例中，包含錫（Sn）的無鉛焊料可例如用作構成凸塊結構191的材料。半導體封裝10可經由凸塊結構191連接至諸如印刷電路板（printed circuit board；PCB）的外部裝置。凸塊結構191可經由凸塊墊123電連接至重佈層結構140。
在一些實施例中，凸塊結構191可具有大於下部結構123B的第二寬度W2的第三寬度W3。在此情況下，第一底切121C1可由絕緣層130填充，且第二底切121C2可由凸塊結構191填充。凸塊結構191可設置為接觸下部結構123B的下表面，且可設置為不接觸下部保護層111的下表面。此外，凸塊結構191可經由第二底切121C2接觸下部結構123B的側表面及下部保護層111的側表面。
響應於電子行業的快速發展且為滿足使用者的需求，電子裝置變得更緊湊且多功能。因此，對諸如用於電子裝置中的半導體晶片170的半導體晶片的小型化及多功能化的需求亦日益增大。因此，需要諸如半導體晶片170的半導體晶片具有精細（或縮小的）間距連接端子及微型電極墊173，以將高容量半導體晶片170安裝於具有有限大小的半導體封裝10的結構內。因此，需要用於將凸塊結構191（其為外部連接端子）電連接至包含於半導體封裝10中的具有精細（或較小）大小的電極墊173的重佈層結構140。然而，在近來研發的使用超精細處理製造半導體封裝10期間，存在凸塊結構191由於凸塊墊123與下部保護層111之間的剝離現象而脫落的問題。
在本發明概念的實施例中，可藉由將凸塊墊123形成為具有T形形狀及藉由在凸塊墊123與下部保護層111之間形成金屬晶種層121來減少半導體封裝10中的可在凸塊墊123與下部保護層111之間發生的剝離缺陷。另外，可經由金屬晶種層121的第二底切121C2來增加凸塊墊123及凸塊結構191的接合強度。
因此，根據本發明概念的實施例的半導體封裝10可具有改良的可靠性，且可在降低總體成本的同時提高製造的生產率。
圖5、圖6以及圖7示出根據本發明概念的其他實施例的半導體封裝的一部分的放大橫截面圖。
構成下文中所描述的半導體封裝20、半導體封裝30以及半導體封裝40的組件及構成所述組件的材料的大部分實質上與參考圖1至圖4所描述的組件及材料相同或相似。因此，為方便起見，以下描述將主要集中於半導體封裝20、半導體封裝30以及半導體封裝40與半導體封裝10之間的差異。
參考圖5，半導體封裝20包含如所繪示的附接至凸塊墊123的下表面的凸塊結構291。
包含於半導體封裝20中的凸塊結構291可包含焊球或焊料凸塊。半導體封裝20可經由凸塊結構291連接至諸如PCB的外部裝置。凸塊結構291可經由凸塊墊123電連接至重佈層結構140（參看圖1）。
在一些實施例中，凸塊結構291可具有等於或小於下部結構123B的第二寬度W2的第四寬度W4。在此情況下，第一底切121C1可由絕緣層130填充，且第二底切121C2可保持為空的。凸塊結構291可設置為接觸下部結構123B的下表面，但可設置為不接觸下部保護層111。另外，凸塊結構291可藉由第二底切121C2而與下部結構123B的側表面及下部保護層111的側表面間隔開。
參考圖6，半導體封裝30包含具有如所繪示的為凹圓形的上表面的凸塊墊323。
凸塊墊323可包含接觸重佈層結構140（參看圖1）的上部結構323T及接觸凸塊結構191的下部結構323B。凸塊墊323的上部結構323T的寬度可大於下部結構323B的寬度。亦即，凸塊墊323具有T形形狀，且凸塊墊323的側表面可具有階差。
凸塊墊323的上部結構323T可形成為具有凹面323R。亦即，上部結構323T的上表面的一部分可為凹入的。此可為由形成凸塊墊323的製程產生的特性。
參考圖7，半導體封裝40包含具有如所繪示的為凸圓形的上表面的凸塊墊423。
凸塊墊423可包含接觸重佈層結構140（參看圖1）的上部結構423T及接觸凸塊結構191的下部結構423B。凸塊墊423的上部結構423T的寬度可大於凸塊墊423的下部結構423B的寬度。亦即，凸塊墊423具有T形形狀，且凸塊墊423的側表面可具有階差。
凸塊墊423的上部結構423T可形成為具有凸面423R。亦即，上部結構423T的上表面可為凸起的。此可為由形成凸塊墊423的製程產生的特性。
圖8、圖9、圖10以及圖11示出根據本發明概念的其他實施例的半導體封裝的橫截面圖。
構成下文中所描述的半導體封裝50、半導體封裝60、半導體封裝70以及半導體封裝80的組件及構成所述組件的材料的大部分實質上與參考圖1至圖4所描述的組件及材料相同或相似。因此，為方便起見，以下描述將主要集中於半導體封裝50、半導體封裝60、半導體封裝70以及半導體封裝80與半導體封裝10之間的差異。
參考圖8，半導體封裝50包含形成於半導體晶片170的上表面上的上部重佈層結構540及安裝於上部重佈層結構540上的第二半導體晶片570。
半導體封裝50可包含穿過模製部件181的貫穿電極163。模製部件181覆蓋半導體晶片170及貫穿電極163的側表面，且暴露半導體晶片170及貫穿電極163的上表面。在一些實施例中，在形成模製部件181以覆蓋半導體晶片170及貫穿電極163之後，貫穿電極163的上表面可接地以暴露於外部。在其他實施例中，在形成模製部件181以覆蓋半導體晶片170，且接著經由曝光製程及蝕刻製程在模製部件181中形成貫穿孔之後，形成貫穿電極163以填充貫穿孔。
半導體封裝50可包含被動元件560及第二半導體晶片570。在形成電連接至貫穿電極163的上部重佈層結構540之後，被動元件560及第二半導體晶片570可安裝於上部重佈層結構540上。半導體封裝50可包含多個第二半導體晶片570及多個被動元件。
上部絕緣層530可設置為環繞上部重佈層結構540，且第二模製部件581可設置為環繞被動元件560及第二半導體晶片570。
參考圖9，半導體封裝60包含以子封裝形式安裝於半導體晶片170的上部部分上的第二半導體晶片670。
半導體封裝60包含扇出型面板級封裝（FO-PLP）結構及堆疊封裝（package on package；PoP）結構兩者。亦即，包含半導體晶片170的第一子封裝SP1及包含第二半導體晶片670的第二子封裝SP2藉由封裝間連接結構691連接以組態一個半導體封裝。舉例而言，半導體晶片170可包含控制器半導體晶片，且第二半導體晶片670可包含記憶體半導體晶片。
第一子封裝SP1可包含環繞半導體晶片170的側表面的框架結構160。框架結構160是用於支撐半導體封裝60的組態，且由此，可維持硬度且可確保厚度的均勻性。框架結構160具有上表面及面向上表面的下表面，且形成貫穿區以在其上表面與下表面之間穿透。在貫穿區中，半導體晶片170設置為與框架結構160間隔開，且因此，半導體晶片170的側表面外圍由框架結構160環繞。
框架結構160的材料不受特定限制，只要其可支撐半導體封裝60即可。舉例而言，可使用絕緣材料、具有極佳硬度及導熱性的金屬、玻璃、陶瓷、塑膠或類似物。框架結構160的厚度不受特定限制，且可根據半導體晶片170的厚度來設計。舉例而言，取決於半導體晶片170的類型，框架結構160的厚度可為約100微米至約500微米。框架結構160可具有具備用於大批量生產半導體封裝60的多個貫穿區的較大大小，且可因此使用在製造多個半導體封裝60之後經由鋸切製程單一化個別半導體封裝60的方法來製造。
框架結構160可包含穿透其內部的貫穿電極165及貫穿電極167。貫穿電極165及貫穿電極167可穿透框架結構160的主體。貫穿電極165及貫穿電極167可包含下部貫穿電極167及上部貫穿電極165，但特定數目、間隔、配置類型等不受特別限制，且可根據設計進行充分修改。框架結構160可因此表徵為包含貫穿電極，所述貫穿電極是形成為多級結構的多個配線層。
貫穿電極165及貫穿電極167可電連接至封裝間連接結構691。
第二子封裝SP2可包含：第二半導體晶片670，設置於第二半導體晶片670下方的第二重佈層結構640，設置於第二重佈層結構640下方的第二凸塊墊623，沿著第二凸塊墊623的側表面的一部分設置的第二金屬晶種層621，以及環繞第二重佈層結構640及第二凸塊墊623的第二絕緣層630。另外，第二子封裝SP2可包含底部填充物683以加強第二半導體晶片670與焊球之間的連接，且可包含保護第二半導體晶片670免受諸如污染及衝擊的外部影響的模製部件681。
第二凸塊墊623可與凸塊墊123實質上相同，且第二金屬晶種層621可與金屬晶種層121實質上相同。亦即，在根據本發明概念的實施例的半導體封裝60中，包含於第一子封裝SP1中的特徵亦可應用於第二子封裝SP2。
參考圖10，半導體封裝70包含封裝基板720、設置於封裝基板720上的插入件710以及設置於插入件710上的半導體晶片770。
包含於半導體封裝70中的封裝基板720可為PCB、晶圓基板、陶瓷基板、玻璃基板或類似物。在根據本發明概念的實施例的半導體封裝70中，封裝基板720可為PCB。
外部端子791可設置於封裝基板720的下表面上。半導體封裝70可經由外部端子791電連接至電子產品的模組板或系統板且安裝於所述模組板或所述系統板上。
插入件710可包含重佈層結構140、連接至重佈層結構140的下部部分的凸塊墊123以及連接至重佈層結構140的上部部分的貫穿電極711。
半導體晶片770可安裝於插入件710上。半導體封裝70可包含環繞半導體晶片770的模製部件781及模製部件781上的散熱部件783。另外，半導體封裝70可包含環繞插入件710、模製部件781以及散熱部件783的包封體785。
半導體晶片770可包含第一半導體晶片771及第二半導體晶片772。第一半導體晶片771包含單個邏輯晶片，且可例如實施為微處理器、圖形處理器、信號處理器、網路處理器、晶片組、音訊編碼解碼器、視訊編碼解碼器、應用處理器或系統晶片（system on chip；SoC）。第二半導體晶片772可包含其中多個薄片形成堆疊結構的高頻寬記憶體晶片。在一些實施例中，半導體晶片770可包含任何數目的第一半導體晶片771及第二半導體晶片772。
參考圖11，半導體封裝80包含封裝基板820、設置於封裝基板820上的第一半導體晶片871以及設置於第一半導體晶片871上的多個第二半導體晶片872及第二半導體晶片873。
包含於半導體封裝80中的封裝基板820可為PCB、晶圓基板、陶瓷基板、玻璃基板或類似物。在根據本發明概念的實施例的半導體封裝80中，封裝基板820可為PCB。
外部端子891可設置於封裝基板820的下表面上。半導體封裝80可經由外部端子891電連接至電子產品的模組板或系統板且安裝於所述模組板或所述系統板上。
半導體晶片870可包含第一半導體晶片871以及多個第二半導體晶片872及第二半導體晶片873。第一半導體晶片871可包含重佈層結構140。另外，第一半導體晶片871可包含連接至重佈層結構140的下部部分的凸塊墊123及連接至重佈層結構140的上部部分的貫穿電極861。多個第二半導體晶片872及第二半導體晶片873可安裝於第一半導體晶片871上，且多個第二半導體晶片872及第二半導體晶片873的側表面可由模製部件881環繞。
第一半導體晶片871包含單個邏輯晶片，且可例如實施為微處理器、圖形處理器、信號處理器、網路處理器、晶片組、音訊編碼解碼器、視訊編碼解碼器、應用處理器或系統晶片。多個第二半導體晶片872及第二半導體晶片873可例如包含揮發性記憶體晶片及/或非揮發性記憶體晶片。
圖12示出描述根據本發明概念的實施例的製造半導體封裝的方法的方塊圖。
參考圖12，製造半導體封裝的方法（S10）可包含第一步驟至第九步驟（S110至S190）的製程順序。
根據本發明概念的實施例的製造半導體封裝的方法（S10）可包含：在支撐基板上形成黏著層及下部保護層的第一步驟（S110），在黏著層的上表面及下部保護層的暴露表面上形成預晶種層的第二步驟（S120），在預晶種層上形成凸塊墊的第三步驟（S130），藉由濕式蝕刻預晶種層來形成金屬晶種層的第四步驟（S140），在凸塊墊上形成重佈層結構的第五步驟（S150），安裝半導體晶片及形成環繞半導體晶片的模製部件的第六步驟（S160），附接載體基板及移除支撐基板的第七步驟（S170），藉由濕式蝕刻移除黏著層的第八步驟（S180），以及在凸塊墊下方形成凸塊結構及移除載體基板的第九步驟（S190）。
在一些實施例中，圖12中所繪示的步驟的特定製程次序可以不同於所描述的次序來執行。舉例而言，在適當的情況下，順序描述的兩個製程可實質上同時執行，或可以與所描述次序相反的次序執行。
將參考圖13至圖29詳細地描述第一步驟至第九步驟（S110至S190）中的每一者的技術特徵。
圖13至圖29示出根據製程順序描述根據本發明概念的實施例的製造半導體封裝的方法的橫截面圖。
參考圖13，在支撐基板101上依序形成黏著層AL及預保護層111P。
在形成半導體封裝10（參看圖1）中，支撐基板101可用於支撐各種材料層，且隨後可自半導體封裝10（參看圖1）移除。
支撐基板101可支撐絕緣層及導電層，且可由對於烘烤製程及蝕刻製程具有穩定性的材料製成。在一些實施例中，當隨後將藉由雷射切除來分離及移除支撐基板101時，支撐基板101可為半透明基板。在其他實施例中，當隨後將藉由加熱來分離及移除支撐基板101時，支撐基板101可為耐熱基板。
在一些實施例中，支撐基板101可為玻璃基板。在其他實施例中，支撐基板101可由諸如聚醯亞胺、聚醚醚酮、聚醚碸、聚苯硫醚或類似物的耐熱有機聚合物材料製成，但不限於此材料。
可在支撐基板101上設置黏著層AL。黏著層AL可允許支撐基板101與半導體封裝10（參看圖1）分離。黏著層AL可包含金屬材料層。黏著層AL可例如由包含選自鈦（Ti）、鈦鎢（TiW）以及鉻（Cr）或其合金中的至少一者的金屬形成。
隨後，可在黏著層AL上形成預保護層111P。預保護層111P可防止歸因於在後續製程中添加的各種材料層與黏著層AL之間的材料擴散的污染。此外，預保護層111P可防止在後續製程中添加的各種材料層在支撐基板101分離時受影響。預保護層111P可包含諸如氧化矽、氮化矽或可光成像介電質（photo imageable dielectric；PID）的感光性絕緣膜。
參考圖14，在預保護層111P（參看圖13）上形成罩幕圖案（未繪示），且使用罩幕圖案作為蝕刻罩幕來蝕刻預保護層（參看圖13的111P）的一部分，從而形成下部保護層111。
在形成下部保護層111之後，藉由灰化及剝離製程移除罩幕圖案。蝕刻可為乾式蝕刻。經由乾式蝕刻，形成包含多個第一開口111H的下部保護層111。第一開口111H可具有實質上垂直於支撐基板101的上表面的側壁。在此情況下，第一開口111H可具有矩形橫截面形狀。在其他實施例中，歸因於乾式蝕刻製程的性質，第一開口111H可具有寬度變窄的錐形側壁而非豎直側壁。
第一開口111H部分地暴露黏著層AL的上表面。另外，自上方觀察，黏著層AL的暴露部分可具有圓形形狀。亦即，下部保護層111可包含具有圓柱形形狀的多個第一開口111H。
參考圖15，預晶種層121P藉由物理氣相沈積製程形成於經暴露黏著層AL的上表面及下部保護層111的暴露表面上以具有約100埃至約20,000埃範圍內的厚度。
預晶種層121P可由例如含有選自鈦（Ti）、鈦鎢（TiW）以及鉻（Cr）或其合金中的至少一者的金屬形成。亦即，預晶種層121P可由與黏著層AL實質上相同的材料形成。因此，繪示了預晶種層121P與黏著層AL之間的界面，儘管所述界面看起來可能與如圖15中所示出的不同。
預晶種層121P可充當用於形成凸塊墊123（參看圖17）的晶種。亦即，當藉由電鍍方法形成凸塊墊123（參看圖17）時，預晶種層121P提供電流可流經的路徑，使得凸塊墊123（參看圖17）可形成於預晶種層121P上。
預晶種層121P可形成為共形地覆蓋下部保護層111的第一開口111H。由第一開口111H暴露的黏著層AL的上表面對應於與預晶種層121P直接接觸的一部分。
參考圖16，在預晶種層121P上形成罩幕圖案MP。
罩幕圖案MP可形成為具有暴露預晶種層121P的一部分的圖案。因為由罩幕圖案MP暴露的所述部分與在隨後製程中形成凸塊墊123（參看圖17）的一部分相對應，所以當形成多個凸塊墊123（參看圖17）時，可形成由罩幕圖案MP暴露的多個部分以對應於凸塊墊123（參看圖17）。在下文中，為便於描述，多個凸塊墊123可簡單地稱為凸塊墊123。
參考圖17，凸塊墊123形成於其上形成有罩幕圖案MP的預晶種層121P上。
凸塊墊123可形成為直接接觸由罩幕圖案MP暴露的預晶種層121P的上表面。凸塊墊123可藉由執行電鍍製程而形成。
為形成凸塊墊123，可將其上形成有罩幕圖案MP的支撐基板101置放於池中，且可執行電鍍。凸塊墊123可由例如選自銅（Cu）、鎳（Ni）以及金（Au）或其合金的金屬製成。
凸塊墊123可形成為不完全填充由罩幕圖案MP限定的區，而是僅部分地填充所述區。亦即，凸塊墊123的高度可形成為低於罩幕圖案MP的高度。
參考圖18，執行灰化及剝離製程，且移除罩幕圖案MP（參看圖17）。
凸塊墊123可包含上部結構123T（參看圖20）及下部結構123B（參看圖20）。凸塊墊123的上部結構123T（參看圖20）的寬度可大於凸塊墊123的下部結構123B（參看圖20）的寬度。亦即，凸塊墊123具有T形形狀，且凸塊墊123的側表面可具有階差。
一起參考圖19及圖20（圖20示出圖19的區CC的放大橫截面圖），藉由使用凸塊墊123作為蝕刻罩幕，暴露於外部的經暴露外部晶種層121P（參看圖18）經濕式蝕刻WE以形成金屬晶種層121。
金屬晶種層121可沿著凸塊墊123的上部結構123T的下表面及下部結構123B的側表面設置。
當藉由使用等向性濕式蝕刻WE選擇性地蝕刻預晶種層121P（參看圖18）時，可在設置於凸塊墊123與下部保護層111之間的金屬晶種層121處形成第一底切121C1。亦即，第一底切121C1可形成於金屬晶種層121的接觸上部結構123T的一個端部處。第一底切121C1可在第一方向（X方向）上或沿著第一方向形成。
參考圖21，在下部保護層111上形成絕緣層130以填充凸塊墊123的外圍且包含部分地暴露凸塊墊123的上表面的第二開口130H。可形成多個第二開口130H，且在下文中，為便於描述，多個第二開口130H可稱為第二開口130H。
絕緣層130可由氧化矽或氮化矽製成。在一些實施例中，絕緣層130可包含諸如PID的感光性絕緣膜。感光性絕緣膜的特徵在於其可形成為具有不反射或具有底層形狀的平坦上表面。因此，不管凸塊墊123的形狀如何，絕緣層130可具有平坦輪廓。此外，絕緣層130可填充第一底切121C1。
藉由使用罩幕圖案（未繪示）作為蝕刻罩幕來蝕刻絕緣層130的一部分而形成第二開口130H，且藉由灰化及剝離製程移除罩幕圖案。
蝕刻可為乾式蝕刻。經由乾式蝕刻，形成包含多個第二開口130H的絕緣層130。歸因於蝕刻製程的性質，第二開口130H可具有向下變窄的錐形側壁而非垂直側壁。
第二開口130H部分地暴露凸塊墊123的上表面。另外，如自上方觀察，凸塊墊123的暴露部分可具有圓形形狀。
參考圖22，在凸塊墊123上依序形成重佈層結構140及上部墊161。
重佈層結構140及上部墊161可例如由銅（Cu）、鎳（Ni）、金（Au）、鉻（Cr）、鈦（Ti）或鈀（Pd）或其合金形成。在一些實施例中，重佈層結構140可經由鑲嵌製程形成。因為鑲嵌製程為人所熟知，所以省略其詳細描述。
當重複地執行類似製程時，可形成所有的重佈層結構140、環繞重佈層結構140的絕緣層130、在重佈層結構140上的上部墊161以及環繞上部墊161的上部保護層151。
參考圖23，半導體晶片170安裝為電連接至上部墊161。
可使用焊料凸塊將半導體晶片170電連接至上部墊161。半導體晶片170可為個別化半導體晶粒或模製半導體晶粒的子封裝。安裝半導體晶片170以使得其上形成有連接墊的主動表面可面朝下，且半導體晶片170的連接墊可與上部墊161的上表面對準。
可安裝多個半導體晶片170。多個半導體晶片170中的一些半導體晶片可為邏輯晶片，且其他半導體晶片可為記憶體晶片。為方便起見，以下描述可參考一個半導體晶片170而非多個半導體晶片170。
在電連接半導體晶片170及焊料凸塊的製程中，可在半導體晶片170與焊料凸塊之間形成間隙。此間隙可導致半導體晶片170與焊料凸塊之間的連接可靠性的問題。為確保可靠性，可注入且固化底部填充物（未繪示）以加強連接。
半導體晶片170藉由底部填充物更穩定地固定於焊料凸塊上，且儘管半導體晶片170與焊料凸塊之間的熱膨脹係數存在差異，但仍可防止半導體晶片170與焊料凸塊的電分離。在一些實施例中，模製部件181（參看圖24）可直接填充至半導體晶片170與焊料凸塊之間的間隙中，且在此情況下，可不需要底部填充物。
參考圖24，形成模製部件181以環繞半導體晶片170的側表面及上表面。
模製部件181可保護半導體晶片170免受諸如衝擊的外部影響。為了執行此作用，模製部件181可由環氧樹脂模製化合物、樹脂或類似物製成。
在一些實施例中，模製部件181可僅覆蓋半導體晶片170的側表面，且可將半導體晶片170的上表面暴露於外部。
參考圖25，將載體基板102附接至模製部件181以便面向支撐基板101（參看圖24），且移除支撐基板101（參看圖24）。
載體基板102可包含例如玻璃或氧化鋁。為了促進載體基板102的附接，可在載體基板102與模製部件181之間形成第二黏著層（未繪示）。第二黏著層可呈在預定壓力下可容易變形的液體形式或凝膠形式。
為了分離及移除支撐基板101（參看圖24），可用雷射輻照支撐基板101（參看圖24）。可藉由雷射的照射減弱黏著層AL與支撐基板101（參看圖24）之間的接合力，且可分離支撐基板101（參看圖24）。
一起參考圖26及圖27（圖27示出圖26的區DD的放大橫截面圖），藉由濕式蝕刻WE移除外部暴露的黏著層AL（參看圖25）。
歸因於濕式蝕刻WE，可暴露凸塊墊123的下表面及下部保護層111的最低表面。凸塊墊123的下表面的水平高度可與下部保護層111的最低表面的水平高度實質上相同。
當使用濕式等向性蝕刻WE蝕刻黏著層AL（參看圖25）時，可在設置於凸塊墊123與下部保護層111之間的金屬晶種層121處形成第二底切121C2。亦即，第二底切121C2可形成於金屬晶種層121的接觸下部結構123B的另一端部處。第二底切121C2可在第三方向（Z方向）上（或沿著第三方向）形成。
一起參考圖28及圖29（圖29示出圖28的區EE的放大橫截面圖），在凸塊墊123的下表面上形成作為外部連接端子的凸塊結構191。
在一些實施例中，凸塊結構191可形成為焊球。焊球以球形形狀形成，且可附接至凸塊墊123的下表面。在其他實施例中，關於凸塊結構191，焊料層可形成於凸塊墊123的下表面上，且焊料層可藉由回焊製程熔融以形成回焊層。
在一些實施例中，凸塊結構191可具有大於下部結構123B（參看圖3及圖4）的第二寬度W2的第三寬度W3。根據此類實施例，第一底切121C1可由絕緣層130填充，且第二底切121C2可由凸塊結構191填充。凸塊結構191可設置為接觸下部結構123B的下表面，且可設置為不接觸下部保護層111的下表面。此外，凸塊結構191可經由第二底切121C2接觸下部結構123B的側表面及下部保護層111的側表面。
再次參考圖1，可移除載體基板102以完成半導體封裝10的製造。因此，關於根據本發明概念的實施例的半導體封裝10，可藉由形成具有T形形狀的凸塊墊123及藉由在凸塊墊123與下部保護層111之間形成金屬晶種層121來防止凸塊墊123與下部保護層111之間出現剝離缺陷。
圖30示出示意性地繪示根據本發明概念的實施例的半導體封裝的組態的組態圖。
參考圖30，半導體封裝1000可包含藉由匯流排1060互連的微處理單元（micro processing unit；MPU）1010、記憶體1020、介面1030、圖形處理單元（graphic processing unit；GPU）1040以及功能區塊1050。半導體封裝1000可包含MPU 1010及GPU 1040兩者，或可僅包含MPU 1010及GPU 1040中的一者。
MPU 1010可包含核心及快取記憶體。舉例而言，MPU 1010可包含多核心。多核心的每一核心可具有相同或不同效能。另外，多核心的每一核心可同時激活或可在不同時間激活。
記憶體1020可儲存在MPU 1010的控制下由功能區塊1050處理的結果。介面1030可經由外部裝置交換資訊或信號。GPU 1040可執行圖形功能。舉例而言，GPU 1040可執行為視訊編碼解碼器或可處理3D圖形。功能區塊1050可執行各種功能。舉例而言，當半導體封裝1000為用於行動裝置中的應用處理器時，功能區塊1050中的一些功能區塊可執行通信功能。
半導體封裝1000可包含上文參考圖1至圖11所描述的半導體封裝10、半導體封裝20、半導體封裝30、半導體封裝40、半導體封裝50、半導體封裝60、半導體封裝70以及半導體封裝80中的任一者。
儘管本發明概念已參考其實施例進行特定繪示及描述，但應理解，可在不脫離以下申請專利範圍的精神及範疇的情況下對形式及細節作出各種改變。
10、20、30、40、50、60、70、80、1000:半導體封裝 101:支撐基板 111:下部保護層 111H:第一開口 111P:預保護層 121:金屬晶種層 121C1:第一底切 121C2:第二底切 121P:預晶種層 123、323、423:凸塊墊 123B、323B、423B:下部結構 123C:中心軸 123H:厚度 123T、323T、423T:上部結構 130:絕緣層 130H:第二開口 131:第一絕緣層 132:第二絕緣層 133:第三絕緣層 134:第四絕緣層 135:第五絕緣層 140:重佈層結構 141:第一重佈層線 142:第二重佈層線 143:第三重佈層線 144:第四重佈層線 151:上部保護層 160:框架結構 161:上部墊 163、165、167、711、861:貫穿電極 170、770、870:半導體晶片 171:半導體基板 173:電極墊 175:焊料凸塊 181、681、781、881:模製部件 191、291:凸塊結構 323R:凹面 423R:凸面 530:上部絕緣層 540:上部重佈層結構 560:被動元件 570、670:第二半導體晶片 581:第二模製部件 621:第二金屬晶種層 623:第二凸塊墊 630:第二絕緣層 640:第二重佈層結構 683:底部填充物 691:封裝間連接結構 710:插入件 720、820:封裝基板 771、871:第一半導體晶片 772、872、873:第二半導體晶片 783:散熱部件 785:包封體 791、891:外部端子 1010:微處理單元 1020:記憶體 1030:介面 1040:圖形處理單元 1050:功能區塊 1060:匯流排 AA、BB、CC、DD、EE:區 AL:黏著層 C1:第一長度 C2:第二長度 MP:罩幕圖案 S10:方法 S110:第一步驟 S120:第二步驟 S130:第三步驟 S140:第四步驟 S150:第五步驟 S160:第六步驟 S170:第七步驟 S180:第八步驟 S190:第九步驟 SP1:第一子封裝 SP2:第二子封裝 W1:第一寬度 W2:第二寬度 W3:第三寬度 W4:第四寬度 WE:濕式蝕刻 X:第一方向 Y:第二方向 Z:第三方向
自結合隨附圖式進行的以下詳細描述將更清楚地理解本發明概念的實施例，在隨附圖式中： 圖1示出根據本發明概念的實施例的半導體封裝的橫截面圖。 圖2示出圖1的區AA的放大橫截面圖。 圖3示出繪示圖2的凸塊墊的仰視圖。 圖4示出圖2的區BB的放大橫截面圖。 圖5示出根據本發明概念的實施例的半導體封裝的一部分的放大橫截面圖。 圖6示出根據本發明概念的其他實施例的半導體封裝的一部分的放大橫截面圖。 圖7示出根據本發明概念的又另外實施例的半導體封裝的一部分的放大橫截面圖。 圖8示出根據本發明概念的實施例的半導體封裝的橫截面圖。 圖9示出根據本發明概念的其他實施例的半導體封裝的橫截面圖。 圖10示出根據本發明概念的另外實施例的半導體封裝的橫截面圖。 圖11示出根據本發明概念的又另外實施例的半導體封裝的橫截面圖。 圖12示出描述根據本發明概念的實施例的製造半導體封裝的方法的方塊圖。 圖13、圖14、圖15、圖16、圖17、圖18、圖19、圖20、圖21、圖22、圖23、圖24、圖25、圖26、圖27、圖28以及圖29示出根據製程順序描述根據本發明概念的實施例的製造半導體封裝的方法的橫截面圖。 圖30示出示意性地繪示根據本發明概念的實施例的半導體封裝的組態的組態圖。
10:半導體封裝
111:下部保護層
121:金屬晶種層
123:凸塊墊
130:絕緣層
140:重佈層結構
151:上部保護層
161:上部墊
170:半導體晶片
171:半導體基板
173:電極墊
175:焊料凸塊
181:模製部件
191:凸塊結構
AA:區
X:第一方向
Y:第二方向
Z:第三方向

Claims (20)

  1. 一種半導體封裝，包括： 半導體晶片； 重佈層結構，設置於所述半導體晶片下方； 凸塊墊，設置於所述重佈層結構下方，所述凸塊墊具有第一寬度的上部結構及小於所述第一寬度的第二寬度的下部結構； 金屬晶種層，沿著所述上部結構的下表面及所述下部結構的側表面設置； 絕緣層，環繞所述重佈層結構及所述凸塊墊；以及 凸塊結構，設置於所述凸塊墊下方， 其中第一底切設置於所述金屬晶種層的接觸所述上部結構的一個端部處，且第二底切設置於所述金屬晶種層的接觸所述下部結構的另一端部處。
  2. 如請求項1所述的半導體封裝，其中所述重佈層結構包括： 多個重佈層線；以及 多個通孔，連接至所述多個重佈層線， 其中所述多個通孔具有隨著遠離所述半導體晶片而變窄的錐形形狀。
  3. 如請求項1所述的半導體封裝，其中所述第一底切與所述第二底切彼此正交延伸。
  4. 如請求項3所述的半導體封裝，其中所述第一底切用所述絕緣層填充，且所述第二底切用所述凸塊結構填充。
  5. 如請求項4所述的半導體封裝，其中所述凸塊結構具有大於所述下部結構的所述第二寬度的第三寬度。
  6. 如請求項3所述的半導體封裝，其中所述第一底切用所述絕緣層填充，且所述第二底切是空的。
  7. 如請求項6所述的半導體封裝，其中所述凸塊結構具有第三寬度，且所述下部結構的所述第二寬度大於或等於所述凸塊結構的所述第三寬度。
  8. 如請求項1所述的半導體封裝，其中所述金屬晶種層包括鈦（Ti）、鈦鎢（TiW）以及鉻（Cr）中的至少一者。
  9. 如請求項1所述的半導體封裝，其中所述下部結構的下表面的水平高度與所述絕緣層的最低表面的水平高度相同， 其中所述凸塊結構與所述下部結構的所述下表面及所述側表面接觸，且 其中所述凸塊結構與所述絕緣層的側表面接觸，且不與所述絕緣層的所述下表面接觸。
  10. 如請求項1所述的半導體封裝，其中所述上部結構的上表面向上凸起或向下凹入。
  11. 一種半導體封裝，包括： 第一子封裝，包含第一半導體晶片； 第二子封裝，設置於所述第一子封裝上且包含第二半導體晶片；以及 封裝間連接結構，將所述第一子封裝連接至所述第二子封裝， 其中所述第一子封裝及所述第二子封裝中的每一者包括 下部重佈層結構， 凸塊墊，設置於所述下部重佈層結構下方，所述凸塊墊具有第一寬度的上部結構及小於所述第一寬度的第二寬度的下部結構， 金屬晶種層，沿著所述上部結構的下表面及所述下部結構的側表面設置， 下部絕緣層，環繞所述下部重佈層結構及所述凸塊墊，以及 凸塊結構，設置於所述凸塊墊下方， 其中第一底切設置於所述金屬晶種層的接觸所述上部結構的一個端部處，且第二底切設置於所述金屬晶種層的接觸所述下部結構的另一端部處。
  12. 如請求項11所述的半導體封裝，其中所述第一子封裝更包括設置於所述第一半導體晶片的側表面周圍的框架結構，且 其中所述第一子封裝的所述框架結構及所述下部重佈層結構藉由設置於所述框架結構內部的貫穿電極彼此電連接。
  13. 如請求項12所述的半導體封裝，其中所述封裝間連接結構將所述第一子封裝的所述框架結構連接至所述第二子封裝的所述下部重佈層結構。
  14. 如請求項11所述的半導體封裝，其中所述第一底切與所述第二底切彼此正交延伸。
  15. 如請求項14所述的半導體封裝，其中所述凸塊結構具有大於所述下部結構的所述第二寬度的第三寬度， 其中所述第一底切用所述下部絕緣層填充，且 其中所述第二底切用所述凸塊結構填充。
  16. 如請求項14所述的半導體封裝，其中所述凸塊結構具有第三寬度，且所述下部結構的所述第二寬度大於或等於所述凸塊結構的所述第三寬度， 其中所述第一底切用所述下部絕緣層填充，且 其中所述第二底切是空的。
  17. 如請求項11所述的半導體封裝，其中所述下部結構的下表面的水平高度與所述下部絕緣層的最低表面的水平高度相同， 其中所述凸塊結構與所述下部結構的所述下表面及所述側表面接觸，且 其中所述凸塊結構與所述下部絕緣層的側表面接觸，且不與所述下部絕緣層的所述下表面接觸。
  18. 一種半導體封裝，包括： 凸塊結構； T形凸塊墊，設置於所述凸塊結構上，所述T形凸塊墊具有上部結構及下部結構，所述上部結構與所述下部結構之間具有階差； 重佈層結構，設置於所述T形凸塊墊上且具有多個重佈層線； 多個絕緣層，環繞所述重佈層結構及所述T形凸塊墊； 金屬晶種層，共形地設置於所述上部結構的下表面與所述多個絕緣層的最低絕緣層之間及所述下部結構的側表面與所述最低絕緣層之間；以及 半導體晶片，設置於所述重佈層結構上且電連接至所述凸塊結構， 其中第一底切設置於所述金屬晶種層的一個端部處，第二底切設置於所述金屬晶種層的另一端部處，且所述第一底切與所述第二底切彼此正交延伸。
  19. 如請求項18所述的半導體封裝，更包括： 額外半導體晶片，設置於所述重佈層結構上；以及 模製部件，環繞所述半導體晶片及所述額外半導體晶片。
  20. 如請求項18所述的半導體封裝，其中所述T形凸塊墊與所述最低絕緣層之間的所述金屬晶種層的厚度為約100埃至約20,000埃，且 其中所述金屬晶種層包括鈦（Ti）、鈦鎢（TiW）以及鉻（Cr）中的至少一者。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI849725B (zh) * 2022-06-16 2024-07-21 日商鎧俠股份有限公司 半導體裝置及半導體裝置之製造方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102517379B1 (ko) * 2020-02-14 2023-03-31 삼성전자주식회사 반도체 패키지의 제조 방법
US11961873B2 (en) * 2020-05-11 2024-04-16 Seoul Viosys Co., Ltd. Light emitting device for display and display apparatus having the same
KR20210147363A (ko) * 2020-05-28 2021-12-07 에스케이하이닉스 주식회사 반도체 장치 및 그 제조방법
KR20220021615A (ko) 2020-08-14 2022-02-22 삼성전자주식회사 반도체 패키지
KR20220126850A (ko) * 2021-03-09 2022-09-19 삼성전자주식회사 반도체 패키지
KR20220167699A (ko) * 2021-06-14 2022-12-21 삼성전자주식회사 반도체 패키지

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4881211B2 (ja) 2007-04-13 2012-02-22 新光電気工業株式会社 配線基板の製造方法及び半導体装置の製造方法及び配線基板
US7928534B2 (en) 2008-10-09 2011-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad connection to redistribution lines having tapered profiles
US8872326B2 (en) * 2012-08-29 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional (3D) fan-out packaging mechanisms
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
DE112013007038B4 (de) 2013-06-29 2024-08-29 Tahoe Research, Ltd. Zwischenverbindungsstruktur umfassend Metall-Rückseiten-Umverteilungsleitungen mit sehr kleinem Teilungsabstand kombiniert mit Durchkontaktierungen
US9368454B2 (en) 2013-10-10 2016-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with shielding layer in post-passivation interconnect structure
KR101538573B1 (ko) 2014-02-05 2015-07-21 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
JP6423313B2 (ja) * 2015-05-26 2018-11-14 新光電気工業株式会社 電子部品内蔵基板及びその製造方法と電子装置
KR101703964B1 (ko) * 2015-07-10 2017-02-22 광주과학기술원 카드뮴 나노클러스터 형성에 따른 형광세기를 이용한 카드뮴의 검출방법 및 카드뮴 검출키트
KR101933408B1 (ko) 2015-11-10 2018-12-28 삼성전기 주식회사 전자부품 패키지 및 이를 포함하는 전자기기
US10217716B2 (en) 2016-09-12 2019-02-26 Mediatek Inc. Semiconductor package and method for fabricating the same
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10665473B2 (en) 2017-11-08 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same
KR102551034B1 (ko) * 2018-09-07 2023-07-05 삼성전자주식회사 반도체 패키지 및 그 제조방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI849725B (zh) * 2022-06-16 2024-07-21 日商鎧俠股份有限公司 半導體裝置及半導體裝置之製造方法

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