TW201820584A - 扇出型半導體封裝 - Google Patents

扇出型半導體封裝 Download PDF

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Publication number
TW201820584A
TW201820584A TW106109524A TW106109524A TW201820584A TW 201820584 A TW201820584 A TW 201820584A TW 106109524 A TW106109524 A TW 106109524A TW 106109524 A TW106109524 A TW 106109524A TW 201820584 A TW201820584 A TW 201820584A
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layer
redistribution layer
fan
semiconductor package
interconnection member
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TW106109524A
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TWI669803B (zh
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金炳讚
白龍浩
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三星電機股份有限公司
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Publication of TWI669803B publication Critical patent/TWI669803B/zh

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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06548—Conductive via connections through the substrate, container, or encapsulation
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
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    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
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Abstract

一種扇出型半導體封裝包括：第一互連構件，具有貫穿孔；處理器晶片，安置於貫穿孔中；記憶體晶片，安置於貫穿孔中且包括彼此堆疊的多個晶粒；囊封體，囊封第一互連構件的至少某些部分、記憶體晶片的至少某些部分及處理器晶片的至少某些部分；以及第二互連構件，安置於第一互連構件上、記憶體晶片的主動表面上及處理器晶片的主動表面上。第一互連構件及第二互連構件分別包括重佈線層，重佈線層電性連接至處理器晶片的連接墊及記憶體晶片的連接墊，且處理器晶片的連接墊與記憶體晶片的連接墊藉由第二互連構件的重佈線層而電性連接至彼此。

Description

扇出型半導體封裝
本發明是有關於一種半導體封裝，且更具體而言，是有關於一種連接端子可在安置有半導體晶片的區之外延伸的扇出型半導體封裝。
與半導體晶片相關的技術發展中的近期顯著趨勢是減小半導體晶片的尺寸。因此，在封裝技術的情形中，隨著對小尺寸半導體晶片等的需求的快速增加，已經需要實作在包括多個引腳的同時具有緊湊尺寸的半導體封裝。
為滿足上述技術要求所提出的一種封裝技術是扇出型封裝。此種扇出型封裝藉由在安置有半導體晶片的區之外對連接端子進行重佈線而具有緊湊尺寸且可達成對多個引腳的實作。
本發明的態樣可提供一種能夠執行各種功能、被薄化的以及具有優異的安裝可靠性的扇出型半導體封裝。
根據本發明的態樣，可提供一種扇出型半導體封裝，在所述扇出型半導體封裝中，處理器晶片與記憶體晶片在互連構件中的相同的貫穿孔或不同的貫穿孔中實質上安置於相同的水平高度上且藉由重佈線層電性連接至彼此。
根據本發明的態樣，一種扇出型半導體封裝可包括：第一互連構件，具有貫穿孔；處理器晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊；記憶體晶片，安置於所述第一互連構件的所述貫穿孔中，具有主動表面，且包括彼此堆疊的多個晶粒，所述主動表面上安置有連接墊；囊封體，囊封所述第一互連構件的至少某些部分、所述記憶體晶片的至少某些部分及所述處理器晶片的至少某些部分；以及第二互連構件，安置於所述第一互連構件上、所述記憶體晶片的所述主動表面上及所述處理器晶片的所述主動表面上。所述第一互連構件及所述第二互連構件分別包括重佈線層，所述重佈線層電性連接至所述處理器晶片的所述連接墊及所述記憶體晶片的所述連接墊，且所述處理器晶片的所述連接墊與所述記憶體晶片的所述連接墊藉由所述第二互連構件的所述重佈線層而電性連接至彼此。
在下文中，將參照附圖闡述本發明中的各示例性實施例。在所述附圖中，為清晰起見，可誇大或省略各組件的形狀、大小等。
在說明中一組件與另一組件的「連接」的含義包括藉由黏合層的間接連接以及兩個組件之間的直接連接。另外，「電性連接」意指包括實體連接及實體斷開的概念。應理解，當以「第一」及「第二」來指代元件時，所述元件並非由此受到限制。使用「第一」及「第二」可能僅用於將所述元件與其他元件區分開的目的，且可不限制所述元件的順序或重要性。在某些情形中，在不背離本文中所提出的申請專利範圍的範圍的條件下，第一元件可被稱作第二元件。相似地，第二元件亦可被稱作第一元件。
本文中所使用的用語「示例性實施例」並不指代同一示例性實施例，而是為強調與另一示例性實施例的特定特徵或特性不同的特定特徵或特性而提供。然而，本文中所提供的示例性實施例被視為能夠藉由彼此整體地或部分地組合而實作。舉例而言，即使並未在另一示例性實施例中闡述在特定示例性實施例中闡述的一個元件，然而除非在本文中提供了相反或矛盾的說明，否則所述元件亦可被理解為與另一示例性實施例相關的說明。
本文所用的用語僅用來對示例性實施例進行闡述而非限制本發明。在此種情形中，除非在上下文中另有解釋，否則單數形式包括複數形式。電子裝置
圖1是說明電子裝置系統的實例的示意性方塊圖。
參照圖1，電子裝置1000中可容置有母板1010。母板1010可包括實體地連接至或電性地連接至母板1010的晶片相關組件1020、網路相關組件1030、其他組件1040等。該些組件可連接至以下將闡述的其他組件，以形成各種訊號線1090。
晶片相關組件1020可包括：記憶體晶片，例如揮發性記憶體（例如動態隨機存取記憶體（dynamic random access memory，DRAM））、非揮發性記憶體（例如唯讀記憶體（read only memory，ROM））、快閃記憶體等；應用處理器晶片，例如中央處理器（例如中央處理單元（central processing unit，CPU））、圖形處理器（例如圖形處理單元（graphic processing unit，GPU））、數位訊號處理器、密碼處理器（cryptographic processor）、微處理器、微控制器等；及邏輯晶片，例如類比至數位轉換器（analog-to-digital converter，ADC）、應用專用積體電路（application-specific integrated circuit，ASIC）等。然而，晶片相關組件1020並非僅限於此，而是亦可包括其他類型的晶片相關組件。另外，晶片相關組件1020可彼此組合。
網路相關組件1030可包括以下協定：無線保真（wireless fidelity，Wi-Fi）（電氣及電子工程師學會（Institute of Electrical And Electronics Engineers，IEEE）802.11家族等）、全球互通微波存取（worldwide interoperability for microwave access，WiMAX）（IEEE 802.16家族等）、IEEE 802.20、長期演進（long term evolution，LTE）、僅支援資料的演進（evolution data only，Ev-DO）、高速封包存取+（high speed packet access +，HSPA+）、高速下行封包存取+（high speed downlink packet access +，HSDPA+）、高速上行封包存取+（high speed uplink packet access +，HSUPA+）、增強型資料GSM環境（enhanced data GSM environment，EDGE）、全球行動通訊系統（global system for mobile communications，GSM）、全球定位系統（global positioning system，GPS）、通用封包無線電服務（general packet radio service，GPRS）、分碼多重存取（code division multiple access，CDMA）、分時多重存取（time division multiple access，TDMA）、數位增強型無線電訊（digital enhanced cordless telecommunications，DECT）、藍芽、3G協定、4G協定及5G協定以及繼上述協定之後指定的任何其他無線協定及有線協定。然而，網路相關組件1030並非僅限於此，而是亦可包括多種其他無線標準或協定或者有線標準或協定。另外，網路相關組件1030可與上述晶片相關組件1020一起彼此組合。
其他組件1040可包括高頻電感器、鐵氧體電感器（ferrite inductor）、功率電感器、鐵氧體珠粒、低溫共燒陶瓷（low temperature co-fired ceramic，LTCC）、電磁干擾（electromagnetic interference，EMI）濾波器、多層陶瓷電容器（multilayer ceramic capacitor，MLCC）等。然而，其他組件1040並非僅限於此，而是亦可包括用於各種其他目的的被動式（passive）組件等。另外，其他組件1040可與上述晶片相關組件1020或網路相關組件1030一起彼此組合。
端視電子裝置1000的一種類型，電子裝置1000可包括可實體地連接至或電性地連接至母板1010或可不實體地連接至或不電性地連接至母板1010的其他組件。該些其他組件可包括例如照相機模組1050、天線1060、顯示器裝置1070、電池1080、音訊編解碼器（圖中未示出）、視訊編解碼器（圖中未示出）、功率放大器（圖中未示出）、羅盤（圖中未示出）、加速度計（圖中未示出）、陀螺儀（圖中未示出）、揚聲器（圖中未示出）、大容量儲存單元（例如硬碟驅動機）（圖中未示出）、光碟（compact disk，CD）（圖中未示出）、數位多功能光碟（digital versatile disk，DVD）（圖中未示出）等。然而，所述其他組件並非僅限於此，而是亦可端視電子裝置1000等的一種類型包括用於各種目的的其他組件。
電子裝置1000可為智慧型電話、個人數位助理（personal digital assistant，PDA）、數位攝影機、數位照相機（digital still camera）、網路系統、電腦、監視器、平板個人電腦（tablet PC）、膝上型個人電腦、隨身型易網機個人電腦（netbook PC）、電視、視訊遊戲機（video game machine）、智慧型手錶、汽車組件等。然而，電子裝置1000並非僅限於此，而是可為處理資料的任何其他電子裝置。
圖2是說明電子裝置的實例的示意性立體圖。
參照圖2，半導體封裝可出於各種目的而在如上所述的各種電子裝置1000中使用。舉例而言，主板1110可容置於智慧型電話1100的主體1101中，且各種電子組件1120可實體地連接至或電性地連接至主板1110。另外，可實體地連接至或電性地連接至主板1110或可不實體地連接至或不電性地連接至主板1110的其他組件（例如照相機模組1130）可容置於主體1101中。電子組件1120中的某些組件可為晶片相關組件，且半導體封裝100可為例如晶片相關組件中的應用處理器，但並非僅限於此。所述電子裝置未必僅限於智慧型電話1100，而是可為如上所述其他電子裝置。半導體封裝
一般而言，在半導體晶片中整合有諸多精細的電路。然而，半導體晶片本身無法用作完成的半導體產品，且可因外部物理衝擊或化學衝擊而被損壞。因此，半導體晶片無法單獨使用，而是可被封裝於電子裝置等中且在電子裝置等中以封裝狀態使用。
此處，由於在電性連接方面，半導體晶片與電子裝置的主板之間存在電路寬度差，因此需要進行半導體封裝。詳言之，半導體晶片的連接墊的大小及半導體晶片的各連接墊之間的間隔是非常精細的，但在電子裝置中使用的主板的組件安裝墊的大小及主板的各組件安裝墊之間的間隔顯著地大於半導體晶片的連接墊的大小及各連接墊之間的間隔。因此，可能難以將半導體晶片直接安裝於主板上，且需要用於緩衝半導體晶片與主板之間的電路寬度差的封裝技術。
端視半導體封裝的結構及目的，利用封裝技術製造的半導體封裝可被劃分成扇入型半導體封裝或扇出型半導體封裝。
在下文中，將參照圖式更詳細地闡述所述扇入型半導體封裝及所述扇出型半導體封裝。扇入型半導體封裝
圖3A及圖3B是說明在被封裝之前及被封裝之後的扇入型半導體封裝的狀態的示意性剖視圖。
圖4是說明扇入型半導體封裝的封裝製程的示意性剖視圖。
參照所述圖式，半導體晶片2220可為例如處於裸露狀態下的積體電路（integrated circuit，IC），半導體晶片2220包括：主體2221，包含矽（Si）、鍺（Ge）、砷化鎵（GaAs）等；連接墊2222，形成於主體2221的一個表面上且包含例如鋁（Al）等導電材料；以及例如氧化物膜、氮化物膜等的保護層2223，形成於主體2221的一個表面上且覆蓋連接墊2222的至少某些部分。在此種情形中，由於連接墊2222顯著小，因此難以將積體電路（IC）安裝於中級印刷電路板（printed circuit board，PCB）上以及電子裝置的主板上等。
因此，可端視半導體晶片2220的大小而在半導體晶片2220上形成互連構件2240以對連接墊2222進行重佈線。可藉由以下步驟來形成互連構件2240：利用例如感光成像介電（photoimagable dielectric，PID）樹脂等絕緣材料在半導體晶片2220上形成絕緣層2241；形成使連接墊2222開口的介層窗孔2243h；且接著形成配線圖案2242及介層窗2243。然後，可形成保護互連構件2240的保護層2250、可形成開口2251及可形成凸塊下金屬層2260等。亦即，可藉由一系列製程而製造出包括例如半導體晶片2220、互連構件2240、保護層2250及凸塊下金屬層2260的扇入型半導體封裝2200。
如上所述，所述扇入型半導體封裝可具有所述半導體晶片的例如輸入/輸出（input/output，I/O）端子等所有連接墊均安置於半導體晶片內的封裝形式，且可具有優異的電性特性並以低成本進行生產，可具有優異的電性特性並可以低成本進行生產。因此，已以扇入型半導體封裝形式製造出安裝於智慧型電話中的諸多元件。詳言之，已開發出安裝於智慧型電話中的諸多元件以使得能夠在具有緊湊大小的同時實作快速訊號轉移。
然而，由於所有的輸入/輸出端子均需要安置於扇入型半導體封裝中的半導體晶片內，因此扇入型半導體封裝具有大的空間限制。因此，難以將此結構應用於具有大量輸入/輸出端子的半導體晶片或具有緊湊大小的半導體晶片。另外，由於上述缺點，扇入型半導體封裝無法在電子裝置的主板上直接安裝及使用。此處，即使在藉由重佈線製程增大了半導體晶片的輸入/輸出端子的大小及半導體晶片的各輸入/輸出端子之間的間隔的情形中，半導體晶片的輸入/輸出端子的大小及半導體晶片的各輸入/輸出端子之間的間隔可能仍不足以將扇入型半導體封裝直接安裝於電子裝置的主板上。
圖5是說明扇入型半導體封裝安裝於插板基板上且最終安裝於電子裝置的主板上的情形的示意性剖視圖。
圖6是說明扇入型半導體封裝嵌於插板基板中且最終安裝於電子裝置的主板上的情形的示意性剖視圖。
參照所述圖式，在扇入型半導體封裝2200中，半導體晶片2220的連接墊2222（即，輸入/輸出端子）可經由插板基板2301再次進行重佈線，且扇入型半導體封裝2200可在被安裝於插板基板2301上的狀態下最終安裝於電子裝置的主板2500上。在此種情形中，可藉由底部填充樹脂2280等來固定焊料球2270等，且半導體晶片2220的外表面可被覆蓋以模製材料2290等。作為另外一種選擇，扇入型半導體封裝2200可嵌於單獨的插板基板2302中，半導體晶片2220的連接墊2222（即，輸入/輸出端子）可在扇入型半導體封裝2200嵌於插板基板2302中的狀態下藉由插板基板2302再次進行重佈線，且扇入型半導體封裝2200可最終安裝於電子裝置的主板2500上。
如上所述，可能難以在電子裝置的主板上直接安裝並使用扇入型半導體封裝。因此，所述扇入型半導體封裝可安裝於單獨的插板基板上且接著藉由封裝製程安裝於電子裝置的主板上；或者可在嵌於插板基板中的狀態下而在電子裝置的主板上安裝及使用。扇出型半導體封裝
圖7是說明扇出型半導體封裝的示意性剖視圖。
參照所述圖式，在扇出型半導體封裝2100中，舉例而言，半導體晶片2120的外表面可被囊封體2130保護，且半導體晶片2120的連接墊2122可藉由互連構件2140而在半導體晶片2120之外進行重佈線。在此種情形中，在互連構件2140上可進一步形成保護層2150，且在保護層2150的開口中可進一步形成凸塊下金屬層2160。在凸塊下金屬層2160上可進一步形成焊料球2170。半導體晶片2120可為包括主體2121、連接墊2122、保護層（圖中未示出）等的積體電路（IC）。互連構件2140可包括絕緣層2141、形成於絕緣層2141上的重佈線層2142及將連接墊2122及重佈線層2142電性連接至彼此的介層窗2143。
如上所述，所述扇出型半導體封裝可具有半導體晶片的輸入/輸出端子藉由形成於半導體晶片上的互連構件而在所述半導體晶片之外進行重佈線並安置於所述半導體晶片之外的形式。如上所述，在扇入型半導體封裝中，半導體晶片的所有輸入/輸出端子均需要安置於半導體晶片內。因此，當半導體晶片的大小減小時，需要減小球的大小及節距，因而使得標準化球佈局無法用於扇入型半導體封裝中。另一方面，所述扇出型半導體封裝具有半導體晶片的輸入/輸出端子藉由形成於上述半導體晶片上的互連構件而在半導體晶片之外進行重佈線並安置於半導體晶片之外的形式。因此，即使在半導體晶片的大小減小的情形中，實際上仍可在扇出型半導體封裝中使用標準化球佈局，以使得所述扇出型半導體封裝可在不使用單獨的插板基板的條件下安裝於電子裝置的主板上，如以下所闡述。
圖8是說明扇出型半導體封裝安裝於電子裝置的主板上的情形的示意性剖視圖。
參照所述圖式，扇出型半導體封裝2100可藉由焊料球2170等安裝於電子裝置的主板2500上。亦即，如上所述，扇出型半導體封裝2100包括互連構件2140，互連構件2140形成於半導體晶片2120上且能夠將連接墊2122重佈線至半導體晶片2120的區域之外的扇出區，以使得實際上可在扇出型半導體封裝2100中使用標準化球佈局。因此，扇出型半導體封裝2100可在不使用單獨的插板基板等的條件下安裝於電子裝置的主板2500上。
如上所述，由於所述扇出型半導體封裝可在不使用單獨的插板基板的條件下安裝於電子裝置的主板上，因此所述扇出型半導體封裝可被實作成具有較使用插板基板的扇入型半導體封裝的厚度小的厚度。因此，所述扇出型半導體封裝可被微型化及薄化。另外，所述扇出型半導體封裝具有優異的熱特性及電性特性，以使得所述扇出型半導體封裝尤其適合用於行動產品。因此，所述扇出型半導體封裝可被實作成較使用印刷電路板（PCB）的通用堆疊封裝（package-on-package，POP）型半導體封裝更為緊湊的形式，且可解決因出現翹曲現象而出現的問題。
同時，所述扇出型半導體封裝指代用於如上所述將半導體晶片安裝於電子裝置等的主板上且保護所述半導體晶片不受外部衝擊的封裝技術，並且所述扇出型半導體封裝在概念上不同於具有與扇出型半導體封裝的規模、目的等不同的規模、目的等的印刷電路板（PCB）（例如插板基板等），且所述印刷電路板中嵌置有扇入型半導體封裝。
在下文中，將參照圖式闡述一種能夠同時地執行各種功能、被薄化的以及具有優異的安裝可靠性的扇出型半導體封裝。
圖9是說明扇出型半導體封裝的實例的示意性剖視圖。
圖10是沿圖9所示的扇出型半導體封裝的線I-I'截取的示意性平面圖。
參照圖式，根據本發明中的示例性實施例的扇出型半導體封裝100A可包括：第一互連構件110，具有貫穿孔110H；處理器晶片120，安置於第一互連構件110的貫穿孔110H中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊122；記憶體晶片125，安置於第一互連構件110的貫穿孔110H中，具有主動表面且具有堆疊有多個晶粒126及127的形式，所述主動表面上安置有連接墊129；囊封體130，囊封第一互連構件110的至少某些部分、記憶體晶片125的至少某些部分及處理器晶片120的至少某些部分；第二互連構件140，安置於第一互連構件110上及記憶體晶片125的主動表面上以及處理器晶片120的主動表面上；保護層150，安置於第二互連構件140上；凸塊下金屬層160，形成於保護層150的開口151中；連接端子170，形成於凸塊下金屬層160上；加強層183，安置於囊封體130上；樹脂層184，安置於加強層183上；開口185，穿透過樹脂層184、加強層183及囊封體130，且暴露出第一互連構件110的重佈線層112b的至少某些部分；以及表面安裝技術（surface mounted technology，SMT）組件，表面安裝於保護層150上。第一互連構件110及第二互連構件140可分別包括電性連接至處理器晶片120的連接墊122及記憶體晶片125的連接墊129的重佈線層112a及重佈線層112b以及重佈線層142。處理器晶片120的連接墊122與記憶體晶片125的連接墊129可藉由第二互連構件140的重佈線層142而電性連接至彼此。
一般而言，高效能伺服器及圖形卡具有將處理器晶片與記憶體晶片利用矽系插板基板而連接至彼此的形式。然而，矽系插板基板需要大的大小，且因由在將記憶體晶片連接至精細凸塊時晶粒移位及翹曲而造成的組裝良率及可靠性問題而成為困難的技術。為解決此一問題，可考量以晶圓級封裝的形式封裝處理器晶片且堆疊將記憶體晶片安裝於晶圓級封裝上的插板來實作堆疊封裝（package-on-package，POP）形式。然而，在晶圓級封裝中，利用模製材料來簡單地模製處理器晶片，因而仍存在例如翹曲等可靠性問題且所述堆疊封裝形式並不適合於必須具有薄度的近期現狀。
另一方面，在根據示例性實施例的扇出型半導體封裝100A中，處理器晶片120與記憶體晶片125可在第一互連構件110的貫穿孔110H中實質上安置於相同的水平高度上，且接著藉由第二互連構件140的第二重佈線層142電性連接至彼此，以使得可對處理器晶片120的連接墊與記憶體晶片125的連接墊進行重佈線。因此，扇出型半導體封裝100A可對經由第一互連構件110等施加的機械應力及熱應力具有更強的耐受性，以使得可提高扇出型半導體封裝100A的可靠性。另外，處理器晶片120與記憶體晶片125不安置於不同的水平高度上，而是可實質上安置於相同的水平高度上，以使得扇出型半導體封裝100A的薄化成為可能。另外，具有精細節距的相應的輸入/輸出（input/output，I/O）可經由第二互連構件140被重佈線至扇出區，以使得可提高扇出型半導體封裝100A的安裝可靠性。
同時，處理器晶片120可具有與一般具有記憶功能的晶粒的厚度相比相對較大的厚度。因此，可使用具有堆疊有所述多個晶粒126及晶粒127的形式的記憶體晶片125，只要記憶體晶片125不對扇出型半導體封裝100A的厚度產生影響即可。結果，記憶功能的效率可更加優異。另外，所述多個晶粒126與晶粒127可藉由分別穿透過所述多個晶粒126及晶粒127的多個貫穿電極128a及將所述多個貫穿電極128a連接至彼此的多個凸塊128b而電性連接至彼此。在此種連接形式中，信號傳遞路徑可顯著減小，且囊封體130可填充所述多個晶粒126及晶粒127之間的空間以充分地固定記憶體晶片125，以使得可進一步提高扇出型半導體封裝100A的可靠性。
同時，處理器晶片120可包括應用處理器（application processor，AP），且記憶體晶片125可包括高頻寬記憶體（high bandwidth memory，HBM）及/或寬輸入/輸出（wide I/O，WIO）。如上所述，需要彼此通訊的應用處理器及高頻寬記憶體或寬輸入/輸出安裝於一個扇出型半導體封裝100A中且在所述一個扇出型半導體封裝100A中電性連接至彼此，以使得扇出型半導體封裝100A的薄度可得到提高且應用處理器與高頻寬記憶體或寬輸入/輸出之間的訊號距離可顯著減小。另外，應用處理器與高頻寬記憶體或寬輸入/輸出安置於盡可能小的同一貫穿孔110H中，以使得扇出型半導體封裝100A的製程成本可降低。
在下文中，將更詳細地闡述根據示例性實施例的扇出型半導體封裝100A中所包括的相應的組件。
第一互連構件110可包括重佈線層112a及重佈線層112b，重佈線層112a及重佈線層112b對處理器晶片120的連接墊122及/或記憶體晶片125的連接墊129進行重佈線，以藉此減少第二互連構件140的層的數目。若需要，則第一互連構件110可端視第一互連構件110的材料而維持扇出型半導體封裝100A的剛性且用於確保囊封體130的厚度的均勻性。在某些情形中，由於具有第一互連構件110，根據示例性實施例的扇出型半導體封裝100A可用作具有另一種形式的堆疊封裝的一部分。第一互連構件110可具有貫穿孔110H。貫穿孔110H中可安置有處理器晶片120及記憶體晶片125以與第一互連構件110間隔開預定距離。處理器晶片120的側表面及記憶體晶片125的側表面可被第一互連構件110環繞。然而，此種形式僅為實例，且可進行各種修改以具有其他形式，並且扇出型半導體封裝100A可端視此種形式而執行另一功能。
第一互連構件110可包括絕緣層111、第一重佈線層112a以及第二重佈線層112b，絕緣層111接觸第二互連構件140，第一重佈線層112a接觸第二互連構件140且嵌於絕緣層111中，第二重佈線層112b安置於絕緣層111的與絕緣層111的嵌有第一重佈線層112a的一個表面相對的另一表面上。第一互連構件110可包括介層窗113，介層窗113穿透過絕緣層111且將第一重佈線層112a與第二重佈線層112b電性連接至彼此。第一重佈線層112a及第二重佈線層112b可電性連接至處理器晶片120的連接墊122及記憶體晶片125的連接墊129。當第一重佈線層112a嵌於絕緣層111中時，可顯著減小因第一重佈線層112a的厚度產生的台階，且第二互連構件140的絕緣距離可因此變成恆定的。亦即，自第二互連構件140的重佈線層142至絕緣層111的下表面的距離與自第二互連構件140的重佈線層142至處理器晶片120的連接墊122的距離之間的差可小於第一重佈線層112a的厚度。因此，可易於達成第二互連構件140的高密度配線設計。
絕緣層111的材料並不受特別限制。舉例而言，可使用絕緣材料作為絕緣層111的材料。在此種情形中，所述絕緣材料可為：熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；其中將熱固性樹脂或熱塑性樹脂與無機填料一起浸漬於例如玻璃布（或玻璃織物）等核心材料中的樹脂，例如預浸體、味之素構成膜（Ajinomoto Build up Film，ABF）、FR-4、雙馬來醯亞胺三嗪（Bismaleimide Triazine，BT）等。作為另外一種選擇，亦可使用感光成像介電（PID）樹脂作為絕緣材料。
重佈線層112a及重佈線層112b可用於對處理器晶片120的連接墊122及/或記憶體晶片125的連接墊129進行重佈線，且重佈線層112a及重佈線層112b中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。重佈線層112a及重佈線層112b可端視與重佈線層112a及重佈線層112b對應的層的設計而具有各種功能。舉例而言，重佈線層112a及重佈線層112b可包括接地（ground，GND）圖案、電源（power，PWR）圖案、訊號（signal，S）圖案等。此處，訊號（S）圖案可包括除接地（GND）圖案、電源（PWR）圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層112a及重佈線層112b可包括介層窗墊、連接端子墊等。作為非限制性實例，重佈線層112a及重佈線層112b中的兩者可包括接地圖案。在此種情形中，在第二互連構件140的重佈線層142上形成的接地圖案的數目可顯著減少，以使得配線設計自由度可得以提高。
若需要，則在經由形成於囊封體130中的開口131而自重佈線層112a及重佈線層112b暴露出的重佈線層112b的表面的某些部分上可進一步形成表面處理層P。表面處理層P並不受特別限制，只要表面處理層P是相關技術中已知的即可，但表面處理層P可藉由例如電解鍍金、無電鍍金、有機可焊性保護（organic solderability preservative，OSP）或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金（direct immersion gold，DIG）鍍敷、熱空氣焊料均塗（hot air solder leveling，HASL）等形成。
介層窗113可將在不同層上形成的重佈線層112a與重佈線層112b電性連接至彼此，從而在第一互連構件110中形成電性路徑。介層窗113中的每一者的材料可為導電材料。介層窗113中的每一者可被導電材料完全填充；或導電材料可沿相應的介層窗孔的壁形成。另外，介層窗113中的每一者可具有相關技術中習知的所有形狀，例如錐形形狀、柱形形狀等。同時，當形成介層窗113的孔時，第一重佈線層112a的墊中的某些墊可用作終止層（stopper），且可因此有利於介層窗113中的每一者具有其上表面的寬度大於下表面的寬度的錐形形狀的製程。在此種情形中，介層窗113可與第二重佈線層112b的墊圖案整合在一起。
處理器晶片120可為被設置成在單個晶片中整合有數量為數百個至數百萬個元件或更多元件的應用專用積體電路（ASIC）。在此種情形中，所述應用專用積體電路可為例如應用處理器（AP），例如中央處理器（例如中央處理單元）、圖形處理器（例如圖形處理單元）、現場可程式化閘陣列（field programmable gate array，FPGA）、數位訊號處理器、密碼處理器、微處理器、微控制器等，但並非僅限於此。處理器晶片120可基於主動晶圓而形成。在此種情形中，主體121的基材（base material）可為矽（Si）、鍺（Ge）、砷化鎵（GaAs）等。在主體121上可形成有各種電路。連接墊122可將處理器晶片120電性連接至其他組件。連接墊122中的每一者的材料可為例如鋁（Al）等導電材料。在主體121上可形成暴露出連接墊122的保護層123，且保護層123可為氧化物膜、氮化物膜等抑或可為由氧化物層及氮化物層構成的雙層。連接墊122的下表面可藉由保護層123而相對於囊封體130的下表面具有台階。因此，在某種程度上可防止囊封體130滲透入連接墊122的下表面中的現象。亦可在其他需要的位置中進一步安置絕緣層（圖中未示出）等。
處理器晶片120的被動表面可安置於低於第一互連構件110的第二重佈線層112b的上表面的水平高度上。舉例而言，處理器晶片120的被動表面可安置於低於第一互連構件110的絕緣層111的上表面的水平高度上。處理器晶片120的被動表面與第一互連構件110的第二重佈線層112b的上表面之間的高度差可為2微米或大於2微米，例如可為5微米或大於5微米。在此種情形中，可有效地防止在處理器晶片120的被動表面的隅角中產生裂紋。另外，在使用囊封體130的情形中，可顯著減少處理器晶片120的被動表面上的絕緣距離的偏差。
記憶體晶片125可為在基礎晶粒126上堆疊有多個動態隨機存取記憶體（dynamic random access memory，DRAM）127的高頻寬記憶體（high bandwidth memory，HBM）、寬輸入/輸出（wide I/O，WIO）等，但並非僅限於此。基礎晶粒126及多個動態隨機存取記憶體127可藉由分別穿透過基礎晶粒126及所述多個動態隨機存取記憶體127的所述多個貫穿電極128a以及將所述多個貫穿電極128a連接至彼此的所述多個凸塊128b而電性連接至彼此。貫穿電極128a可為矽穿孔（through-silicon via，TSV）。凸塊128b可包含習知導電材料。基礎晶粒126可具有用於連接至第二互連構件140的連接墊129。同時，在某些情形中，可省略基礎晶粒126，且記憶體晶片125可包括所述多個動態隨機存取記憶體127。在此種情形中，最低的動態隨機存取記憶體可具有連接墊，但並非僅限於此。
囊封體130可保護第一互連構件110、處理器晶片120、記憶體晶片125等。囊封體130的囊封形式並不受特別限制，但可為囊封體130環繞第一互連構件110的至少某些部分、處理器晶片120的至少某些部分、記憶體晶片125的至少某些部分等的形式。舉例而言，囊封體130可覆蓋第一互連構件110以及記憶體晶片125的被動表面及處理器晶片120的被動表面，且填充貫穿孔110H的壁、處理器晶片120的側表面與記憶體晶片125的側表面之間的空間。另外，囊封體130亦可填充處理器晶片120的保護層123與第二互連構件140之間的空間的至少一部分。另外，囊封體130可填充記憶體晶片125的所述多個晶粒126及晶粒127之間的空間的至少某些部分。同時，囊封體130可填充貫穿孔110H，以因此充當黏合劑並端視囊封體130的材料而減少半導體晶片120的彎曲（buckling）。
囊封體130的材料並不受特別限制。舉例而言，可使用絕緣材料作為囊封體130的材料。在此種情形中，所述絕緣材料可為包含無機填料及絕緣樹脂的材料，舉例而言，熱固性樹脂，例如環氧樹脂；熱塑性樹脂，例如聚醯亞胺樹脂；具有被浸漬於熱固性樹脂及熱塑性樹脂中的例如無機填料等加強材料的樹脂，例如味之素構成膜、FR-4、雙馬來醯亞胺三嗪等。作為另外一種選擇，可使用環氧模製化合物（epoxy molding compound，EMC）、感光成像介電質等作為絕緣材料。作為另外一種選擇，亦可使用將熱固性樹脂或熱塑性樹脂與無機填料一起浸漬於例如玻璃布（或玻璃織物）等核心材料中的材料作為所述絕緣材料。
第二互連構件140可對處理器晶片120的連接墊122及記憶體晶片125的連接墊129進行重佈線，並將處理器晶片120的連接墊122與記憶體晶片125的連接墊129電性連接至彼此。具有各種功能的數十至數百個連接墊122及連接墊129可藉由第二互連構件140而進行重佈線，且可端視各種功能經由連接端子170而實體地連接或電性地連接至外部源。第二互連構件140可包括：絕緣層141；重佈線層142，安置於絕緣層141上；以及介層窗143，穿透過絕緣層141且將各重佈線層142電性連接至彼此。在根據所述示例性實施例的扇出型半導體封裝100A中，第二互連構件140可包括單個層，且亦可包括多個層。
可使用絕緣材料作為絕緣層141的材料。在此種情形中，亦可使用例如感光成像介電（PID）樹脂等感光性絕緣材料作為所述絕緣材料。亦即，絕緣層141可為感光性絕緣層。在絕緣層141具有感光性質的情形中，絕緣層141可被形成為具有較小的厚度，且可更易於達成介層窗143的精細節距。絕緣層141可為包含絕緣樹脂及無機填料的感光性絕緣層。當絕緣層141為多個層時，絕緣層141的材料可彼此相同或者視需要亦可彼此不同。當絕緣層141為多個層時，絕緣層141可端視製程而彼此整合，以使得各絕緣層141之間的邊界可不為顯而易見的。
重佈線層142可實質上用於對連接墊122及/或記憶體晶片125的連接墊129進行重佈線。重佈線層142中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。重佈線層142可端視與其對應的層的設計而具有各種功能。舉例而言，重佈線層142可包括接地（GND）圖案、電源（PWR）圖案、訊號（S）圖案等。此處，訊號（S）圖案可包括除接地（GND）圖案、電源（PWR）圖案等之外的各種訊號，例如資料訊號等。另外，重佈線層142可包括介層窗墊、連接端子墊等。
若需要，則在被暴露的重佈線層142的表面上可形成表面處理層（圖中未示出）。所述表面處理層可藉由例如電解鍍金、無電鍍金、有機可焊性保護或無電鍍錫、無電鍍銀、無電鍍鎳/置換鍍金、直接浸金鍍敷、熱空氣焊料均塗等來形成，但並非僅限於此。
介層窗143可將在不同層上形成的重佈線層142、連接墊122及/或連接墊129等電性連接至彼此，從而在扇出型半導體封裝100A中形成電性路徑。介層窗143中的每一者的材料可為例如銅（Cu）、鋁（Al）、銀（Ag）、錫（Sn）、金（Au）、鎳（Ni）、鉛（Pb）、鈦（Ti）或其合金等導電材料。介層窗143中的每一者可被導電材料完全填充，抑或導電材料可沿所述介層窗中的每一者的壁形成。另外，介層窗143中的每一者可具有相關技術中習知的所有形狀，例如錐形形狀、柱形形狀等。
第一互連構件110的重佈線層112a及重佈線層112b的厚度可大於第二互連構件140的重佈線層142的厚度。由於第一互連構件110的厚度可與處理器晶片120的厚度相等或較處理器晶片120的厚度大，因此形成於第一互連構件110中的重佈線層112a及重佈線層112b可端視第一互連構件110的規模而被形成為大的。另一方面，第二互連構件140的重佈線層142可被形成為較第一互連構件110的重佈線層112a及重佈線層112b的大小相對小的大小，以達成第二互連構件140的薄化。
保護層150可另外被配置成保護第二互連構件140不受外部物理損壞或化學損壞。保護層150可具有開口151，開口151暴露出第二互連構件140的重佈線層142的至少某些部分。形成於保護層150中的開口151的數目可為數十個至數千個。
可使用具有較第二互連構件140的絕緣層141的彈性模數大的材料作為保護層150的材料。舉例而言，可使用不包含玻璃布（或玻璃織物）但包含無機填料及絕緣樹脂的味之素構成膜等作為保護層150的材料。當使用味之素構成膜等作為保護層150的材料時，保護層150中所包含的無機填料的重量百分比可大於第二互連構件140的絕緣層141中所包含的無機填料的重量百分比。在此種條件下，可靠性可得以提高。當使用味之素構成膜等作為保護層150的材料時，保護層150可為包含無機填料的非感光性絕緣層，且可有效地提高可靠性，但並非僅限於此。
凸塊下金屬層160可另外被配置成提高連接端子170的連接可靠性並提高扇出型半導體封裝100A的板級可靠性（board level reliability）。凸塊下金屬層160可連接至第二互連構件140的經由保護層150的開口151而被暴露出的重佈線層142。凸塊下金屬層160可藉由使用習知導電金屬（例如金屬）的習知金屬化方法而被形成於保護層150的開口151中，但並非僅限於此。
連接端子170可另外被配置成在外部對扇出型半導體封裝100A進行實體地或電性地連接。舉例而言，扇出型半導體封裝100A可經由連接端子170而安裝於電子裝置的主板上。連接端子170中的每一者可由例如焊料等導電材料形成。然而，此僅為實例，且連接端子170中的每一者的材料並不僅限於此。連接端子170中的每一者可為焊盤（land）、球、引腳等。連接端子170可被形成為多層式結構或單層式結構。當連接端子170被形成為多層式結構時，連接端子170可包含銅（Cu）柱及焊料。當連接端子170被形成為單層式結構時，連接端子170可包含錫-銀焊料或銅（Cu）。然而，此僅為實例，且連接端子170並非僅限於此。
連接端子170的數目、間隔、佈置等並不受特別限制，而是可由熟習此項技術者端視設計詳情而進行充分地修改。舉例而言，根據連接墊122及連接墊129的數目，連接端子170可被設置成數十至數千的數量；或者可被設置成數十至數千或更多的數量或者數十至數千或更少的數量。當連接端子170為焊料球時，連接端子170可覆蓋凸塊下金屬層160的延伸至保護層150的一個表面上的側表面，且連接可靠性可更為優異。
連接端子170中的至少一者可安置於扇出區中。所述扇出區為除安置有處理器晶片120的區之外的區。相較於扇入型封裝而言，所述扇出型封裝可具有優異的可靠性，所述扇出型封裝可實作多個輸入/輸出（I/O）端子，且可有利於3D互連。另外，相較於球柵陣列（ball grid array，BGA）封裝、焊盤柵陣列（land grid array，LGA）封裝等而言，所述扇出型封裝可被製造成具有減小的厚度，且可具有價格競爭力。
加強層183可另外被配置成抑制在扇出型半導體封裝100A中產生的翹曲。舉例而言，加強層183可抑制囊封體130的材料（例如熱固性樹脂膜）的硬化收縮，以抑制扇出型半導體封裝100A的翹曲。加強層183的彈性模數可較囊封體130的彈性模數相對大，且加強層183的熱膨脹係數可較囊封體130的熱膨脹係數（CTE）小。在此種情形中，翹曲抑制效果可特別優異。
加強層183可包含核心材料、無機填料及絕緣樹脂。舉例而言，加強層183可由未被包覆的覆銅疊層板（copper clad laminate，CCL）、預浸體等形成。在加強層183包含例如玻璃布（或玻璃織物）等核心材料的情形中，加強層183可被實作成具有相對大的彈性模數，且在加強層183包含無機填料的情形中，可藉由調整無機填料的含量來將加強層183實作成具有相對小的熱膨脹係數。加強層183可在硬化狀態下（c-階段）附裝至囊封體130。在此種情形中，囊封體130與加強層183之間的邊界面可具有近似線性形狀。同時，無機填料可為二氧化矽、氧化鋁等，且所述樹脂可為環氧樹脂等。然而，所述無機填料及所述樹脂並非僅限於此。
樹脂層184可另外被配置成安置於加強層183上。樹脂層184可由與囊封體130的材料相同或相似的材料（例如包含無機填料及絕緣樹脂但不包含核心材料的絕緣材料，亦即，味之素構成膜等）形成。在加強層183包含核心材料等的情形中，可能難以在加強層183中形成開口185，但在增加了樹脂層184的情形中，可易於形成開口185。開口185可穿透過囊封體130、加強層183及樹脂層184，且可暴露出第一互連構件110的重佈線層112b的至少某些部分。開口185可用作用於進行標記的開口。作為另外一種選擇，開口185可用作用於暴露出堆疊封裝結構中的墊的開口。作為另外一種選擇，開口185可用作用於安裝表面安裝技術（surface mounted technology，SMT）組件的開口。在安置有樹脂層184的情形中，可更易於抑制翹曲。
在使用包含無機填料及絕緣樹脂但不包含核心材料的絕緣材料（例如味之素構成膜等）作為保護層150及樹脂層184二者的材料的情形中，亦即，在使用具有相同組成物的材料作為保護層150及樹脂層184二者的材料的情形中，扇出型半導體封裝100A可因保護層150及樹脂層184而具有對稱效應，且扇出型半導體封裝100A的翹曲可因所述對稱效應而更有效地減小。
表面安裝技術（SMT）組件可另外地被配置成實質上安置於與位於保護層150上的連接端子170相同的水平高度上。表面安裝技術組件可為例如盤側電容器（land side capacitor，LSC）等被動組件，但並非僅限於此。表面安裝技術組件可經由第二互連構件140的重佈線層142而電性連接至處理器晶片120及/或記憶體晶片125。
儘管圖式中未示出，但若需要，則在第一互連構件110的貫穿孔110H的內壁上可進一步安置金屬層。亦即，處理器晶片120的側表面及/或記憶體晶片125的側表面亦可被所述金屬層環繞。自處理器晶片120及/或記憶體晶片125產生的熱量可經由所述金屬層而向扇出型半導體封裝100A之上或扇出型半導體封裝100A之下有效地消散，且可藉由所述金屬層而有效地阻擋電磁波。另外，例如電容器、電感器等單獨的被動式組件可與處理器晶片及記憶體晶片一起被囊封於貫穿孔110H中。
圖11是說明圖9所示扇出型半導體封裝的經修改實例的示意圖。
參照所述圖式，在根據經修改實例的扇出型半導體封裝100B中，第一互連構件110可包括：第一絕緣層111a，接觸第二互連構件140；第一重佈線層112a，接觸第二互連構件140且嵌於第一絕緣層111a中；第二重佈線層112b，安置於第一絕緣層111a的與第一絕緣層111a的嵌有第一重佈線層112a的一個表面相對的另一表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第三重佈線層112c，安置於第二絕緣層111b上。第一重佈線層112a、第二重佈線層112b及第三重佈線層112c可電性連接至連接墊122及連接墊129。同時，第一重佈線層112a與第二重佈線層112b以及第二重佈線層112b與第三重佈線層112c可經由分別穿透過第一絕緣層111a及第二絕緣層111b的第一介層窗113a及第二介層窗113b而電性連接至彼此。
由於在第一絕緣層111a中嵌有第一重佈線層112a，因此如上所述，第二互連構件140的絕緣層141的絕緣距離可為實質上恆定的。由於第一互連構件110可包括大數目的重佈線層112a、重佈線層112b及重佈線層112c，因此可簡化第二互連構件140。因此，可改良因在形成第二互連構件140的製程中出現的缺陷而導致的良率下降。第一重佈線層112a可凹陷至第一絕緣層111a中，進而使得在第一絕緣層111a的下表面與第一重佈線層112a的下表面之間具有台階。因此，當形成囊封體130時，可防止囊封體130的材料滲透而污染第一重佈線層112a的現象。
可在高於處理器晶片120的連接墊122的下表面的水平高度上安置第一互連構件110的第一重佈線層112a的下表面。另外，第二互連構件140的重佈線層142與第一互連構件110的第一重佈線層112a之間的距離可大於第二互連構件140的重佈線層142與處理器晶片120的連接墊122之間的距離。此處，第一重佈線層112a可凹陷至第一絕緣層111a中。可在處理器晶片120的主動表面與被動表面之間的水平高度上安置第一互連構件110的第二重佈線層112b。第一互連構件110可被形成為具有與處理器晶片120的厚度對應的厚度。因此，可在處理器晶片120的主動表面與被動表面之間的水平高度上安置形成於第一互連構件110中的第二重佈線層112b。
第一互連構件110的重佈線層112a、重佈線層112b及重佈線層112c的厚度可較第二互連構件140的重佈線層142的厚度大。由於第一互連構件110的厚度可與處理器晶片120的厚度相等或較處理器晶片120的厚度大，因此端視第一互連構件110的規模而定，重佈線層112a、重佈線層112b及重佈線層112c可被形成為大的。另一方面，第二互連構件140的重佈線層142可被形成為相對小的以達成薄化。其他內容與上述內容重複，且因此不再對其予以贅述。
圖12是說明圖9所示扇出型半導體封裝的另一經修改實例的示意性剖視圖。
參照所述圖式，在根據另一經修改實例的扇出型半導體封裝100C中，第一互連構件110可包括：第一絕緣層111a；第一重佈線層112a及第二重佈線層112b，分別安置於第一絕緣層111a的相對的表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第一重佈線層112a；第三重佈線層112c，安置於第二絕緣層111b上；第三絕緣層111c，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第四重佈線層112d，安置於第三絕緣層111c上。第一重佈線層112a、第二重佈線層112b、第三重佈線層112c及第四重佈線層112d可電性連接至連接墊122及連接墊129。由於第一互連構件110可包括較大數目的重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d，因此可進一步簡化第二互連構件140。因此，可改良因在形成第二互連構件140的製程中出現的缺陷而導致的良率下降。同時，第一重佈線層112a、第二重佈線層112b、第三重佈線層112c及第四重佈線層112d可藉由分別穿透過第一絕緣層111a、第二絕緣層111b及第三絕緣層111c的第一介層窗113a、第二介層窗113b及第三介層窗113c而電性連接至彼此。
第一絕緣層111a的厚度可較第二絕緣層111b及第三絕緣層111c的厚度大。第一絕緣層111a可為相對厚的以維持剛性，且可引入第二絕緣層111b及第三絕緣層111c以形成較大數目的重佈線層112c及重佈線層112d。第一絕緣層111a包含的絕緣材料可與第二絕緣層111b及第三絕緣層111c包含的絕緣材料不同。舉例而言，第一絕緣層111a可為例如包含核心材料、無機填料及絕緣樹脂的預浸體，且第二絕緣層111b及第三絕緣層111c可為包含無機填料及絕緣樹脂的味之素構成膜或感光性絕緣膜。然而，第一絕緣層111a的材料以及第二絕緣層111b及第三絕緣層111c的材料並非僅限於此。
可在低於處理器晶片120的連接墊122的下表面的水平高度上安置第一互連構件110的第三重佈線層112c的下表面。另外，第二互連構件140的重佈線層142與第一互連構件110的第三重佈線層112c之間的距離可小於第二互連構件140的重佈線層142與處理器晶片120的連接墊122之間的距離。此處，第三重佈線層112c可以突出形式安置於第二絕緣層111b上，從而與第二互連構件140接觸。可在處理器晶片120的主動表面與被動表面之間的水平高度上安置第一互連構件110的第一重佈線層112a及第二重佈線層112b。第一互連構件110可被形成為具有與處理器晶片120的厚度對應的厚度。因此，可在處理器晶片120的主動表面與被動表面之間的水平高度上安置形成於第一互連構件110中的第一重佈線層112a及第二重佈線層112b。
第一互連構件110的重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d的厚度可大於第二互連構件140的重佈線層142的厚度。由於第一互連構件110的厚度可與處理器晶片120的厚度相等或較處理器晶片120的厚度大，因此重佈線層112a、重佈線層112b、重佈線層112c及重佈線層112d亦可被形成為具有大的大小。另一方面，第二互連構件140的重佈線層142可被形成為相對小的以達成薄化。其他內容與上述內容重複，且因此不再對其予以贅述。
圖13是說明扇出型半導體封裝的另一實例的示意性剖視圖。
圖14是沿圖13所示扇出型半導體封裝的線II-II'截取的示意性平面圖。
參照所述圖式，根據本發明中另一示例性實施例的扇出型半導體封裝100D可包括：第一互連構件110，具有多個貫穿孔110Ha及貫穿孔110Hb；處理器晶片120，安置於第一互連構件110的第一貫穿孔110Ha中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊122；記憶體晶片125，安置於第一互連構件110的第二貫穿孔110Hb中，具有主動表面，且具有堆疊有多個晶粒126及晶粒127的形式，所述主動表面上安置有連接墊129；囊封體130，囊封第一互連構件110的至少某些部分、記憶體晶片125的至少某些部分以及處理器晶片120的至少某些部分；第二互連構件140，安置於第一互連構件110上以及記憶體晶片125的主動表面及處理器晶片120的主動表面上；保護層150，安置於第二互連構件140上；凸塊下金屬層160，形成於保護層150的開口151中；連接端子170，形成於凸塊下金屬層160上；加強層183，安置於囊封體130上；樹脂層184，安置於加強層183上；開口185，穿透過樹脂層184、加強層183及囊封體130且暴露出第一互連構件110的重佈線層112b的至少某些部分；以及表面安裝技術（SMT）組件，表面安裝於保護層150上。第一互連構件110及第二互連構件140可分別包括電性連接至處理器晶片120的連接墊122及記憶體晶片125的連接墊129的重佈線層112a與重佈線層112b以及重佈線層142，且處理器晶片120的連接墊122與記憶體晶片125的連接墊129可藉由第二互連構件140的重佈線層142而電性連接至彼此。如上所述，在根據另一示例性實施例的扇出型半導體封裝100D中，第一互連構件110可包括所述多個貫穿孔110Ha及貫穿孔110Hb，且處理器晶片120及記憶體晶片125可分別安置於貫穿孔110Ha及貫穿孔110Hb中。在此種情形中，可更有效地控制扇出型半導體封裝100D的機械應力及/或熱應力。其他內容與上述內容重複，且因此不再對其予以贅述。
圖15是說明圖13所示扇出型半導體封裝的經修改實例的示意圖。
參照所述圖式，其亦在第一互連構件110包括多個貫穿孔110Ha及貫穿孔110Hb且處理器晶片120及記憶體晶片125分別安置於貫穿孔110Ha及貫穿孔110Hb中的情形中，如在根據經修改實例的扇出型半導體封裝100E中一樣，第一互連構件110可包括：第一絕緣層111a，接觸第二互連構件140；第一重佈線層112a，接觸第二互連構件140且嵌於第一絕緣層111a中；第二重佈線層112b，安置於第一絕緣層111a的與第一絕緣層111a的嵌有第一重佈線層112a的一個表面相對的另一表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第三重佈線層112c，安置於第二絕緣層111b上。第一重佈線層112a與第二重佈線層112b以及第二重佈線層112b與第三重佈線層112c可藉由分別穿透過第一絕緣層111a及第二絕緣層111b的第一介層窗113a及第二介層窗113b而電性連接至彼此。其他內容與上述內容重複，且因此不再對其予以贅述。
圖16是說明圖13所示扇出型半導體封裝的另一經修改實例的示意圖。
參照所述圖式，其亦在第一互連構件110包括多個貫穿孔110Ha及貫穿孔110Hb且處理器晶片120及記憶體晶片125分別安置於貫穿孔110Ha及貫穿孔110Hb中的情形中，如在根據另一經修改實例的扇出型半導體封裝100F中一樣，第一互連構件110可包括：第一絕緣層111a；第一重佈線層112a及第二重佈線層112b，分別安置於第一絕緣層111a的相對的表面上；第二絕緣層111b，安置於第一絕緣層111a上且覆蓋第一重佈線層112a；第三重佈線層112c，安置於第二絕緣層111b上；第三絕緣層111c，安置於第一絕緣層111a上且覆蓋第二重佈線層112b；以及第四重佈線層112d，安置於第三絕緣層111c上。第一重佈線層112a、第二重佈線層112b、第三重佈線層112c及第四重佈線層112d可藉由分別穿透過第一絕緣層111a、第二絕緣層111b及第三絕緣層111c的第一介層窗113a、第二介層窗113b及第三介層窗113c電性連接至彼此。其他內容與上述內容重複，且因此不再對其予以贅述。
如上所述，根據本發明中的示例性實施例，可提供一種能夠執行各種功能、被薄化的且具有優異的安裝可靠性的扇出型半導體封裝。
儘管以上已示出並闡述了各示例性實施例，然而對於熟習此項技術者而言將顯而易見，在不背離由隨附申請專利範圍所界定的本發明的範圍的條件下，可作出修改及變型。
100‧‧‧半導體封裝
100A、100B、100C、100D、100E、100F、2100‧‧‧扇出型半導體封裝
110‧‧‧第一互連構件
110H‧‧‧貫穿孔
110Ha‧‧‧貫穿孔/第一貫穿孔
110Hb‧‧‧貫穿孔/第二貫穿孔
111、141、2141、2241‧‧‧絕緣層
111a‧‧‧第一絕緣層
111b‧‧‧第二絕緣層
111c‧‧‧第三絕緣層
112a‧‧‧重佈線層/第一重佈線層
112b‧‧‧重佈線層/第二重佈線層
112c‧‧‧重佈線層/第三重佈線層
112d‧‧‧重佈線層/第四重佈線層
113、143、2143、2243‧‧‧介層窗
113a‧‧‧第一介層窗
113b‧‧‧第二介層窗
113c‧‧‧第三介層窗
120‧‧‧處理器晶片
121、1101、2121、2221‧‧‧主體
122、129、2122、2222‧‧‧連接墊
123‧‧‧保護層
125‧‧‧記憶體晶片
126‧‧‧晶粒/基礎晶粒
127‧‧‧晶粒/動態隨機存取記憶體
128a‧‧‧貫穿電極
128b‧‧‧凸塊
130、2130‧‧‧囊封體
140‧‧‧第二互連構件
142、2142‧‧‧重佈線層
150、2150、2223、2250‧‧‧保護層
151、185、2251‧‧‧開口
160、2160、2260‧‧‧凸塊下金屬層
170‧‧‧連接端子
183‧‧‧加強層
184‧‧‧樹脂層
1000‧‧‧電子裝置
1010‧‧‧母板
1020‧‧‧晶片相關組件
1030‧‧‧網路相關組件
1040‧‧‧其他組件
1050、1130‧‧‧照相機模組
1060‧‧‧天線
1070‧‧‧顯示器裝置
1080‧‧‧電池
1090‧‧‧訊號線
1100‧‧‧智慧型電話
1110、2500‧‧‧主板
1120‧‧‧電子組件
2120、2220‧‧‧半導體晶片
2140、2240‧‧‧互連構件
2170、2270‧‧‧焊料球
2200‧‧‧扇入型半導體封裝
2242‧‧‧配線圖案
2243h‧‧‧介層窗孔
2280‧‧‧底部填充樹脂
2290‧‧‧模製材料
2301、2302‧‧‧插板基板
I-I'、II-II'‧‧‧線
P‧‧‧表面處理層
藉由結合附圖閱讀以下詳細說明，將更清晰地理解本發明的以上及其他態樣、特徵、及優點，在附圖中： 圖1是說明電子裝置系統的實例的示意性方塊圖。 圖2是說明電子裝置的實例的示意性立體圖。 圖3A及圖3B是說明在被封裝之前及在被封裝之後的扇入型半導體封裝的狀態的示意性剖視圖。 圖4是說明扇入型半導體封裝的封裝製程的示意性剖視圖。 圖5是說明扇入型半導體封裝安裝於插板基板上且最終安裝於電子裝置的主板上的情形的示意性剖視圖。 圖6是說明扇入型半導體封裝嵌於插板基板中且最終安裝於電子裝置的主板上的情形的示意性剖視圖。 圖7是說明扇出型半導體封裝的示意性剖視圖。 圖8是說明扇出型半導體封裝安裝於電子裝置的主板上的情形的示意性剖視圖。 圖9是說明扇出型半導體封裝的實例的示意性剖視圖。 圖10是沿圖9所示的扇出型半導體封裝的線I-I'截取的示意性平面圖。 圖11是說明圖9所示扇出型半導體封裝的經修改實例的示意圖。 圖12是說明圖9所示扇出型半導體封裝的另一經修改實例的示意性剖視圖。 圖13是說明扇出型半導體封裝的另一實例的示意性剖視圖。 圖14是沿圖13所示扇出型半導體封裝的線II-II'截取的示意性平面圖。 圖15是說明圖13所示扇出型半導體封裝的經修改實例的示意圖。 圖16是說明圖13所示扇出型半導體封裝的另一經修改實例的示意圖。

Claims (16)

  1. 一種扇出型半導體封裝，包括： 第一互連構件，具有貫穿孔； 處理器晶片，安置於所述第一互連構件的所述貫穿孔中且具有主動表面及與所述主動表面相對的被動表面，所述主動表面上安置有連接墊； 記憶體晶片，安置於所述第一互連構件的所述貫穿孔中，具有主動表面且包括彼此堆疊的多個晶粒，所述主動表面上安置有連接墊； 囊封體，囊封所述第一互連構件的至少某些部分、所述記憶體晶片的至少某些部分及所述處理器晶片的至少某些部分；以及 第二互連構件，安置於所述第一互連構件上、所述記憶體晶片的所述主動表面上及所述處理器晶片的所述主動表面上， 其中所述第一互連構件及所述第二互連構件分別包括電性連接至所述處理器晶片的所述連接墊及所述記憶體晶片的所述連接墊的重佈線層，且 所述處理器晶片的所述連接墊與所述記憶體晶片的所述連接墊藉由所述第二互連構件的所述重佈線層而電性連接至彼此。
  2. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述處理器晶片包括應用處理器，且所述記憶體晶片包括高頻寬記憶體及寬輸入/輸出中的至少一者。
  3. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述多個晶粒藉由分別穿透過所述多個晶粒的多個貫穿電極及將所述多個貫穿電極連接至彼此的多個凸塊而電性連接至彼此。
  4. 如申請專利範圍第3項所述的扇出型半導體封裝，其中所述囊封體填充所述多個晶粒之間的空間的至少某些部分。
  5. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述貫穿孔的數目是多個，且所述處理器晶片及所述記憶體晶片分別安置於多個所述貫穿孔中的不同貫穿孔中。
  6. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一互連構件包括第一絕緣層、第一重佈線層及第二重佈線層，所述第一重佈線層接觸所述第二互連構件且嵌於所述第一絕緣層中，所述第二重佈線層安置於所述第一絕緣層的與所述第一絕緣層的嵌有所述第一重佈線層的一個表面相對的另一表面上。
  7. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第一互連構件更包括安置於所述第一絕緣層上且覆蓋所述第二重佈線層的第二絕緣層及安置於所述第二絕緣層上的第三重佈線層。
  8. 如申請專利範圍第7項所述的扇出型半導體封裝，其中所述第二重佈線層安置於所述處理器晶片的所述主動表面與所述被動表面之間的水平高度上。
  9. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第二互連構件的所述重佈線層與所述第一重佈線層之間的距離大於所述第二互連構件的所述重佈線層與所述處理器晶片的所述連接墊之間的距離。
  10. 如申請專利範圍第6項所述的扇出型半導體封裝，其中所述第一重佈線層的厚度較所述第二互連構件的所述重佈線層的厚度大。
  11. 如申請專利範圍第1項所述的扇出型半導體封裝，其中所述第一互連構件包括第一絕緣層、第一重佈線層、第二重佈線層、第二絕緣層以及第三重佈線層，所述第一重佈線層及所述第二重佈線層分別安置於所述第一絕緣層的相對的表面上，所述第二絕緣層安置於所述第一絕緣層上且覆蓋所述第一重佈線層，所述第三重佈線層安置於所述第二絕緣層上。
  12. 如申請專利範圍第11項所述的扇出型半導體封裝，其中所述第一互連構件更包括安置於所述第一絕緣層上且覆蓋所述第二重佈線層的第三絕緣層以及安置於所述第三絕緣層上的第四重佈線層。
  13. 如申請專利範圍第11項所述的扇出型半導體封裝，其中所述第一絕緣層的厚度較所述第二絕緣層的厚度大。
  14. 如申請專利範圍第11項所述的扇出型半導體封裝，其中所述第三重佈線層的厚度較所述第二互連構件的所述重佈線層的厚度大。
  15. 如申請專利範圍第11項所述的扇出型半導體封裝，其中所述第一重佈線層安置於所述處理器晶片的所述主動表面與所述被動表面之間的水平高度上。
  16. 如申請專利範圍第1項所述的扇出型半導體封裝，更包括： 加強層，安置於所述囊封體上且包含核心材料、無機填料及絕緣樹脂； 樹脂層，安置於所述加強層上且包含無機填料及絕緣樹脂； 以及 開口，穿透過所述樹脂層、所述加強層及所述囊封體且暴露出所述第一互連構件的所述重佈線層的至少某些部分。
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