TW201806079A - 半導體製造方法 - Google Patents

半導體製造方法 Download PDF

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TW201806079A
TW201806079A TW106104038A TW106104038A TW201806079A TW 201806079 A TW201806079 A TW 201806079A TW 106104038 A TW106104038 A TW 106104038A TW 106104038 A TW106104038 A TW 106104038A TW 201806079 A TW201806079 A TW 201806079A
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semiconductor wafer
metal film
nozzles
semiconductor
cleaner
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TWI673828B (zh
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右田達夫
庄子史人
小木曽浩二
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東芝記憶體股份有限公司
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    • HELECTRICITY
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    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B08CLEANING
    • B08BCLEANING IN GENERAL; PREVENTION OF FOULING IN GENERAL
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/67005Apparatus not specifically provided for elsewhere
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    • H01L21/67017Apparatus for fluid treatment
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    • H01L21/67051Apparatus for fluid treatment for cleaning followed by drying, rinsing, stripping, blasting or the like for wet cleaning or washing using mainly spraying means, e.g. nozzles
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    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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    • H01L2224/732Location after the connecting process
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Abstract

本發明之實施形態提供一種不會產生漏鍍之不良之半導體製造方法。 實施形態之半導體製造方法具備如下步驟:於半導體晶圓之一主面上,利用第1鍍覆處理形成第1金屬膜;一面自與半導體晶圓之一主面隔開配置之洗淨器朝一主面上噴射洗淨液,一面使洗淨器及半導體晶圓之至少一者旋轉,而洗淨第1金屬膜之表面;及於第1金屬膜上,利用第2鍍覆處理形成第2金屬膜。於洗淨器,設置有沿一方向配置之複數個噴嘴。複數個噴嘴係自與半導體晶圓之中心位置對向之位置偏離配置,且於半導體晶圓之周緣部側較半導體晶圓之中心側配置得更多。配置於半導體晶圓之周緣部側之噴嘴係對自一方向傾斜之方向之第1範圍內噴射洗淨液,配置於半導體晶圓之中心側之噴嘴中之1者對包含半導體晶圓之中心位置之第2範圍內噴射洗淨液。

Description

半導體製造方法
本發明係關於一種半導體製造方法。
已知有將形成有半導體元件或積體電路之晶片於基板上積層多段,而減小半導體裝置之佔有面積之技術。有為謀求所積層之各晶片間之電性導通,而形成被稱為TSV(Through Silicon Via:矽穿孔)之貫通電極之情形。 對導通孔填埋金屬一般係藉由電場鍍覆等鍍覆處理進行。於貫通電極之鍍覆處理中,有為提高導電性或耐久性等,而積層複數層金屬之情形。該情形時,重複進行如下處理:於浸沒於鍍覆液中形成一層量之金屬膜之後,以水洗淨金屬膜之表面去除鍍覆液後,浸沒於下一鍍覆液中形成新的金屬膜。 然而,若以水洗淨金屬膜之表面,會於金屬膜之表面形成氧化膜。因此,必須於以某種步驟去除氧化膜之後,形成下一金屬膜,但根據構成金屬膜之金屬材料不同,而有難以去除氧化膜之情形。該情形時,變成於氧化膜之上,利用鍍覆處理形成新的金屬膜,但由於氧化膜與金屬膜接觸性欠佳,故有產生漏鍍之不良之虞。
本發明之實施形態提供一種不會產生漏鍍之不良之半導體製造方法。 本發明之一態樣之半導體製造方法具備如下步驟:於半導體晶圓之一主面上,利用第1鍍覆處理形成第1金屬膜; 一面自與上述半導體晶圓之上述一主面隔開配置之洗淨器朝上述一主面上噴射洗淨液,一面使上述洗淨器及上述半導體晶圓之至少一者旋轉,而洗淨上述第1金屬膜之表面;及 於上述第1金屬膜上,利用第2鍍覆處理形成第2金屬膜;且 於上述洗淨器,設置有沿一方向配置之複數個噴嘴; 上述複數個噴嘴係自與上述半導體晶圓之中心位置對向之位置偏離配置,且於上述半導體晶圓之周緣部側較上述半導體晶圓之中心側配置得更多; 配置於上述半導體晶圓之周緣部側之噴嘴係對自上述一方向傾斜之方向之第1範圍內噴射上述洗淨液; 配置於上述半導體晶圓之中心側之噴嘴中之1者對包含上述半導體晶圓之中心位置之第2範圍內噴射上述洗淨液。
以下,對本發明之實施形態進行詳細說明。本實施形態係利用鍍覆處理而形成於半導體晶圓上形成之貫通電極或凸塊電極、接觸件等各種電極者。更具體言之,本實施形態係考量利用鍍覆處理積層複數層金屬膜而形成各種電極。於利用鍍覆處理積層複數層金屬膜之情形時,重複進行如下處理:於利用鍍覆處理形成一層之金屬膜之後,進行水洗金屬膜之表面之洗淨步驟,其後利用鍍覆處理形成下一層金屬膜。 圖1係於上述洗淨步驟使用之洗淨裝置1之剖視圖。於圖1之洗淨裝置1中,將半導體晶圓2以其洗淨對象面2a朝下而固定。洗淨對象面2a係形成貫通電極或凸塊電極等之一主面。 半導體晶圓2由支持機構自圖1之正背方向予以支持,但於圖1中省略支持機構之圖示。於半導體晶圓2之上方配置有未圖示之上蓋,於洗淨半導體晶圓2時,將半導體晶圓2密封於圖示之洗淨腔室4內,從而防止水飛濺至洗淨裝置1之外側。 於洗淨對象面2a之下方,配置有於一方向延伸之線狀之洗淨器5。於半導體晶圓2與洗淨器5之間,設置有間隙。於洗淨器5,沿一方向設置有複數個噴嘴6。各噴嘴6朝上方噴射洗淨液(例如水),而洗淨對向配置之半導體晶圓2之洗淨對象面2a。 於洗淨器5之長度方向(一方向)之中央部,安裝有旋轉軸7與旋轉驅動部8,洗淨器5被設為繞旋轉軸7旋動自如。即,洗淨器5以與半導體晶圓2之洗淨對象面2a維持固定之距離之狀態,沿洗淨對象面2a旋轉。 將半導體晶圓2以其中心位置之法線2b與洗淨器5之旋轉軸7大致一致之方式定位並固定。藉此,洗淨器5繞半導體晶圓2之中心位置旋轉。洗淨器5一面繞旋轉軸7旋轉,一面自各噴嘴6朝半導體晶圓2之洗淨對象面2a噴射水,而對整個洗淨對象面2a進行洗淨。另,旋轉軸7係只要洗淨器5可繞半導體晶圓2之中心位置相對地旋轉即可,可將洗淨器5固定而使半導體晶圓2旋轉,或亦可使洗淨器5與半導體晶圓2兩者旋轉。 於洗淨器5,安裝有用以對噴嘴6供給水之未圖示之供水管、或用以排出洗淨後之水之未圖示之排出管、對旋轉驅動部8進行電源供給之未圖示之電源供給電纜等。 洗淨器5之長度方向之全長雖設計成略小於半導體晶圓2之直徑,但如後述,因各噴嘴6對特定之角度範圍噴射水量均勻之水,故可洗淨半導體晶圓2之整個洗淨對象面2a。 本實施形態之洗淨器5之特徵在於,可以固定之水量均勻地洗淨半導體晶圓2之整個洗淨對象面2a。該特徵係藉由洗淨器5之噴嘴6之配置與水自噴嘴6之噴射方向而實現。另,自各噴嘴6噴射之每單位時間之水量可進行調整,但水量之調整假定為以所有噴嘴6為對象進行,並不意圖針對各噴嘴6之每一者而個別地調整水量。 圖2係顯示本實施形態之洗淨器5之噴嘴6之配置之圖,圖3係顯示自圖2之各噴嘴6噴射之水之噴射範圍之圖。於噴嘴6之上表面、即與半導體晶圓2之洗淨對象面2a對向之面,以不規則之間隔配置有複數個噴嘴6。更具體言之,複數個噴嘴6避開與半導體晶圓2之中心位置對向之位置而配置。於圖2及圖3之例中,以配置於洗淨器5之長度方向之中央之旋轉軸7之軸中心為基準點rp,於一側LS與另一側RS各配置相同數量之3個噴嘴6。一側LS之3個中之2個噴嘴6配置於半導體晶圓2之周緣側,剩餘之1個噴嘴6配置於半導體晶圓2之中心側。同樣,另一側RS之3個中之2個噴嘴6配置於半導體晶圓2之周緣側,剩餘之1個噴嘴6配置於半導體晶圓2之中心側。 此處,所謂基準點rp係洗淨器5之旋轉軸7中心,理想為與通過半導體晶圓2之中心位置之法線2b交叉之點。 如圖3所示,自基準點rp配置於一側LS之3個噴嘴6之中,半導體晶圓2之周緣側之2個朝自洗淨器5之長度方向(一方向)傾斜之方向之第1範圍r1內噴射水,半導體晶圓2之中心側之1個朝洗淨器5之長度方向之第2範圍r2內噴射水。同樣,自基準點rp配置於另一側RS之3個噴嘴6之中,半導體晶圓2之周緣側之2個朝自洗淨器5之長度方向傾斜之方向之第1範圍r1內噴射水,半導體晶圓2之中心側之1個朝洗淨器5之長度方向之第2範圍r2內噴射水。且,於2個第2範圍r2中之至少一個第2範圍r2內包含基準點rp。如此,各噴嘴6對半導體晶圓2之洗淨對象面2a呈大致扇狀地噴射水。圖3所示之6個矩形範圍r1、r2顯示水自各噴嘴6之噴射範圍之概略。 又,於基準點rp之一側LS與另一側RS之任一側,水自周緣側之各2個噴嘴6之噴射方向皆相互平行。即,周緣側之各2個噴嘴6朝自一方向傾斜相同角度之方向噴射水。藉此,來自各噴嘴6之水彼此不會衝突,而可使飛濺至半導體晶圓2之洗淨對象面2a上之水量無論任何部位皆為均勻。若來自複數個噴嘴6之水彼此衝突,則水會不規則地飛濺至晶圓之洗淨對象面2a上,依部位不同而產生之水量不均亦變大,但於本實施形態中,可使水之飛濺範圍內之水量為均勻。 再者,於基準點rp之一側LS與另一側RS之任一側,水自半導體晶圓2之中心側之各1個噴嘴6之噴射範圍皆略微重合。又,於基準點rp之一側LS與另一側RS之任一側,水自中心側之1個噴嘴6之噴射範圍皆與水自周緣側之2個噴嘴6之噴射範圍略微重合。藉此,可極力抑制自複數個噴嘴6噴射出之水彼此重合之範圍,而抑制附著於半導體晶圓2之洗淨對象面2a之水量依部位不同而產生之不均。 圖4係顯示一比較例之洗淨器5之噴嘴6之配置之圖,圖5係顯示自圖4之各噴嘴6噴射之水之噴射範圍之圖。於圖4之例中,於半導體晶圓2之中心側較周緣側配置有更多噴嘴6。又,自位於洗淨器5之長度方向之中央之基準點rp偏向另一側RS配置噴嘴6。再者,如圖5所示,各噴嘴6對自洗淨器5之長度方向傾斜之方向之特定範圍r3內噴射水。 藉此,於一比較例之洗淨器5中,半導體晶圓2之洗淨對象面2a之中央側之水量變得比周緣側多。又,因來自各噴嘴6之水之噴射方向為共通,且各噴嘴6於洗淨器5之長度方向上不規則地配置,故半導體晶圓2之洗淨對象面2a內之水量依部位而大幅度變動。因此,於水量較多之洗淨對象面2a之中心附近若有應進行鍍覆處理之通孔存在,會於該通孔內之鍍覆金屬膜之表面形成較厚之氧化膜,因而導致與隨後利用鍍覆處理形成之新金屬膜之接觸性變差。 如一比較例般,只要於半導體晶圓2之中心側配置更多噴嘴6,就難以使半導體晶圓2之洗淨對象面2a上之水量無論任何部位皆均勻。因此,於本實施形態中,於半導體晶圓2之中心側,儘量不配置噴嘴6。又,使自各噴嘴6噴射之水彼此不衝突。 使用本實施形態之洗淨裝置1,能以適度之水量且無論任何部位皆均勻之水量,對利用鍍覆處理形成之金屬膜之整個表面進行洗淨,而消除因於金屬膜之表面局部附著過多之水分、而於金屬膜之表面形成較厚之氧化膜之虞。 因此,即使於利用鍍覆處理形成複數層金屬膜之情形時,於形成各金屬膜之後,亦可將形成於最上面之金屬膜之表面適度地洗淨至不會形成較厚之氧化膜之程度,從而與利用下一步驟之鍍覆處理形成之金屬膜之密接性變佳。因此,根據本實施形態,可高品質且可靠性良好地製造積層有複數層金屬膜之貫通電極或凸塊電極、接觸電極等。 圖6係顯示部分使用本實施形態之半導體製造方法製造之半導體裝置21之概略構成之剖視圖。圖6具備積層有複數個半導體晶片22之晶片積層體23、貫通晶片積層體23之貫通電極24、供晶片積層體23安裝之安裝基板25、及支持晶片積層體23之支持基板26。安裝基板25與支持基板26對向配置,於安裝基板25與支持基板26之間配置有晶片積層體23,支持基板26與晶片積層體23之周圍被樹脂封裝構件27覆蓋。 半導體晶片22例如為NAND(NOT-AND,反及)快閃型記憶體晶片,但半導體晶片22之具體種類不拘。晶片積層體23介隔突出電極28而覆晶安裝於安裝基板25上。於安裝基板25之背面側,配置有突出電極29。於所積層之貫通電極24之下方,配置有介面晶片30。 貫通電極24與突出電極28、29之至少一者可使用本實施形態之半導體製造方法,以鍍覆處理製作。 圖7係圖6所示之貫通電極24之詳細剖視圖,顯示設置於圖6之晶片積層體23中之一個半導體晶片22內之貫通電極24之剖面構造。 半導體晶片22具有半導體基板31、配置於半導體基板31之上之層間絕緣膜32、及配置於層間絕緣膜32之上之保護膜33。於半導體晶片22為NAND快閃型記憶體晶片之情形時,將記憶胞及周邊電路於層間絕緣膜32內分離配置。 貫通電極24以貫通半導體基板31之方式形成。於層間絕緣膜32內,配置有多層配線層34。多層配線層34自半導體基板31側朝向上方而具有最下層連接配線層35、下層連接配線層36、上層連接配線層37及最上層連接配線層38。 最下層連接配線層35為積層構造,自半導體基板31側朝向上方,依序積層有第1導電層39、第2導電層40及第3導電層41。第3導電層41之上表面與覆蓋絕緣層42相接,第3導電層41與下層連接配線層36係藉由貫通覆蓋絕緣層42與層間絕緣膜32之複數個接觸件43而電性連接。 同樣,下層連接配線層36與上層連接配線層37係藉由貫通層間絕緣膜32之複數個接觸件44而電性連接。又,上層連接配線層37與最上層連接配線層38係藉由貫通層間絕緣膜32之複數個接觸件45而電性連接。最上層連接配線層38與貫通保護膜33之表面電極46相接。 貫通電極24配置於貫通半導體基板31之導通孔之內側部分。導通孔之側壁被側壁絕緣膜47覆蓋。於側壁絕緣膜47之上,利用上述鍍覆處理,形成有金屬膜。藉由進行所謂保形鍍覆作為鍍覆處理,可使金屬膜自導通孔之底面側與側壁側之兩者成長,而可於短時間內以金屬膜填埋導通孔內。此時,雖亦有於導通孔之中央部,形成於積層方向延伸之接縫狀之空間部,但利用保形鍍覆,可以金屬膜確實地封閉空間部之上部側,而即使於導通孔之內部殘留有空間部,亦不會成為電性特性上之障礙。 導通孔內之金屬膜之材料例如為Ni。貫通電極24之上部與第3導電層41相接。於貫通電極24之與第3導電層41之接觸部附近,可利用鍍覆處理形成例如銅之金屬膜,且於該銅之金屬膜之上,利用鍍覆處理形成例如錫之金屬膜。 如此,於利用鍍覆處理使貫通電極24為例如鎳、銅及錫之積層構造之情形時,於形成各金屬膜之後,必須使用上述洗淨裝置1,洗淨去除附著於金屬膜之表面之鍍覆液。此時,根據本實施形態之半導體製造方法,消除來自洗淨器5之水過多地附著於金屬膜之表面之虞,而不會於金屬膜之表面形成較厚之氧化膜。因此,可提高構成貫通電極24之金屬膜彼此之接觸性。 另,於製造半導體裝置21之情形時,於形成貫通電極24之後,存在進行熱處理之步驟。由於該熱處理,而配置於貫通電極24內之空間部與側壁絕緣膜47之間之金屬膜產生裂縫,從而有貫通電極24之導電性能下降等,而貫通電極24之可靠性下降之虞。為防止裂縫,只要將金屬膜之膜厚增大即可,但為使貫通電極24用之導通孔孔徑微細化,不可過於增大。 本發明者對金屬膜之膜厚相對於貫通電極24之通孔孔徑之比率進行各種改變,研究不產生裂縫之最小比率,結果發現其為15.6%。另,該數字係將形成有貫通電極24之半導體裝置21於封裝後之狀態下驗證之值。若將比率設為15.6%以上,則即使進行熱處理,亦不會於金屬膜產生裂縫,而貫通電極24之可靠性提高。 如此,於本實施形態中,於利用鍍覆處理積層複數層金屬膜之情形時,每當於半導體晶圓2上形成各金屬膜時,均以均勻且適度之水量洗淨半導體晶圓2之整個洗淨對象面2a,因此,於進行下一鍍覆步驟前,不會於金屬膜之表面形成較厚之氧化膜,而金屬膜彼此之接觸性變佳。藉此,於例如於導通孔內積層複數層金屬膜之情形時,可進行所謂保形鍍覆,而可於短時間內進行複數層金屬膜之積層。 更具體言之,於本實施形態中,具備於半導體晶圓2之一方向上延伸,且長度方向之全長小於半導體晶圓2之直徑之線狀之洗淨器5,且藉由將洗淨器5之噴嘴6之配置如圖3設置,而可以適度且均勻之水量洗淨半導體晶圓2之整個洗淨對象面。 又,於本實施形態中,於導通孔內形成金屬膜之情形時,將金屬膜之厚度相對於導通孔之孔徑之比率設為15.6%以上,因此,可防止金屬膜產生裂縫之不良情形。 已對本發明之若干實施形態進行了說明,但該等實施形態係作為例子而提出,並不意圖限定發明之範圍。該等新穎之實施形態可以其他各種形態實施,可於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變形包含於發明之範圍或主旨中,且包含於申請專利範圍所記載之發明及其均等之範圍內。 [相關申請案] 本申請案享有以日本專利申請案2016-50105號(申請日:2016年3月14日)為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
1‧‧‧洗淨裝置
2‧‧‧半導體晶圓
2a‧‧‧洗淨對象面
2b‧‧‧法線
4‧‧‧洗淨腔室
5‧‧‧洗淨器
6‧‧‧噴嘴
7‧‧‧旋轉軸
8‧‧‧旋轉驅動部
21‧‧‧半導體裝置
22‧‧‧半導體晶片
23‧‧‧晶片積層體
24‧‧‧貫通電極
25‧‧‧安裝基板
26‧‧‧支持基板
27‧‧‧樹脂封裝構件
28‧‧‧突出電極
29‧‧‧突出電極
30‧‧‧介面晶片
31‧‧‧半導體基板
32‧‧‧層間絕緣膜
33‧‧‧保護膜
34‧‧‧多層配線層
35‧‧‧最下層連接配線層
36‧‧‧下層連接配線層
37‧‧‧上層連接配線層
38‧‧‧最上層連接配線層
39‧‧‧第1導電層
40‧‧‧第2導電層
41‧‧‧第3導電層
42‧‧‧覆蓋絕緣層
43‧‧‧接觸件
44‧‧‧接觸件
45‧‧‧接觸件
46‧‧‧表面電極
47‧‧‧側壁絕緣膜
LS‧‧‧一側
r1‧‧‧第1範圍
r2‧‧‧第2範圍
r3‧‧‧特定範圍
rp‧‧‧基準點
RS‧‧‧另一側
圖1係洗淨步驟所使用之洗淨裝置之剖視圖。 圖2係顯示本實施形態之洗淨器之噴嘴之配置之圖。 圖3係顯示自圖2之各噴嘴噴射之水之噴射範圍之圖。 圖4係顯示一比較例之洗淨器之噴嘴之配置之圖。 圖5係顯示自圖4之各噴嘴噴射之水之噴射範圍之圖。 圖6係顯示部分使用本實施形態之半導體製造方法製造之半導體裝置之概略構成之剖視圖。 圖7係圖6所示之貫通電極之詳細剖視圖。
2‧‧‧半導體晶圓
2a‧‧‧洗淨對象面
2b‧‧‧法線
4‧‧‧洗淨腔室
5‧‧‧洗淨器
6‧‧‧噴嘴
7‧‧‧旋轉軸
8‧‧‧旋轉驅動部

Claims (7)

  1. 一種半導體製造方法,其具備如下步驟: 於半導體晶圓之一主面上,利用第1鍍覆處理形成第1金屬膜; 一面自與上述半導體晶圓之上述一主面隔開配置之洗淨器朝上述一主面上噴射洗淨液,一面使上述洗淨器及上述半導體晶圓之至少一者旋轉,而洗淨上述第1金屬膜之表面;及 於上述第1金屬膜上,利用第2鍍覆處理形成第2金屬膜;且 於上述洗淨器,設置有沿一方向配置之複數個噴嘴; 上述複數個噴嘴係自與上述半導體晶圓之中心位置對向之位置偏離配置,且於上述半導體晶圓之周緣部側較上述半導體晶圓之中心側配置得更多; 配置於上述半導體晶圓之周緣部側之噴嘴係對自上述一方向傾斜之方向之第1範圍內噴射上述洗淨液; 配置於上述半導體晶圓之中心側之噴嘴中之1者對包含上述半導體晶圓之中心位置之第2範圍內噴射上述洗淨液。
  2. 如請求項1之半導體製造方法,其中上述一方向係與通過上述半導體晶圓之中心位置之法線交叉、且於與上述一主面平行之方向延伸之方向。
  3. 如請求項2之半導體製造方法,其中上述複數個噴嘴係以與通過上述半導體晶圓之中心位置之法線交叉之點為基準點,於上述一方向之一側與另一側各配置相同數量。
  4. 如請求項3之半導體製造方法,其中於上述一方向之上述一側與上述另一側各自之上述半導體晶圓之周緣側,配置2個以上噴嘴,該等2個以上噴嘴之各者係於自上述一方向傾斜相同角度之上述第1範圍內噴射上述洗淨液。
  5. 如請求項1至4中任一項之半導體製造方法,其中上述洗淨器以上述一方向之中心位置為旋轉軸,於上述半導體晶圓之周圍旋轉; 上述半導體晶圓被固定。
  6. 如請求項1至4中任一項之半導體製造方法,其具備如下步驟: 於形成上述第2金屬膜之後,一面自上述洗淨器朝上述一主面上噴射洗淨液,一面使上述洗淨器或上述半導體晶圓旋轉,而洗淨上述第2金屬膜之表面;及 於上述第2金屬膜上,利用第2鍍覆處理而形成第3金屬膜。
  7. 如請求項1至4中任一項之半導體製造方法,其中 具備於形成於上述半導體晶圓之孔之內壁部分形成絕緣膜之步驟;且 於上述第1鍍覆處理中,於形成於上述孔之內部之側壁之上述絕緣膜上形成上述第1金屬膜,上述孔內部之上述第1金屬膜之膜厚相對於上述孔徑之比率為15.6%以上。
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