JP2011193007A - 半導体チップおよびこれを用いた半導体装置 - Google Patents
半導体チップおよびこれを用いた半導体装置 Download PDFInfo
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Abstract
【解決手段】ジンケート法による無電解めっき法を用いて、半導体チップ1の表面側のAl電極3の上にNiめっき層5が形成される。Al電極3の上には、選択的にNiめっき層5が析出されるため、周辺耐圧構造4部分には、Niめっき層5は形成されない。また、形成されるNiめっき層5は、所定の厚さに均一に形成することができる。続いて、Niめっき層5の上にAuめっき層6が形成される。無電解めっき法を用いることによって、Auめっき層6もNiめっき層5と同様に、Niめっき層5の上に選択的、かつ均一に形成される。
【選択図】 図1
Description
図5は、従来のケース構造型の半導体装置の断面図である。
なお、接続導体は、半導体チップの表面電極と絶縁基板上に構成された第2の回路パターンとに接合されるリードフレームと、半導体チップの表面電極と接合し、一端を外部電極としてモジュール外部に露出させる外部電極用端子を含む、はんだ接合によって半導体チップ表面電極に接合される導体を言う。
本発明の実施の形態の半導体チップ1は、ベアチップ2の表面側にAl膜で形成されたAl電極3が積層されており、Al電極3の側面には、周辺耐圧構造4を形成するポリイミド膜が成膜される。
このような無電解Ni/Auめっき工程を経て2層電極膜が形成された半導体チップ1は、Al電極3の上に選択的に電極膜が形成されており、周辺耐圧構造4部に電極膜が形成されることがない。このため、半導体チッププロセスにおいて行われていたNi/Au層のエッチング工程を省くことができ、プロセスを簡単にすることができる。
上記の説明のように、ベアチップ2にAl電極3と周辺耐圧構造4が形成された状態で、無電解Ni/Auめっき工程が開始される。すなわち、表面電極にアルミワイヤがボンディングされる従来の半導体チップがウェハ状態あるいはダイシング後のチップ状態のときに、無電解Ni/Auめっき工程に入る。
続いて、第2工程の脱脂、第4工程の酸エッチングが実施され、Al電極3の表面の汚れと、Al酸化膜が除去される。
第6工程でジンケートを行う浴に半導体チップを浸漬することで、イオン化傾向によりAlが溶出し、代わりに選択的に亜鉛(Zn)がAl電極3表面に析出する(置換めっき)。その後、ZnとNiを置換する。
続く第10工程では、Niめっき層5表面の酸化を防止するために、上記説明のような置換めっきを用いてNiめっき層5の上にAuめっき層6を成膜する。
このように、従来の工程に無電解Ni/Auめっき工程を追加することで、周辺耐圧構造4を形成するポリイミド膜上には金属が堆積することなく、半導体チップ1の表面Al電極3上にはんだ接合に必要なNiめっき層5およびAuめっき層6の2層電極膜を成膜することが可能となる。
図3は、本発明の実施の形態の半導体チップが実装される半導体装置の構造を示す断面図である。
絶縁基板15は、セラミックなどの絶縁板の両面に金属層を形成したものであり、絶縁層15bを挟んで下側(半導体チップ非搭載面)に金属層15a、上側(半導体チップ搭載面)に金属層15c、15dを具備する構造をとる。半導体チップが接合される側の面の金属層(15c、15d)は、所定の回路パターンとして形成されている。
また、半導体チップ1の表面側は、はんだ層12cを介して熱伝導性と導電性を備えたリードフレーム20aに接合する。図の例では、リードフレーム20aは、放熱効率を上げるため、半導体チップ1の表面を覆うような形状を備えているが、半導体チップ1の表面に形成された均一な2層電極膜により、信頼性の高いはんだ接合配線が確保される。リードフレーム20aのもう一方は、絶縁基板15の表面に形成された第2回路パターン15dに接合し、これによって電気的な配線経路が構成される。また、リードフレーム20bは、外部電極用端子14との配線経路としても用いられる。
図4は、めっき層形成後のNiめっき層とはんだ接合後のNiめっき層の厚さの関係を示している。図は、横軸がはんだ接合前、すなわち、無電解めっき法によって形成されたNiめっき層の厚さ(図では初期Niめっき厚さ)を表しており、縦軸がはんだ接合後のNiめっき層の厚さを示している。
2 ベアチップ
3 アルミニウム(Al)電極
4 周辺耐圧構造
5 Niめっき層
6 Auめっき層
12a、12b、12c はんだ層
14 外部電極用端子
15 絶縁基板
15a 金属層
15b 絶縁層
15c 金属層(第1回路パターン)
15d 金属層(第2回路パターン)
16 放熱ベース
17 ケース
20a、20b リードフレーム
Claims (15)
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップにおいて、
アルミニウム(Al)層から形成される前記表面電極と、
前記表面電極の側面に形成される周辺耐圧構造と、
該周辺耐圧構造の内側の前記表面電極上にジンケート法による無電解めっき法で選択的に成膜されるニッケル(Ni)層及び該ニッケル(Ni)層の上に積層される金(Au)層からなる電極膜と、を有する半導体チップ。 - 前記周辺耐圧構造がポリイミド膜からなる請求項1記載の半導体チップ。
- 前記ニッケル(Ni)層の厚さは3μm以上である請求項1記載の半導体チップ。
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置において、
アルミニウム(Al)層から形成される前記表面電極と、
前記表面電極の側面に形成される周辺耐圧構造と、
該周辺耐圧構造の内側の前記表面電極上にジンケート法による無電解めっき法で選択的に成膜されるニッケル(Ni)層及び該ニッケル(Ni)層の上に積層される金(Au)層からなる電極膜と、を有し、かつ、
前記表面電極は前記電極膜を介し、Sn−Ag系鉛フリーはんだを用いて前記接続導体と接合され、電極膜はNiとSnが拡散した層を含む半導体装置。 - 前記周辺耐圧構造がポリイミド膜からなる請求項4記載の半導体装置。
- 前記ニッケル(Ni)層の厚さが1μm以上である請求項4記載の半導体装置。
- 前記Sn−Ag系鉛フリーはんだはSn−3.5Agである請求項4記載の半導体装置。
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップの製造方法において、
アルミニウム(Al)層から形成される前記表面電極と、前記表面電極の側面に形成される周辺耐圧構造とを有するベアチップを用意する工程と、
該周辺耐圧構造の内側の前記表面電極上に、ニッケル(Ni)層と金(Au)層とから成る電極膜をジンケート法により選択的に形成する無電解めっき工程と、を有する半導体チップの製造方法。 - 前記周辺耐圧構造がポリイミド膜からなる請求項8記載の半導体チップの製造方法。
- 前記ニッケル(Ni)層の膜厚が3μm以上である請求項8記載の半導体チップの製造方法。
- 裏面電極が絶縁基板上に構成された回路パターンに接合され、表面電極が接続導体に接合される半導体チップを実装した半導体装置の製造方法において、
アルミニウム(Al)層から形成される前記表面電極と、前記表面電極の側面に形成される周辺耐圧構造とを有するベアチップを用意する工程と、
該周辺耐圧構造の内側の前記表面電極上に、ニッケル(Ni)層と金(Au)層とから成る電極膜をジンケート法により選択的に形成する無電解めっき工程と、
前記表面電極と前記接続導体とを、前記電極膜を介し、Sn−Ag系鉛フリーはんだを用いて接合する接合工程と、を有する半導体装置の製造方法。 - 前記周辺耐圧構造がポリイミド膜からなる請求項11記載の半導体装置の製造方法。
- 前記無電解めっき工程が、前記ベアチップのプラズマクリーニングを含む請求項11記載の半導体装置の製造方法。
- 前記ニッケル(Ni)層の膜厚が3μm以上である請求項11記載の半導体装置の製造方法。
- 前記接合工程の後、電極膜はNiにSnが拡散した層を含み、前記ニッケル(Ni)層の膜厚は1μm以上である請求項11記載の半導体装置の製造方法。
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JP2016048760A (ja) * | 2014-08-28 | 2016-04-07 | 三菱電機株式会社 | 半導体装置 |
WO2018088284A1 (ja) * | 2016-11-14 | 2018-05-17 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子および製造方法、並びに電子機器 |
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JP2000150574A (ja) * | 1998-11-13 | 2000-05-30 | Fujitsu Ltd | 半導体装置及び半田による接合方法 |
JP2002093837A (ja) * | 2000-09-13 | 2002-03-29 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2002313832A (ja) * | 2001-04-17 | 2002-10-25 | Nagase & Co Ltd | 突起電極とその製造方法 |
JP2003068959A (ja) * | 2001-08-22 | 2003-03-07 | Denso Corp | 半導体装置 |
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JP2000150574A (ja) * | 1998-11-13 | 2000-05-30 | Fujitsu Ltd | 半導体装置及び半田による接合方法 |
JP2002093837A (ja) * | 2000-09-13 | 2002-03-29 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2002313832A (ja) * | 2001-04-17 | 2002-10-25 | Nagase & Co Ltd | 突起電極とその製造方法 |
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WO2018088284A1 (ja) * | 2016-11-14 | 2018-05-17 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子および製造方法、並びに電子機器 |
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