TW201509249A - 具有貫通電極的配線基板、其製造方法及半導體裝置 - Google Patents
具有貫通電極的配線基板、其製造方法及半導體裝置 Download PDFInfo
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- TW201509249A TW201509249A TW103118924A TW103118924A TW201509249A TW 201509249 A TW201509249 A TW 201509249A TW 103118924 A TW103118924 A TW 103118924A TW 103118924 A TW103118924 A TW 103118924A TW 201509249 A TW201509249 A TW 201509249A
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- electrode
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- wiring
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- wiring board
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Classifications
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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- H01L21/4814—Conductive parts
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/09—Use of materials for the conductive, e.g. metallic pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
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- H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/26—Cleaning or polishing of the conductive pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
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- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1511—Structure
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
本發明的課題在提供一種配線對玻璃具有密著力且具備沒有孔隙的貫通電極,並可靠性高、電氣特性優良之玻璃製中介層及其製造方法。該製造方法具有:在玻璃(1)的內部形成第一層配線形成部(3)和第一層連接盤形成部(4)之工序;僅在玻璃(1)的表面形成金屬層(6)之工序;僅在從背面的連接盤形成部(4)至成為表面的連接盤形成部(4)的部分之玻璃(1),形成盲孔(7)之工序;使用金屬層(6)藉由電解鍍敷埋入盲孔(7)而形成貫通電極(8)之工序;在玻璃(1)的背面形成金屬層(14)之工序;以及研磨玻璃(1)的表背面的金屬層(6)及(14)直到玻璃(1)露出為止。
Description
本發明係關於例如具備貫通電極之玻璃的配線基板,詳言之,係關於可在玻璃形成具有密著力的配線,且可作為在貫通電極沒有孔隙之可靠性高且電氣特性亦優異的中介層使用之具有貫通電極的配線基板、其製造方法及半導體裝置。
在晶圓製程中所製造的各種記憶體、CMOS(互補型金屬氧化膜半導體)、CPU(中央演算處理裝置)等的半導體元件,具有電性連接用端子。該連接用端子的間距、與應和半導體元件電性連接之印刷基板側的連接部的間距,通常,其等的尺度(scale)相差數倍到數十倍左右。因此,將半導體元件與印刷基板電性連接時,可使用被稱為中介層之間距變換用的仲介用基板(半導體元件安裝用基板)。在該中介層的一面安裝半導體元件,在另一面或基板的周邊進行與印刷基板的連接。
就用以將半導體元件安裝於印刷基板的中介層而言,目前為止係使用有機基板或有機增層基板。可是,因為近來以智慧型手機為代表之急速的電子機器的高性能化的關係,將半導體元件縱向積層、或者將記憶體、邏輯之類的不同半導體元件排列安裝在同一基板上
的3次元安裝技術或2.5次元安裝技術之開發有正日趨必要不可缺少。藉由此等的開發,可實現電子機器類的進一步高速化.大容量化.低消耗電力化等,伴隨半導體元件的高密度化,中介層亦需要設置更微細的配線。
可是,使用以往的有機材料的基板中,會產生因樹脂的吸濕或溫度所導致的伸縮大,而難以進行對準尺度(scale)的微細配線的形成之問題。
因此,近年,在基材使用矽或玻璃之中介層的開發受到很大注目。由於幾乎不會受到使用有機基板時會成為問題之吸濕或伸縮的影響,所以有利於微細配線的形成。又,由於具備高加工性,所以可形成在內部開設微細的貫通孔並以導電性物質充填該孔而作成且被稱為TSV(Through-Silicon Via)或TGV(Through-Glass Via)的貫通電極。此貫通電極由於可縮短配線長度並可以最短距離連接基板的表背面的彼此配線,所以可實現信號傳送速度之高速化等優良的電氣特性。再者,具有以下等許多優點,例如:由於在內部形成配線的構造,故對電子裝置的小型化或高密度化亦為有效的安裝方法;藉由貫通電極的採用,可進行多銷並列連接,因不需要使LSI本身高速化,故可實現低消耗電力化。
若將兩者進行比較的話,以矽中介層而言,其比玻璃中介層能更微細化,且確立有配線或TSV形成製程,但另一方面,因為會有如下的大缺點:由於只能以圓形矽晶圓處理,故無法使用晶圓周邊部;以及由於無法以大型尺寸一次生產,故成本變高。關於這點,在
玻璃中介層中,由於可進行大型面板的大量處理,且也可考量輥對輥(roll-to-roll)的生產方法,故可大幅降低成本。又,與利用放電或雷射等方式貫通的TGV不同,TSV是藉由氣體蝕刻來挖掘孔,所以包含加工時間變長或將晶圓切削得較薄之工序等也是增加成本的主要原因。
再者,在電氣特性方面,玻璃中介層其基板本身為絕緣體,與矽中介層不同,所以即便在高速電路中也不會有寄生元件產生的疑慮,電氣特性更優良。原本基板使用玻璃時,就不需要形成絕緣膜的工序本身,所以絕緣可靠性高,且也可縮短工序。
如以上所述,雖然是能以低成本製作中介層的玻璃,但會有以下的大缺點:形成微細配線的製程沒有確立;以及由於日益成為配線材料的主流的銅不會密著於玻璃,所以在基板上形成配線時,需要對表面進行特殊處理。再者,TGV的形成需要通孔充填(through hole via filling)的工序,所以會有發生孔隙且可靠性大有問題。
例如,引用文獻1等曾提出可使用玻璃中介層進行高密度安裝的方法。然而,引用文獻1的技術中,雖然比起以往的有機樹脂,是使用形成有微細銅配線的玻璃中介層,但是並沒有與配線的形成方法相關的詳細描述,所以欠缺可靠性。
又,專利文獻2等曾提出使用無電解鍍敷以未粗化的方式在玻璃上形成金屬膜之方法,但是當鍍敷膜加厚成可使用於配線時,密著力不足,故有輕易地剝離
之慮。
[專利文獻1]日本特開2003-249606號公報
[專利文獻2]日本特開平10-209584號公報
本發明係為解決上述課題而完成者,目的在提供一種作為玻璃中介層使用之配線基板、其製造方法及半導體裝置,其中該配線基板係藉由在玻璃基板的內部埋入第一層配線層,而使密著力大幅提升,再者,TGV的形成是藉由使用電解鍍敷選擇性地以增層法僅埋入貫通電極部而防止孔隙的產生,所以可靠性高。
請求項1的發明係一種具有貫通電極的配線基板,其係在基材為玻璃且其內部具備貫通電極而成之多層構造之具有貫通電極的配線基板,其特徵為:前述基材的表背面的第一層配線層與前述貫通電極係形成於玻璃的內部。
請求項2的發明係如請求項1之具有貫通電極的配線基板,其特徵為:貫通電極部分的主材料係Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe或包含此等金屬的化合物之任一者。
請求項3的發明係一種具有貫通電極的配線
基板的製造方法,其特徵為:在玻璃的內部,形成成為第一層配線和接承貫通電極的連接盤之部分的工序;僅在前述玻璃的表面形成金屬層的工序;僅在從接承背面的前述貫通電極之連接盤至成為表面的該連接盤之部分的前述玻璃,形成貫通孔之工序;以導電性物質埋入前述貫通孔的工序;在前述背面形成金屬層的工序;以及研磨前述玻璃之表背面的前述金屬層直到玻璃面露出為止之工序。
請求項4的發明係如請求項3之具有貫通電極
的配線基板的製造方法,其特徵為:以導電性物質埋入配線基板的貫通孔的工序,係藉由電解鍍敷法選擇性地以增層法僅埋入貫通孔的內部。
請求項5的發明係如請求項3或4之具有貫通
電極的配線基板的製造方法,其特徵為:貫通電極部分的主材料係Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe或包含此等金屬的化合物之任一者。
請求項6的發明之特徵為:使用如請求項1之具有貫通電極的配線基板,在該板面最上層部搭載半導體元件而構成半導體裝置。
根據本發明之具有貫通電極的配線基板,可輕易地製作即便是使用基材為玻璃的配線基板,其配線的密著力也高,且在貫通電極部沒有孔隙之可靠性高的配線基板。
亦即,根據本發明之具有貫通電極的配線基
板,係藉由將配線及連接盤的部分在表背面一起加工到玻璃內之後,用金屬層埋入,藉此成為第一層配線層被組入內部的形態,可使密著力大幅提升,且藉由配線之表面以外的所有面與玻璃密著,即使沒有前處理也具有高密著性,能提升裝卸(handling)時的可靠性。
又,根據本發明的製造方法,構成為在TGV的形成方法使用盲孔充填(blind via filling),不用進一步使晶種層形成於通路內,而能進行電解鍍敷。由於藉由形成於單面的金屬層,僅在通路的底部存在晶種層,所以當進行電解鍍敷時,便可從通路底部以增層方式使鍍敷物析出,可在不會有鍍敷物的析出集中在開口部的情況下進行充填,可輕易地形成無孔隙的TGV,可實現高可靠性與優良的電氣特性。
以貫通電極的主材料而言,藉由使用Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe或包含此等金屬的化合物之任一者,可藉由鍍敷容易地析出作為單體或合金,可確保優良的電氣特性。
又,本發明之具有貫通電極的配線基板,因可供搭載半導體元件、或可對印刷配線板進行安裝,所以當作為半導體裝置使用時,由於配線層係以貫通電極連接,所以具有高速傳送特性等優異的電氣特性。又,藉由在內部形成配線的構造,也有助於電子機器的小型化。
1‧‧‧玻璃
2‧‧‧阻劑
3‧‧‧第一層配線形成部
4‧‧‧第一層連接盤形成部
5‧‧‧阻劑
6‧‧‧金屬層
7‧‧‧盲孔
8‧‧‧貫通電極
9‧‧‧金屬層
10‧‧‧第一層配線
11‧‧‧第一層連接盤
12‧‧‧絕緣層
13‧‧‧貫通孔
14‧‧‧金屬層
15‧‧‧貫通電極
16‧‧‧配線層
17‧‧‧連接盤
18‧‧‧絕緣層
19‧‧‧焊球
20‧‧‧邏輯晶片
21‧‧‧記憶體晶片
22‧‧‧印刷配線板
圖1係顯示本發明一實施形態之具有貫通電極的配線基板的主要部分的剖面之概念圖。
圖2A係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖2B係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖2C係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖2D係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖2E係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖2F係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖3A係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖3B係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面
之概念圖。
圖3C係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖3D係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖3E係為了說明本發明一實施形態之具有貫通電極的配線基板的製造方法的步驟,而顯示主要部分的剖面之概念圖。
圖4A係為了說明形成第二層配線層的步驟,而顯示主要部分的剖面之概念圖。
圖4B係為了說明形成第二層配線層的步驟,而顯示主要部分的剖面之概念圖。
圖4C係為了說明形成第二層配線層的步驟,而顯示主要部分的剖面之概念圖。
圖4D係為了說明形成第二層配線層的步驟,而顯示主要部分的剖面之概念圖。
圖4E係為了說明形成第二層配線層的步驟,而顯示主要部分的剖面之概念圖。
圖5係為了說明使用了圖1之具有貫通電極的玻璃配線基板的本發明一實施形態的半導體裝置,而顯示主要部分的剖面之概念圖。
以下,參照圖面,詳細說明本發明實施形態
之具有貫通電極的配線基板、其製造方法及半導體裝置。
圖1顯示本發明一實施形態之具有貫通電極
的配線基板,在成為基材之玻璃1的表背面,第一層配線10及連接盤(land)11被埋入內部而形成。埋設於表背面的第一層連接盤11係藉貫通電極8連接。
其次,參照圖2及圖3,詳細說明具有貫通電
極的配線基板之製造方法。
首先,在玻璃1將阻劑2圖案化(圖2A、圖2B)
。以形成手段而言,可藉由光刻形成。將阻劑2塗布於玻璃整面後,使用既定的遮罩進行曝光,利用顯影去除多餘的阻劑(resist),藉此可進行圖案化。較理想為阻劑2係以達到蝕刻的選擇比之方式盡量形成較厚。又,亦可以使Al、Ni等的金屬膜圖案化的方法,來取代阻劑2。玻璃的種類並無特別限定。例如,可使用石英玻璃或硼矽酸玻璃、無鹼玻璃等。
接著,將阻劑2圖案化後,如圖2C所示,在
玻璃1的內部,分別形成成為配線10的第一層配線形成部3、和成為連接盤11的第一層連接盤形成部4。以形成手段而言,可考量乾式蝕刻或濕式蝕刻,但以使用乾式蝕刻較佳。原因在於:濕式蝕刻為各向同性,所以不僅在縱向可進行蝕刻,在橫向也可進行蝕刻;但乾式蝕刻為各向異性,所以僅能在縱向進行選擇性蝕刻,而適用於微細圖案形成。使用於乾式蝕刻的氣體並無限定,可使
用例如HF、CF4、SF6等氟系氣體。
將配線形成部3及連接盤形成部4加工後,如
圖2D所示將已圖案化的阻劑2去除。去除的方法並無限定,在阻劑為有機物的情況,可藉由強鹼剝離劑或灰化來去除,在阻劑為金屬的情況,若是Ni則可藉由硫酸/過氧化氫水的混合液或氯化鐵(III)水溶液來去除,若是Al則可藉由磷酸/硝酸/乙酸的混合液等來去除。
在包含配線形成部3及連接盤形成部4的面,
以圖2E、圖2F的步驟形成金屬層6。以形成手段而言,可藉由無電解鍍敷形成晶種層,藉由電解鍍敷使金屬層6成長。此時,藉由事先在背面形成阻劑5(參照圖2E),可僅在單面選擇性地進行鍍敷。又,亦可採用以濺鍍或蒸鍍等物理方法形成晶種層,以電解鍍敷使金屬層6成長的方法。此時,由於可僅在單面形成晶種層,故形成阻劑5的工序可省略。雖然形成於單面的金屬層6對玻璃1的密著力弱,但由於在玻璃1表面有實施微細加工,故不會有因為與定錨效應(anchor effect)同樣的作用而輕易地造成金屬層6剝離的情況發生。
為了形成盲孔(blind hole)7,去除形成於背面
的阻劑5(圖3A、圖3B)。以盲孔7的形成手段而言,可使用雷射。加工玻璃的雷射係以波長較長者為佳,又,波長較長的雷射由於銅的吸收率低,故若使用二氧化碳雷射等,可選擇性地使玻璃貫通。
將所形成的盲孔7藉由電解鍍敷法充填導電
性物質,而形成貫通電極8(圖3C)。此時,藉由以金屬層
6作為電極進行電解鍍敷,可從盲孔的底部以增層方式使鍍敷物析出。由於鍍敷物是從通路底部依序析出,故可防止孔隙的產生。以貫通電極材料而言,係以成本或電氣特性兩方面者皆優異的銅較佳。
貫通電極8形成後,如圖3D所示,在背面部
分形成金屬層9。以形成手段而言,係可與金屬層6同樣在藉由無電解鍍敷或濺鍍形成晶種層後,藉由電解鍍敷使金屬層9成長。雖然也可僅藉由無電解鍍敷或濺鍍使金屬層增厚,但以使用可在短時間使金屬層增厚的電解鍍敷較佳。
利用CMP(Chemical Mechanical Polishing,化
學機械研磨)等研磨形成於玻璃1的兩面之金屬層6及金屬層9,直到如圖3E所示那樣玻璃面露出為止,可製作表背面的第一層配線10及連接盤11被埋在玻璃1內部且具有無孔隙的貫通電極之玻璃配線基板。
接著,參照圖4,說明第二層配線層的製造方法。
在配線基板形成絕緣層12(圖4A)。此絕緣層12可使用SiO2膜或Si3N4、聚醯亞胺等,材料並不限定於此等。以形成手段而言,可藉由CVD法或旋轉塗布法、溶膠凝膠法等形成。
其次,為了與配線基板連接,如圖4B所示藉由雷射等在絕緣層12開設貫通孔13。此時,進行對準,設成僅使第一層連接盤11露出。以導電性物質埋入此貫通孔13,如圖4C所示形成作為第二層配線層的金屬層14
。金屬層14可利用鍍敷或導電性糊等形成,材料並無特別限定,但由成本或電氣特性方面來看,以銅較佳。
其後,藉由蝕刻金屬層14進行電路形成,如
圖4D所示形成配線層16及連接盤17。在此層上,如圖4E所示再度形成絕緣層18,藉此可製作透過貫通電極15與第一層電性連接之第二層配線層。
第二層以後的配線係可藉由反覆進行第二層
配線層的形成工序,不管幾層都可自由地設置配線層的數量。此外,圖4中,僅顯示表面的配線之製造方法,關於背面的配線層亦可以同樣的方法製作。
本發明之具有貫通電極的配線基板係可作為
半導體裝置使用,例如,作為圖5所示之中介層使用。亦即,使用焊球19,將記憶體晶片21與邏輯晶片20同樣地搭載於表面,背面也同樣是使用焊球19安裝印刷配線板22,藉此可作為2.5次元安裝構造的玻璃中介層使用。邏輯晶片20和記憶體晶片21係可在同一平面上的近距離進行信號的交換,又,可藉由貫通電極以最短距離將信號傳送到印刷配線板22,所以具有優異的電氣特性。由於基材為玻璃,故不會伸縮,可作為具有遠比以往的有機樹脂基板還要高密度的配線層之中介層而發揮機能。
以下,製作依據本發明實施形態的實施例,並進行探討。
首先,對製作具有貫通電極的玻璃配線基板的實施例進行說明。亦即,準備厚度300μm的無鹼玻璃
,藉由旋轉塗布法形成25μm之可形成厚膜的光硬化性SU-8阻劑(環氧樹脂基底的負型)。使用既定的遮罩進行曝光後,使用PGMEA(聚丙二醇甲醚乙酸酯:polypropylene glycol methyl ether acetate)作為顯影液來進行圖案化。背面也是利用同樣的方法,進行圖案化。
其次,藉由利用SF6氣體的乾式蝕刻,在玻璃
的表面形成成為配線及連接盤的部分。規格是將配線部分設為寬度5μm,將連接盤部分設為100μm平方,深度方向均加工20μm。背面也是利用同樣的方法事先加工。藉由灰化去除阻劑圖案後,僅在表面藉由銅濺鍍形成晶種層,藉由電解銅鍍敷,用銅充填加工部分。最後使銅成長到玻璃表面的銅厚達5μm為止。
然後,從玻璃的背面進行對準,朝連接盤部
分照射二氧化碳雷射,形成直徑為75μm的盲孔。繼之,將表面的銅膜連接到電極並藉由電解銅鍍敷,充填盲孔以形成貫通電極。
與在表面形成銅膜的方法同樣,背面也是利
用濺鍍形成銅的晶種層,利用電解銅鍍敷充填加工部分。最後,藉由CMP研磨形成於表背面的銅直到玻璃面露出為止,藉此可製作可作為玻璃中介層使用的配線基板,該玻璃中介層具有密著力高的配線層且具有沒有孔隙的貫通電極。
其次,說明關於第二層以後之配線層的製作。
以絕緣層而言,係塗布20μm的聚醯亞胺樹脂
,並藉由二氧化碳雷射開設75μm的孔。其後,在貫通孔及聚醯亞胺上藉由無電解銅鍍敷形成晶種層,進而,藉由電解銅鍍敷形成10μm厚度的導體層,藉由對該導體層進行光刻而進行電路形成。
再度塗布聚醯亞胺樹脂並使絕緣層形成於電路,藉此可形成第二層配線層。使配線進一步多層化時,係可藉由重複進行上述方法來形成,且背面也是以同樣的方法形成。
藉由上述構成,可確認可製造在玻璃基板上密著配線,且具有沒有孔隙的貫通電極之配線基板。
此外,本發明不侷限於上述實施形態,其他,可在實施階段於不脫離其要旨的範圍內實施各種變形。再者,上述實施形態含有各種階段的發明,藉由所揭示之複數個構成要件的適當組合,可形成各種發明。
例如,在即便由實施形態所示之所有構成要件刪除幾個構成要件,亦可解決發明欲解決之課題的欄位所敘述之課題,且可得到發明效果所敘述之效果的情況下,則此構成要件經刪除後的構成可被取出作為發明。
根據上述構成,可被利用作為能因應3次元安裝或2.5次元安裝之電子機器的高機能化、高速化之中介層的製造方法。
1‧‧‧玻璃
3‧‧‧第一層配線形成部
4‧‧‧第一層連接盤形成部
6‧‧‧金屬層
7‧‧‧盲孔
8‧‧‧貫通電極
10‧‧‧第一層配線
11‧‧‧第一層連接盤
12‧‧‧絕緣層
14‧‧‧金屬層
Claims (6)
- 一種具有貫通電極的配線基板,其係在基材為玻璃且其內部具備貫通電極而成之多層構造之具有貫通電極的配線基板,其特徵為:前述基材的表背面的第一層配線層與前述貫通電極係形成於玻璃的內部。
- 如請求項1之具有貫通電極的配線基板,其中,在前述配線基板中,貫通電極部分的主材料係Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe或包含此等金屬的化合物之任一者。
- 一種具有貫通電極的配線基板的製造方法,其特徵為:在玻璃的內部,形成成為第一層配線和接承貫通電極的連接盤之部分的工序;僅在前述玻璃的表面形成金屬層的工序;僅在從接承背面的前述貫通電極之連接盤至成為表面的該連接盤之部分的前述玻璃,形成貫通孔之工序;以導電性物質埋入前述貫通孔的工序;在前述背面形成金屬層的工序;以及研磨前述玻璃之表背面的前述金屬層直到玻璃面露出為止之工序。
- 如請求項3之具有貫通電極的配線基板的製造方法,其中,以導電性物質埋入前述配線基板的貫通孔的工序,係藉由電解鍍敷法選擇性地以增層法僅埋入前述貫通孔的內部。
- 如請求項3或4之具有貫通電極的配線基板的製造方法,其中,在前述配線基板中,貫通電極部分的主材料係Cu、Ag、Au、Ni、Pt、Pd、Ru、Fe或包含此等金屬的化合物之任一者。
- 一種半導體裝置,其特徵為:使用如請求項1之具有貫通電極的配線基板,在該板面最上層部搭載有半導體元件。
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