TW201330201A - 成型中介層封裝及其製造方法 - Google Patents
成型中介層封裝及其製造方法 Download PDFInfo
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- TW201330201A TW201330201A TW101150901A TW101150901A TW201330201A TW 201330201 A TW201330201 A TW 201330201A TW 101150901 A TW101150901 A TW 101150901A TW 101150901 A TW101150901 A TW 101150901A TW 201330201 A TW201330201 A TW 201330201A
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- Prior art keywords
- metal
- wafer
- interposer package
- molding material
- top surface
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- 238000000034 method Methods 0.000 title claims abstract description 194
- 239000002184 metal Substances 0.000 claims abstract description 382
- 229910052751 metal Inorganic materials 0.000 claims abstract description 382
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- 239000010949 copper Substances 0.000 claims description 11
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
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- 229910052732 germanium Inorganic materials 0.000 description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 7
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- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Abstract
本發明揭露一種成型中介層封裝及其製造方法。成型中介層封裝包括複數個金屬塊;一成型材質,包裹該些金屬塊,使該些金屬塊的複數個底面暴露出來;一第一晶片,設置於該成型材質上,且連接至該些金屬塊的複數個頂面;複數個焊球,連接且接觸該些金屬塊的該些底面。
Description
本申請的申請專利範圍依35 U.S.C.§119要求如下申請的優先權:2012年01月04日遞交的申請號為61/583,113的美國臨時案;2012年01月19日遞交的申請號為61/588,347的美國臨時案。在此合併參考這些申請案的申請標的。
本發明係有關於一種中介層封裝(interposer package)及其製造方法,特別係有關於一種成型中介層封裝(molded interposer package)及其製造方法。
中介層為一電子介面,其於連接座之間繞線或將一連接座連接至另一連接座。中介層的目的係加寬晶片的一凸塊到一連線的間距,或將連線重新繞線。習知的中介層製程係首先提供利用堆疊雙馬來醯亞胺-三氮雜苯樹脂(bismaleimide triacine,BT)形成的樹脂基核心基板(resin-based core substrate)。接著,依序進行一穿孔蝕刻(through via etching)製程、一絕緣物氧化(insulation oxidation)製程、一金屬填充(metal filling)製程、一多層接線(multilayer wiring)製程、一防焊層(solder mask)製程、一微凸塊(micro bumping)製程、一晶片安裝(chip mounting)製程和一成型蓋(mold cap)製程。值得注意的是,習知的核
心基板和穿孔為複合結構。習知的多層接線製程和防焊層製程需要於核心基板的兩側上形成內連線結構和防焊層。為了增加封裝剛性,習知技術需要成型蓋(mold cap)製程。因此,由於前述的複雜製程,所以習知的中介層的製程成本高。另外,習知的樹脂基核心基板因為其機械強度不佳,所以僅能製作成小尺寸。前述的缺點會限制中介層技術的發展。並且,習知的中介層係遭受許多設計挑戰。舉例來說,習知中介層係難以對核心基板和輸入/輸出(I/O)提供適當的電源傳輸網路,且上述電源傳輸網路包括對較寬的電源線(wider power traces)、專用的電源層(dedicated power planes)、專用的電源島狀物(dedicated power islands)和直接貼附在板上的去耦合電容(on-board decoupling capacitors)的選擇。並且,習知中介層係難以對並排(side-by-side)、封裝上封裝(package-on-package,POP)、與封裝上封裝並排(side-by-POP)的動態存取記憶體匯流排(DRAM memory bus)提供配置選擇,而且難以改善穿過基板和焊球的導熱。並且,習知中介層係難以對晶片上散熱器(chip-on heat spreader)提供選擇。再者,習知中介層係難以維持現今電路板(printed circuit boar,PCB)客戶之電路密度的限制。此外,習知中介層係難以對多重晶片(multi-die)和混合接線(hybrid wire bonding)提供配置選擇。
因此,在此技術領域中,有需要一種新的中介層封裝結構。
有鑑於此,本發明之目的在於提供改良式的中介層封裝,以解決習知中介層之尺寸無法提升、高製程成本的問題。
本發明之一實施例係提供一種成型中介層封裝,包括複數個金屬塊;一成型材質,包裹該些金屬塊,使該些金屬塊的複數個底面暴露出來;一第一晶片,設置於該成型材質上,並連接至該些金屬塊的複數個頂面;複數個焊球,連接且接觸該些金屬塊的該些底面。
本發明之另一實施例係提供一種成型中介層封裝的製造方法,包括提供一金屬片,其具有一頂面和一底面;進行一第一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,因而於該金屬片中形成複數個第一凹陷;將一載板固著於該金屬片的該頂面,覆蓋該些第一凹陷;進行一第二非等向性蝕刻製程,以從該金屬片的該底面移除位於該些第一凹陷下的一部分該金屬片,因而於該金屬片中形成複數個第二凹陷,其中該些第一凹陷和該些第二凹陷係分別彼此互連;從該金屬片的該底面填入一成型材質至該些第一凹陷和該些第二凹陷,並使該金屬片的該底面暴露出來;移除該載板;於該金屬片的該頂面上形成一保護層,該保護層具有穿過該保護層的複數個開口;形成穿過該些開口的複數個第一金屬介層孔插塞;於該保護層上形成一防焊層,並使該些第一金屬介層孔插塞暴露出來。
本發明之又一實施例係提供一種成型中介層封裝的製造方法,包括提供一金屬片,其具有一頂面和一底面;進
行一第一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,因而於該金屬片中形成複數個第一凹陷;形成一成型材質,覆蓋該金屬片的該頂面,且填入該些第一凹陷;於該成型材質中形成複數個開口,其中該些開口暴露該金屬片的該頂面;於該些開口內形成複數個第一金屬介層孔插塞,且分別於該些第一金屬介層孔插塞上形成複數個第一重佈線層圖案;進行一第二非等向性蝕刻製程,以從該金屬片的該底面移除一部分該金屬片,直到暴露出該成型材質的一底面,其中蝕刻後的該金屬片係轉變成為複數個金屬塊;於該成型材質上形成一防焊層,並使該些第一重佈線層圖案暴露出來。
本發明之再一實施例係提供一種成型中介層封裝的製造方法,包括提供一金屬片,其具有一頂面和一底面;將一載板固著於該金屬片的該底面;進行一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,直到暴露出該載板,因而形成穿過該金屬片的複數個介層孔,其中蝕刻後的該金屬片係轉變成為複數個金屬塊;從該些介層孔中填入一成型材質,使該些金屬塊的該頂面暴露出來;移除該載板;於該些金屬塊的該頂面上形成一保護層,該保護層具有複數個開口,穿過該保護層;形成穿過該些開口的複數個第一金屬介層孔插塞;於該保護層上形成一防焊層,並使該些金屬介層孔插塞暴露出來。
本發明之又一實施例係提供一種成型中介層封裝的製造方法,包括提供一模具;於該模具中裝載複數個金屬塊,其中該些金屬塊的複數個上部和複數個下部分別被該模具
夾緊;於該模具中填入一成型材質,以包裹該些金屬塊;移除該模具,使該些金屬塊的該些上部和該些下部暴露出來;移除超出該成型材質的一頂面和一底面上方的暴露出來的該些金屬塊的該些上部和該些下部;於該成型材質的該頂面上形成一保護層,該保護層具有複數個開口,穿過該保護層;形成穿過該些開口的複數個第一金屬介層孔插塞;於該保護層上形成一防焊層,並使該些第一金屬介層孔插塞暴露出來。
本發明所提出之成型中介層封裝及其製造方法,可減少高製程成本。
以下以各實施例詳細說明並伴隨著圖式說明之範例,作為本發明之參考依據。在圖式或說明書描述中,相似或相同之部分皆使用相同之圖號。且在圖式中,實施例之形狀或是厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式,另外,特定之實施例僅為揭示本發明使用之特定方式,其並非用以限定本發明。
第1圖為本發明一實施例之成型中介層封裝500a的剖面圖。如第1圖所示,本發明一實施例之成型中介層封裝500a包括一成型中介層(molded builder interposer,MBI)200。上述成型中介層200包括一基板600。上述基板600包括複數個金屬塊(metal stud)202和包裹金屬塊202的
一成型材質(molding material)204。上述金屬塊202係彼此隔絕。在本發明一實施例中,每一個金屬塊202為一體成型結構(all-in-one structure),且排列為一陣列。另外,上述金屬塊202可由銅(Cu)形成。成型材質204係包裹金屬塊202,且讓金屬塊202的底面232暴露出來。在本發明一實施例中,成型材質204可由例如樹脂(resin)的成型材料形成。另外,上述成型材質204為一體成型結構(all-in-one structure)。在本發明一實施例中,金屬塊202的頂面230可充當成型中介層200的內連線墊(interconnect pad),其用於連接至少一晶片(例如,如第1圖所示的晶片222),且金屬塊202的底面232可充當球墊(ball pad),其用於連接印刷電路板(printed circuit boar,PCB)(圖未顯示)的接合墊。因此,基板600的一頂面234可充當成型中介層200的一晶片側表面(chip-side surface),且基板600的一底面236可充當成型中介層200的一印刷電路板側表面(PCB-side surface)。在本發明一實施例中,金屬塊202的頂面230可低於成型材質204的頂面或與成型材質204的頂面共平面,且金屬塊202的底面232可位於成型材質204底面的上方或與成型材質204的底面共平面。
在本發明一實施例中,設置於成型中介層200的晶片側表面上的重佈線層圖案(RDL pattern)、介電層和金屬介層孔插塞可共同充當成型中介層200之一內連線結構,且上述內連線結構係用於電性連接成型中介層200和設置於成型中介層200上的晶片222。如第1圖所示,穿過一部分成型材質204的複數個第一金屬介層孔插塞206係位於
金屬塊202的正上方。在本發明其他實施例中,第一金屬介層孔插塞206可穿過覆蓋基板600頂面234(亦即成型材質204的頂面)的一保護層(圖未顯示)而形成。一第一重佈線層圖案208設置於成型材質204和晶片222之間,且電性連接至金屬塊202和晶片222。具體來說,第一重佈線層圖案208係設置於第一金屬介層孔插塞206上。如第1圖所示,第一金屬介層孔插塞206係連接金屬塊202的頂面230和第一重佈線層圖案208。另外,一介電層210,其也充當一重佈線層介電層(RDL dielectric layer),係覆蓋第一重佈線層圖案208。在本發明其他實施例中,內連線結構可包括單層或多層重佈線層圖案。在如第1圖所示之本發明一實施例中,上述內連線結構可包括穿過介電層210連接至第一重佈線層圖案208的複數個第二金屬介層孔插塞212,以及覆蓋且連接至第二金屬介層孔插塞212的第二重佈線層圖案214。防焊層(solder mask layer)216設置於上述內連線結構之頂部,例如防焊層216設置於第二重佈線層圖案214之上。在本發明一實施例中,防焊層216可設置於第一重佈線層圖案208和晶片222之間。在本發明另一實施例中,防焊層(solder mask layer)216位於成型材質204之上且為成型中介層200的最上層。晶片222係設置於基板600的晶片側表面(亦即頂面234)上,且連接至防焊層216的一頂面。如第1圖所示,晶片222具有複數個導電凸塊220,穿過防焊層216以連接至上述內連線結構。詳細來說,晶片222的導電凸塊220可直接連接至最上層的重佈線層圖案,舉例來說,導電凸塊220可連接至本實
施例的第一重佈線層圖案208或第二重佈線層圖案214。因此,晶片222係藉由導電凸塊220和上述內連線結構連接至金屬塊202的頂面230。在本發明一實施例中,導電凸塊220包括複數個焊球、複數個金屬柱或上述組合。此外,一覆晶填充材質218係設置於防焊層216和晶片222之間。在本發明一實施例中,值得注意的是,出於封裝剛性考量,成型中介層封裝500a已經使用一成型材質(例如成型材質204)包裹金屬塊202。因此,不需任何成型材質來覆蓋晶片222和防焊層216。
在本發明一實施例中,複數個焊球224係設置於基板600的印刷電路板側表面(亦即底面236)上,用以電性連接成型中介層200和印刷電路板(圖未顯示)。如第1圖所示,焊球224係分別連接且接觸金屬塊202的底面232。值得注意的是,基板600的底面236(亦即成型材質204的底面)未被任何防焊層或任何重佈線層覆蓋。
第2-9圖為本發明不同實施例之成型中介層封裝500b~500i的剖面圖。在本發明另一實施例中,成型中介層封裝可承載至少一個額外的電子元件。如第2圖所示,成型中介層封裝500b可更包括與晶片222隔開的一電子元件,舉例來說,一表面黏著元件(surface mount technology(SMT)device)238,設置於基板600的頂面234上。上述分離的電子元件係藉由內連線結構電性連接至金屬塊202,且上述內連線結構包括複數個重佈線層圖案(包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214),和複數個金屬介層孔插塞(包括如第1圖所示的第一金屬介
層孔插塞206和第二金屬介層孔插塞212)。為了方便說明起見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。
在本發明另一實施例中,成型中介層封裝可增加一散熱物,以進一步對封裝結構散熱。如第3圖所示,成型中介層封裝500c更包括一散熱物240,覆蓋晶片222的頂面以及包括複數個重佈線層圖案(包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(包括如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212)的內連線結構。為了方便說明起見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。在本發明一實施例中,散熱物240可包括金屬。
在本發明其他實施例中,為了進一步提升封裝剛性,也可於成型中介層封裝上設置一成型蓋(mold cap)。如第4圖所示,成型中介層封裝500d可更包括一成型蓋242,覆蓋晶片222以及包括複數個重佈線層圖案(包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(包括如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212)的內連線結構。為了方便說明起見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。
在本發明另一實施例中,成型中介層封裝可構成一系統級封裝(system-in-package,SIP)。換句話說,成型中介層封裝可承載數個晶片。如第5圖所示,成型中介層封裝500e
可更包括一晶片246或一晶片248,設置於晶片222旁。並且,成型中介層封裝500e可更包括一晶片244,設置於晶片222的正上方。成型中介層封裝500e的晶片可使用一焊線技術或一覆晶技術,以連接至包括複數個重佈線層圖案(包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(包括如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212)的內連線結構。為了方便說明起見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。如第5圖所示,可利用覆晶技術,藉由導電凸塊250將晶片246連接至內連線結構。在本發明其他實施例中,設置於晶片222正上方的晶片244和設置於晶片222旁的晶片248,可分別藉由焊線(bonding wire)252和焊線254連接至內連線結構。
如第6、7圖所示,在本發明又一實施例中,成型中介層封裝可構成一封裝上封裝(package-on-package,POP)。換句話說,成型中介層封裝可允許另一個半導體封裝設置於其上。如第6圖所示,成型中介層封裝500f可更包括一半導體封裝256,設置於成型中介層200和晶片222上。半導體封裝256與晶片222隔開。並且,半導體封裝256可藉由複數個導電凸塊258連接至內連線結構,其中內連線結構包括複數個重佈線層圖案(例如,包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(例如,包括如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212)。為了方便說明起
見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。
如第7圖所示,成型中介層封裝500g可更包括一半導體封裝260,設置於晶片222旁,且位於成型中介層200上。而且,半導體封裝260與晶片222隔開。並且,半導體封裝260可藉由複數個導電凸塊262連接至內連線結構,其中內連線結構包括複數個重佈線層圖案(例如,包括如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(例如,包括如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212)。為了方便說明起見,本實施例僅顯示第一重佈線層圖案208和第一金屬介層孔插塞206。
在本發明又一實施例中,為了增加電路設計的彈性以達到多重晶片封裝的目的,成型中介層封裝可包括另一個矽中介層(silicon interposer),設置於成型中介層和晶片之間。如第8圖所示,成型中介層封裝500h可更包括一矽中介層276,設置於成型中介層200上,亦即矽中介層276設置於金屬塊202的頂面234上。矽中介層276係電性連接至成型中介層200。舉例來說,矽中介層276分別電性連接至金屬塊202和晶片264、晶片266、晶片268。具體來說,複數個彼此隔開的晶片264、晶片266、晶片268係設置於矽中介層276上。可用一表面黏著技術或一覆晶技術,將成型中介層封裝500h的矽中介層276上的晶片連接至矽中介層276。舉例來說,可使用覆晶技術,藉由導電凸塊270將晶片264連接至矽中介層276。可使用表面黏
著技術,分別藉由導電凸塊272、導電凸塊274將晶片266、晶片268連接至矽中介層276。值得注意的是,上述成型中介層封裝500h的製造可不需要如第1圖所示的內連線結構,上述內連線結構包括複數個重佈線層圖案(包括第一重佈線層圖案208和第二重佈線層圖案214)和複數個金屬介層孔插塞(包括第一金屬介層孔插塞206和第二金屬介層孔插塞212)。此外,成型中介層封裝500h也可包括介於成型中介層200和矽中介層276之間的內連線結構。
在本發明其他實施例中,用於成型中介層封裝的成型中介層的電源傳輸的金屬塊也可充當散熱物。如第9圖所示,用於成型中介層封裝500i的電源傳輸的至少兩個金屬塊202a和202b可設計為互相接觸,以形成一金屬島結構(metal island structure)280。因為金屬島結構280係由例如銅的金屬形成,所以金屬島結構280具有優異的散熱能力。因此,金屬島結構280不僅可充當電源傳輸物,而且可充當成型中介層封裝500i的一額外散熱物。
第10圖為本發明一實施例之成型中介層封裝的基板600a的上視圖,其顯示金屬塊的另一種設計。在金屬塊製程期間,可將額外元件設計於基板內。上述額外元件可具有散熱或增強封裝剛性的功能。為了增強封裝剛性和封裝平整度,基板600a可更包括穿過成型材質204之一框型金屬加固物282,其中框型金屬加固物282的一內側壁292係圍繞金屬塊202。在本發明實施例中,框型金屬加固物282可與基板600a的一邊界205平行。複數個金屬鰭284,可設置於框型金屬加固物282的一外側壁294上以進一步
對封裝散熱。如第10圖所示,金屬鰭284可從成型材質204的邊界205暴露出來。在本發明其他實施例中,金屬鰭284可突出於成型材質204的邊界205。因為框型金屬加固物282係配置接近於成型材質204的邊界205,所以框型金屬加固物282和金屬鰭284可一起構成一三維(three-dimensional,3D)散熱物,將熱迅速地散發至外界。並且,為了進一步增強封裝剛性和封裝平整度,可形成一金屬加固條288,穿過成型材質204,連接至框型金屬加固物282的相鄰兩側。再者,可將一電源/接地墊290設計為位於基板600a的中央。電源/接地墊290係提供晶片和印刷電路板(printed circuit boar,PCB)之間的電源/接地內連線。如第10圖所示,電源/接地墊290的一面積係設計為大於每一個金屬塊202的面積,以提供良好的電源性能和額外的散熱通道。
在本發明一實施例中,金屬塊202、框型金屬加固物282、金屬鰭284、金屬加固條288和電源/接地墊290可由例如銅之相同材料形成。
第11a-11i圖為本發明一實施例之成型中介層封裝的製造方法的剖面圖。並且,如第11a-11i圖所示之成型中介層封裝的製造方法也可稱為一雙面蝕刻製程(dual etch process)。如第11a圖所示,首先,提供一金屬片300,其具有一頂面302和一底面304。在本發明一實施例中,金屬片300的頂面302可充當成型中介層封裝的成型中介層的一晶片側表面(chip-side surface)。金屬片300的底面304可充當成型中介層封裝的成型中介層的一印刷電路板側表
面(PCB-side surface)。在本發明一實施例中,金屬片300具有一體成型結構(all-in-one structure)。金屬片300可由銅形成。接著,請參考第11b圖,可進行一微影製程和一非等向性蝕刻製程,以從金屬片300的頂面302移除一部分金屬片300,因而於金屬片300中形成複數個第一凹陷306。值得注意的是,第一凹陷306的底面係位於金屬片300內。進行非等向性蝕刻製程之後,金屬片300的上部會轉變成為複數個檯面(mesa)308,位於第一凹陷306之間。檯面308具有頂面302a,而頂面302a可充當成型中介層的內連線墊(interconnect pad)。
接著,請參考第11c圖,將一載板310固著於金屬片300的檯面308的頂面302a,覆蓋第一凹陷306,讓金屬片300的底面304暴露出來。接著,請參考第11d圖,可進行一微影製程和一非等向性蝕刻製程,以從金屬片300的底面304移除位於第一凹陷306下方的一部分金屬片300,因而於金屬片300中形成複數個第二凹陷312,其中第一凹陷306和第二凹陷312係分別彼此互連。形成第二凹陷312之後,金屬片300的下部會轉變成為複數個檯面314,位於第二凹陷312之間。檯面314具有底面304a,而底面304a可充當成型中介層的球墊(ball pad)。經過上述製程之後,形成複數個分離的金屬塊330,每一個金屬塊330係包括檯面308和檯面314。並且,檯面308的頂面302a可充當金屬塊330的頂面302a,而檯面314的底面304a可充當金屬塊330的底面304a。
值得注意的是,利用雙面蝕刻金屬片300的方式製造
的金屬塊330具有一體成型結構(all-in-one structure)。並且,相較於習知製程,具有一體成型結構的金屬塊330具有改善的剛性。因此,最終形成的成型中介層封裝可製造為更大的尺寸,以達到全尺寸平板封裝(full-size panel package)的要求。
接著,請參考第11e圖,成型材質316係從金屬片330的底面304a填入第一凹陷306和第二凹陷312。可使用例如化學機械研磨法(chemical mechanical polishing polishing,CMP)之一平坦化製程(planarization process),平坦化成型材質316,並讓金屬塊330的底面304a暴露出來。在本發明一實施例中,成型材質316可包括樹脂(resin)。上述成型材質316具有一體成型結構(all-in-one structure)。接著,請參考第11f圖,填入成型材質316之後,移除載板310。因此,形成由金屬塊330和成型材質316構成的一基板600b。並且,基板600b的每一個金屬塊330的剖面圖的中間處係具有一最大寬度。
值得注意的是,可形成包裹金屬塊的成型材質以進一步增強封裝剛性。因此,可不需使用習知製程之用以覆蓋成型中介層(molded builder interposer,MBI)和晶片的一封裝成型蓋(package mold cap)。在維持封裝剛性的同時可減少的封裝成型蓋製程成本。並且,本發明實施例係利用蝕刻金屬片之後填入成型材質之方式形成基板。相較於利用堆疊雙馬來醯亞胺-三氮雜苯樹脂(bismaleimide triacine,BT)形成的習知中介層基板,本發明實施例的中介層基板可減少製程成本。
接著,請參考第11g圖,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)、一物理氣相沉積法(physical vapor deposition,PVD)或一電鍍法(plating)之一沉積製程,於金屬塊330的頂面302a上形成一保護層318。然後,進行例如一雷射鑽孔法(laser drilling)之圖案化製程移除部分保護層318,以形成複數個穿過保護層318的開口320。金屬塊330的部分頂面302a會從保護層318的開口320暴露出來。
接著,請參考第11h圖,可利用例如一電鍍法之一沉積製程形成穿過開口320的複數個第一金屬介層孔插塞322。根據本發明的另一設計變化,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)或一物理氣相沉積法(physical vapor deposition,PVD)之一沉積製程,以及包括一微影製程和後續的一非等向性蝕刻製程之後續的一圖案化製程,形成穿過開口320的複數個第一金屬介層孔插塞322。在本發明其他實施例中,可於第一金屬介層孔插塞322上形成不同層別的數個重佈線圖案、介電層和金屬介層孔插塞,以於金屬塊330的頂面302a(也可充當成型中介層的內連線墊)上製造一內連線結構。舉例來說,可於第一金屬介層孔插塞322上形成如第1圖所示的第一重佈線層圖案208、第二重佈線層圖案214、介電層210、第一金屬介層孔插塞206和第二金屬介層孔插塞212。並且,可利用一沉積製程和一圖案化製程形成如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214。可利用一沉積製程形成如第
1圖所示的介電層210,且利用包括一微影製程和接續的一非等向性蝕刻製程之一圖案化製程形成穿過如第1圖所示的介電層210的開口。並且,可利用一沉積製程,於上述開口中形成如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212。
值得注意的是,可僅於成型中介層(molded builder interposer,MBI)的一側上形成上述內連線結構,而並非於成型中介層的兩側上形成上述內連線結構。並且,可個別地增加上述內連線結構的金屬層(例如重佈線層圖案),例如個別地增加一層、兩層或三層金屬層。再者,可利用適當的製程形成上述內連線結構的每一層。因此,可不需習知技術使用之雷射鑽孔製程的製程成本。相較於成型中介層的習知內連線結構,本發明實施例的內連線結構可降低各層的製程成本。
接著,請參考第11i圖,於保護層318上形成一防焊層324,並使第一金屬介層孔插塞322暴露出來。在本發明其他實施例中,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing)來形成防焊層324。
接著,形成複數個導電凸塊(例如第1圖所示的導電凸塊220),穿過防焊層324,以直接連接至第一金屬介層孔插塞322或如第1圖所示的其他重佈線層圖案。舉例來說,導電凸塊可為銅柱(Cu pillar)。接著,可利用一接合製程,將一晶片(例如第1圖所示的晶片222)接合至導電凸塊上,以連接至第一金屬介層孔插塞322或如第1圖所示的其他重佈線層圖案。因此,上述晶片可利用例如量產的熱壓法
(thermo-compression method)之一接合製程,不需任何焊球而接合至該些導電凸塊以連接至第一金屬介層孔插塞322或如第1圖所示的其他重佈線層圖案。相較於習知晶片的導電凸塊(焊球),本發明實施例的導電凸塊可降低製程成本。並且,相較於習知的晶片黏著技術(回焊製程),本發明實施例的晶片黏著技術可降低製程成本。
將晶片接合至第一金屬介層孔插塞322之前,可於防焊層324與晶片接合的一位置上設置一覆晶填充材質(例如第1圖所示的覆晶填充材質218)。在本發明一實施例中,覆晶填充材質可為固態(薄膜形狀)或液態。相較於將晶片接合至基板之後進行的習知覆晶填充材質製程,本發明實施例的覆晶填充材質製程可降低製程成本。
接著,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing),於金屬塊330的底面304a(亦即球墊)上形成一焊錫。之後,移除上述圖案化光阻,且進行一焊錫回焊製程(solder reflow process),以於金屬塊330的底面上(亦即印刷電路板側表面(PCB-side surface)形成複數個焊球(例如第1圖所示的焊球224)。經過上述製程之後,完成本發明一實施例之具有基板600b的成型中介層封裝。
值得注意的是,基板600b的印刷電路板側表面上沒有覆蓋任何防焊層。相較於在基板的晶片側表面和印刷電路板側表面兩者上進行的習知防焊層製程,本發明實施例的成型中介層封裝製程可減少防焊層的製程成本。
第12a-12f、13a-13g、14a-14g、15a-15g圖為本發明不同實施例之成型中介層封裝的製造方法的剖面圖。
第12a-12f圖為本發明另一實施例之成型中介層封裝的製造方法的剖面圖。上述圖式中的各元件如有與第11a-11i圖所示相同或相似的部分,則可參考前面的相關敍述,在此不做重複說明。並且,如第12a-12f圖所示之成型中介層封裝的製造方法也可稱為一無鈍化製程(no-passivation process)。如第12a圖所示,提供如第11a圖所示之一金屬片300之後,可進行一微影製程和一非等向性蝕刻製程,以從金屬片300的頂面302移除一部分金屬片300,因而於金屬片300中形成複數個第一凹陷326。值得注意的是,第一凹陷326的底面338係位於金屬片300內。進行非等向性蝕刻製程之後,金屬片300的上部會轉變成為複數個檯面328,位於第一凹陷326之間。檯面328具有頂面302a,而頂面302a可充當成型中介層的內連線墊。
接著,請參考第12b圖,成型材質331填入第一凹陷326,且覆蓋檯面328的頂面302a(內連線墊),亦即覆蓋金屬片300的頂面。在本發明一實施例中,成型材質331可包括樹脂(resin)。上述成型材質331具有一頂面332且為一體成型結構(all-in-one structure)。
接著,請參考第12c圖,可進行包括一微影製程和一非等向性蝕刻製程之一圖案化製程,移除部分成型材質331,以於成型材質331中形成複數個開口334,且形成複數個成型材質圖案331a,其中開口334係暴露出檯面328的頂面302a(亦即金屬片300的頂面),頂面302a可充當成型中介層的內連線墊。
接著,請參考第12d圖,可藉由例如一電鍍法之一沉積製程,於開口334中形成複數個第一金屬介層孔插塞336,且同時形成複數個第一重佈線層圖案342。在本發明其他實施例中,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)或一物理氣相沉積法(physical vapor deposition,PVD)之一沉積製程,以及包括一微影製程和接續的一非等向性蝕刻製程之後續的一圖案化製程,於開口334中形成複數個第一金屬介層孔插塞336。第一重佈線層圖案342分別形成於第一金屬介層孔插塞336之上。並且,第一重佈線層圖案342係延伸至成型材質圖案331a的部分頂面332a。在本發明其他實施例中,可於第一金屬介層孔插塞336上形成不同層別的數個重佈線圖案、介電層和金屬介層孔插塞,以於檯面328的頂面302a(也可充當成型中介層的內連線墊)上製造一內連線結構。舉例來說,可於第一金屬介層孔插塞336上形成如第1圖所示的第一重佈線層圖案208、第二重佈線層圖案214、介電層210、第一金屬介層孔插塞206和第二金屬介層孔插塞212。並且,可利用一沉積製程和一圖案化製程形成如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214。可利用一沉積製程形成如第1圖所示的介電層210,且利用包括一微影製程和後續的一非等向性蝕刻製程之一圖案化製程形成穿過如第1圖所示的介電層210的開口。並且,可利用一沉積製程,於上述開口中形成如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212。
接著,請參考第12e圖,進行一微影製程和一非等向性蝕刻製程,以從金屬片300的底面304移除一部分金屬片300,直到暴露出成型材質圖案331a的底面344為止。並且,具有檯面328的金屬片300會轉變成為複數個分離的金屬塊346。金屬塊346的底面304a可充當成型中介層的球墊。因此,形成由金屬塊346和成型材質圖案331a構成的基板600c。並且,如第12e圖所示,基板600c的每一個金屬塊346的剖面圖係具有一錐型輪廓。
接著,請參考第12f圖,於基板600c上(亦即成型材質331上)形成一防焊層340。防焊層340係覆蓋成型材質圖案331a,並使第一重佈線層圖案342暴露出來。在本發明其他實施例中,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing)來形成防焊層340。
後續的覆晶填充材質製程、晶片接合製程和焊球製程可與第11a-11i圖所述的覆晶填充材質製程、晶片接合製程和焊球製程相同或相似,在此不做重複說明。經過上述製程之後,係完成本發明一實施例之具有基板600c的成型中介層封裝。
第13a-13g圖為本發明又一實施例之成型中介層封裝的製造方法的剖面圖。上述圖式中的各元件如有與第11a-11i、12a-12f圖所示相同或相似的部分,則可參考前面的相關敍述,在此不做重複說明。並且,如第13a-13g圖所示之成型中介層封裝的製造方法也可稱為一單向蝕刻製程(single etch process)。如第13a圖所示,提供如第11a圖所示之一金屬片300之後,可將一載板350固著於金屬片
300的底面304。
接著,請參考第13b圖,可進行一微影製程和一非等向性蝕刻製程,以從金屬片300的頂面302移除一部分金屬片300,直到暴露出載板350為止,因而形成穿過該金屬片的複數個介層孔356。進行非等向性蝕刻製程之後,剩餘的金屬片300係轉變成為複數個彼此隔開的金屬塊358。每一個金屬塊358具有一頂面302a和一底面304a。金屬塊358的頂面302a可充當成型中介層的內連線墊(interconnect pad)。並且,金屬塊358的底面304a可充當成型中介層的球墊(ball pad)。
接著,請參考第13c圖,將一成型材質360填入第13b圖所示的介層孔356。然後,可使用例如化學機械研磨法(chemical mechanical polishing,CMP)或一回蝕刻製程(etching back process)之一平坦化製程,來平坦化成型材質360,並讓金屬塊358的頂面302a暴露出來。在本發明一實施例中,成型材質360可包括樹脂(resin)。上述成型材質360具有一體成型結構(all-in-one structure)。接著,請參考第13d圖,填入成型材質360之後,移除載板350。因此,形成由金屬塊358和成型材質360構成的一基板600d。並且,如第13d圖所示,基板600d的每一個金屬塊358的剖面圖係具有一錐型輪廓。
接著,請參考第13e圖,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)、一物理氣相沉積法(physical vapor deposition,PVD)或一電鍍法(plating)之一沉積製程,於金
屬塊358的頂面302a上形成一保護層362。然後,進行例如一雷射鑽孔法之圖案化製程移除部分保護層362,以形成穿過保護層362的複數個開口364。金屬塊358的部分頂面302a會從保護層362的開口364暴露出來。
接著,請參考第13f圖,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)或一物理氣相沉積法(physical vapor deposition,PVD)之一沉積製程,以及包括一微影製程和後續的一非等向性蝕刻製程之後續的一圖案化製程,形成穿過對應開口364的複數個第一金屬介層孔插塞366。在本發明其他實施例中,可於第一金屬介層孔插塞366上形成不同層別的數個重佈線圖案、介電層和金屬介層孔插塞,以於金屬塊358的頂面302a(也可充當成型中介層的內連線墊)上製造一內連線結構。舉例來說,可於第一金屬介層孔插塞366上形成如第1圖所示的第一重佈線層圖案208、第二重佈線層圖案214、介電層210、第一金屬介層孔插塞206和第二金屬介層孔插塞212。並且,可利用一沉積製程和一圖案化製程形成如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214。可利用一沉積製程形成如第1圖所示的介電層210,且利用包括一微影製程和後續的一非等向性蝕刻製程之一圖案化製程形成穿過如第1圖所示的介電層210的開口。並且,可利用一沉積製程,於上述開口中形成如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212。
接著,請參考第13g圖,於保護層362上形成一防焊
層368,並使第一金屬介層孔插塞366暴露出來。在本發明其他實施例中,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing)來形成防焊層368。
後續的覆晶填充材質製程、晶片接合製程和焊球製程可與第11a-11i圖所述的覆晶填充材質製程、晶片接合製程和焊球製程相同或相似,在此不做重複說明。經過上述製程之後,係完成本發明一實施例之具有基板600d的成型中介層封裝。
第14a-14g圖為本發明又一實施例之成型中介層封裝的製造方法的剖面圖。上述圖式中的各元件如有與第11a-11i、12a-12f、13a-13g圖所示相同或相似的部分,則可參考前面的相關敍述,在此不做重複說明。並且,如第14a-14g圖所示之成型中介層封裝的製造方法也可稱為一置球製程(ball drop process)。如第14a圖所示,提供一模具(mold chase)370。在本實施例中,模具370可由兩個彼此隔開的模板370a和370b構成。每一個模板370a和370b係分別具有複數個凹坑形凹陷372a和372b。並且,模板370a的凹坑形凹陷372a係分別面向模板370b的凹坑形凹陷372b。
接著,請參考第14b圖,其顯示於具有模板370a和370b的模具370中裝載複數個金屬塊374,且金屬塊374係位於模板370a和370b之間。如第14b圖所示,金屬塊374的上部和下部係分別被模板370a的凹坑形凹陷372a和模板370b的凹坑形凹陷372b夾緊。因此,相鄰兩個金屬塊374係藉由一間隙376彼此隔開。在本實施例中,金
屬塊374可為球狀的一體成型結構(all-in-one structure)。舉例來說,金屬塊374可為銅球。
接著,請參考第14c圖,於模具370的間隙376中填入一成型材質378,以包裹金屬塊374。值得注意的是,分別被模板370a的凹坑形凹陷372a和模板370b的凹坑形凹陷372b夾緊的金屬塊374的上部和下部並未被成型材質378覆蓋。在本發明一實施例中,成型材質378可包括樹脂(resin)。上述成型材質378具有一體成型結構(all-in-one structure)。接著,可移除模具370,使金屬塊374的上部和下部暴露出來。在本實施例中,金屬塊374的已暴露的上部和下部可為冠形(crown shaped)。
接著,請參考第14d圖,可利用一平坦化製程來平坦化金屬塊374,以移除超出成型材質378的一頂面和一底面而暴露出來的金屬塊374的上部和下部。因此,形成複數個金屬塊374a。在本發明一實施例中,平坦化製程可包括一化學機械研磨法(chemical mechanical polishing,CMP)。如第14d圖所示,金屬塊374a的頂面302係與成型材質378的頂面共平面,而金屬塊374a的底面304係與成型材質378的底面共平面。因此,形成由金屬塊374a和成型材質378構成的一基板600e。基板600e具有平坦化的頂面和平坦化的底面。並且,如第14d圖所示,基板600e的每一個金屬塊374a的剖面圖的中間處係具有一最大寬度。
接著,請參考第14e圖,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor
deposition,CVD)、一物理氣相沉積法(physical vapor deposition,PVD)或一電鍍法(plating)之一沉積製程,於基板600e的頂面(亦即成型材質378的頂面)上形成一保護層380。然後,進行例如一雷射鑽孔法之圖案化製程移除部分保護層380,以形成複數個穿過保護層380的開口382。基板600e的金屬塊374a的部分頂面302會從保護層380的開口382暴露出來。
接著,請參考第14f圖,可藉由例如一電鍍法之一沉積製程,於介層孔開口382中形成複數個第一金屬介層孔插塞384。在本發明其他實施例中,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)或一物理氣相沉積法(physical vapor deposition,PVD)之一沉積製程,以及包括一微影製程和接續的一非等向性蝕刻製程之後續的一圖案化製程,形成穿過開口382的複數個第一金屬介層孔插塞384。在本發明其他實施例中,可於第一金屬介層孔插塞384上形成不同層別的數個重佈線圖案、介電層和金屬介層孔插塞,以於基板600e的頂面302(也可充當基板600e的內連線墊)上製造一內連線結構。舉例來說,可於第一金屬介層孔插塞384上形成如第1圖所示的第一重佈線層圖案208、第二重佈線層圖案214、介電層210、第一金屬介層孔插塞206和第二金屬介層孔插塞212。並且,可利用一沉積製程和一圖案化製程形成如第1圖所示的第一重佈線層圖案208和第二重佈線層圖案214。可利用一沉積製程形成如第1圖所示的介電層210,且利用包括一微影製程和後續的一非等
向性蝕刻製程之一圖案化製程形成穿過如第1圖所示的介電層210的開口。並且,可利用一沉積製程,於上述開口中形成如第1圖所示的第一金屬介層孔插塞206和第二金屬介層孔插塞212。
接著,請參考第14g圖,於保護層380上形成一防焊層386,並使第一金屬介層孔插塞384暴露出來。在本發明其他實施例中,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing)來形成防焊層386。
後續的覆晶填充材質製程、晶片接合製程和焊球製程可與第11a-11i圖所述的覆晶填充材質製程、晶片接合製程和焊球製程相同或相似,在此不做重複說明。經過上述製程之後,係完成本發明又一實施例之具有基板600e的成型中介層封裝。
第15a-15g圖為本發明又一實施例之成型中介層封裝的製造方法的剖面圖。上述圖式中的各元件如有與第11a-11i、12a-12f、13a-13g、14a-14g圖所示相同或相似的部分,則可參考前面的相關敘述,在此不做重複說明。並且,如第15a-15g圖所示之成型中介層封裝的製造方法也可稱為一釘狀物嵌入製程(stud insert process)。如第15a圖所示,提供一模具(mold chase)400。在本實施例中,模具400可由兩個彼此隔開的模板400a和模板400b構成。每一個模板400a和400b係分別具有複數個槽形凹陷(slot-shaped recess)402a和402b。並且,模板400a的槽形凹陷402a係分別面向模板400b的槽形凹陷402b。
接著,請參考第15b圖,其顯示於模具400中裝載複
數個金屬塊404,且金屬塊404係位於模板400a和400b之間。如第15b圖所示,金屬塊404的上部和下部係分別被模板400a的槽形凹陷402a和模板400b的槽形凹陷402b夾緊。因此,相鄰兩個金屬塊404係藉由一間隙406彼此隔開。在本實施例中,金屬塊404可為釘狀的一體成型結構(all-in-one structure)。舉例來說,金屬塊404可為銅釘。
接著,請參考第15c圖,於模具400的間隙406中填入一成型材質408,以包裹金屬塊404。值得注意的是,被模板400a的槽形凹陷402a和模板400b的槽形凹陷402b夾緊的金屬塊404的上部和下部並未被成型材質408覆蓋。在本發明一實施例中,成型材質408可包括樹脂(resin)。上述成型材質408具有一體成型結構(all-in-one structure)。接著,可移除模具400,使金屬塊404的上部和下部暴露出來。在本實施例中,金屬塊404暴露出來的上部和下部可為槽形(slotted shaped)。
接著,請參考第15d圖,可利用一平坦化製程來平坦化金屬塊404,以移除位於成型材質408的一頂面和一底面上方的金屬塊404暴露出來的上部和下部。因此,形成複數個金屬塊404a。在本發明一實施例中,平坦化製程可包括一化學機械研磨法(chemical mechanical polishing,CMP)。如第15d圖所示,金屬塊404a的頂面302係與成型材質408的頂面共平面,而金屬塊404a的底面304係與成型材質408的底面共平面。因此,形成由金屬塊404a和成型材質408構成的一基板600f。基板600f具有平坦化的頂面和平坦化的底面。並且如第15d圖所示,基板600f的
每一個金屬塊404a的剖面圖的中間處係具有一最小寬度。
接著,請參考第15e圖,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)、一物理氣相沉積法(physical vapor deposition,PVD)或一電鍍法(plating)之一沉積製程,於基板600 f的頂面上形成一保護層410。然後,進行例如一雷射鑽孔法之圖案化製程移除部分保護層410,以形成複數個穿過保護層410的開口412。基板600f的金屬塊404a的部分頂面302會從保護層410的開口412暴露出來。
接著,請參考第15f圖,可藉由例如一電鍍法之一沉積製程,於介層孔開口412中形成複數個第一金屬介層孔插塞414。在本發明其他實施例中,可利用例如一旋轉塗佈法(spin-coating)、一化學氣相沉積法(chemical vapor deposition,CVD)或一物理氣相沉積法(physical vapor deposition,PVD)之一沉積製程,以及包括一微影製程和接續的一非等向性蝕刻製程之後續的一圖案化製程,形成穿過開口412的複數個第一金屬介層孔插塞414。在本發明其他實施例中,可於第一金屬介層孔插塞414上形成不同層別的數個重佈線圖案、介電層和金屬介層孔插塞,以於基板600f的頂面302(也可充當基板600f的內連線墊)上製造一內連線結構。舉例來說,可於第一金屬介層孔插塞414上形成如第1圖所示的第一重佈線層圖案208、第二重佈線層圖案214、介電層210、第一金屬介層孔插塞206和第二金屬介層孔插塞212。並且,可利用一沉積製程和一圖案化製程形成如第1圖所示的第一重佈線層圖案208和第
二重佈線層圖案214。可利用一沉積製程形成如第1圖所示的介電層210,且利用包括一微影製程和後續的一非等向性蝕刻製程之一圖案化製程形成穿過如第1圖所示的介電層210的開口。並且,可利用一沉積製程,於上述開口中形成如第1圖所示的第二金屬介層孔插塞212。
接著,請參考第15g圖,於保護層410上形成一防焊層416,並使第一金屬介層孔插塞414暴露出來。在本發明其他實施例中,可利用一圖案化光阻搭配電鍍製程或網版印刷製程(screen printing)來形成防焊層416。
後續的覆晶填充材質製程、晶片接合製程和焊球製程可與第11a-11i圖所述的覆晶填充材質製程、晶片接合製程和焊球製程相同或相似,在此不做重複說明。經過上述製程之後,係完成本發明又一實施例之具有基板600f的成型中介層封裝。
本發明實施例係提供一種成型中介層封裝及其製造方法。本發明實施例的成型中介層封裝可結合由金屬塊構成的一導線架(lead frame)和重佈線層(redistribution layer,RDL)技術,以減少雷射鑽孔製程(laser drilling)、圖案化製程(patterning)和電鍍製程(plating)的使用。並且,本發明實施例的成型中介層封裝的製造方法可使用銅柱製程技術(copper pillar technology)搭配熱壓接合法(thermo-compression bonding),以及一預先供應的覆晶填充材質(pre-applied underfill material)以達到具較低成本的晶片凸塊製程(chip bumping process)和晶片黏著製程(chip attaching process)。上述銅柱製程技術可增強封裝剛性。並
且,成型材質可整合於成型中介層封裝的基板內。因此,可不需使用傳送成型蓋(mold cap)的習知技術,以進一步降低製程成本。再者,成型中介層封裝的基板的製程可增加基板尺寸,以達到全尺寸平板的要求。因此,基板製程可具有更佳的面積使用率。另外,今日使用的成型中介層封裝的基板製程係由現有的導線架和成型材質供應商提供。因此,本發明實施例的成型中介層封裝可以成功地整合導線架和成型材質供應商。
雖然本發明已以實施例揭露如上,然其並非用以限定本揭露,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
200‧‧‧成型中介層
202、202a、202b、330、346、358、374、374a、404、404a‧‧‧金屬塊
204、316、331、360‧‧‧成型材質
205‧‧‧邊界
206、322、336、366、384、414‧‧‧第一金屬介層孔插塞
208、342‧‧‧第一重佈線層圖案
210‧‧‧介電層
212‧‧‧第二金屬介層孔插塞
214‧‧‧第二重佈線層圖案
216、324、340、368、386、416‧‧‧防焊層
218‧‧‧覆晶填充材質
220、250、258、262、270、272、274‧‧‧導電凸塊
222、244、246、248、264、266、268‧‧‧晶片
224‧‧‧焊球
232、236、304、304a、338‧‧‧底面
230、234、302、302a、332、332a‧‧‧頂面
238‧‧‧表面黏著元件
240‧‧‧散熱物
242‧‧‧成型蓋
252、254‧‧‧焊線
256、260‧‧‧半導體封裝
276‧‧‧矽中介層
280‧‧‧金屬島結構
282‧‧‧框型金屬加固物
284‧‧‧金屬鰭
288‧‧‧金屬加固條
290‧‧‧電源/接地墊
292‧‧‧內側壁
294‧‧‧外側壁
300‧‧‧金屬片
306、326‧‧‧第一凹陷
308、314、328‧‧‧檯面
310、350‧‧‧載板
312‧‧‧第二凹陷
318、362、380、410‧‧‧保護層
320、334、364、382、412‧‧‧開口
331、360‧‧‧成型材質
331a‧‧‧成型材質圖案
344‧‧‧底部
356‧‧‧介層孔
370、400‧‧‧模具
370a、370b、400a、400b‧‧‧模板
372a、372b‧‧‧凹坑形凹陷
376、406‧‧‧間隙
378、408‧‧‧成型材質
402a、402b‧‧‧槽形凹陷
500a、500b、500c、500d、500e、500f、500g、500h、500i‧‧‧成型中介層封裝
600、600a、600b、600c、600d、600e、600f‧‧‧基板
第1圖為本發明一實施例之成型中介層封裝的剖面圖。
第2-9圖為本發明不同實施例之成型中介層封裝的剖面圖。
第10圖為本發明一實施例之成型中介層封裝的基板的上視圖。
第11a-11i圖為本發明一實施例之成型中介層封裝的製造方法的剖面圖。
第12a-12f圖為本發明另一實施例之成型中介層封裝的製造方法的剖面圖。
第13a-13g圖為本發明又一實施例之成型中介層封裝
的製造方法的剖面圖。
第14a-14g圖為本發明又一實施例之成型中介層封裝的製造方法的剖面圖。
第15a-15g圖為本發明又一實施例之成型中介層封裝的製造方法的剖面圖。
200‧‧‧成型中介層
202‧‧‧金屬塊
204‧‧‧成型材質
206‧‧‧第一金屬介層孔插塞
208‧‧‧第一重佈線層圖案
210‧‧‧介電層
212‧‧‧第二金屬介層孔插塞
214‧‧‧第二重佈線層圖案
216‧‧‧防焊層
218‧‧‧覆晶填充材質
220‧‧‧導電凸塊
222‧‧‧晶片
224‧‧‧焊球
232、236‧‧‧底面
230、234‧‧‧頂面
500a‧‧‧成型中介層封裝
600‧‧‧基板
Claims (38)
- 一種成型中介層封裝,包括:複數個金屬塊;一成型材質,包裹該些金屬塊,使該些金屬塊的複數個底面暴露出來;一第一晶片,設置於該成型材質上,並連接至該些金屬塊的複數個頂面;以及複數個焊球,連接且接觸該些金屬塊的該些底面。
- 如申請專利範圍第1項所述之成型中介層封裝,更包括:一內連線結構,設置於該些金屬塊的該些頂面上,並電性連接至該些金屬塊和該第一晶片。
- 如申請專利範圍第1項所述之成型中介層封裝,更包括:一第一重佈線層圖案,設置於該成型材質和該第一晶片之間,且電性連接至該些金屬塊和該第一晶片。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括:一防焊層,設置於該第一重佈線層圖案和該第一晶片之間;以及複數個導電凸塊,延伸穿過該防焊層,且將該第一重佈線層圖案連接至該第一晶片。
- 如申請專利範圍第4項所述之成型中介層封裝,其中該些導電凸塊包括複數個焊球、複數個金屬柱或上述組合。
- 如申請專利範圍第4項所述之成型中介層封裝,其中該防焊層位於該成型材質之上。
- 如申請專利範圍第4項所述之成型中介層封裝,更包括一覆晶填充材質,設置於該防焊層和該第一晶片之間。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括:複數個第一金屬介層孔插塞,連接至該些金屬塊的該些頂面和該第一重佈線層圖案;一介電層,覆蓋該第一重佈線層圖案;複數個第二金屬介層孔插塞,穿過該介電層,且連接至該第一重佈線層圖案;以及一第二重佈線層圖案,連接至該些第二金屬介層孔插塞。
- 如申請專利範圍第8項所述之成型中介層封裝,更包括:一保護層,覆蓋該成型材質的一頂面,其中該些第一金屬介層孔插塞係延伸穿過該保護層。
- 如申請專利範圍第1項所述之成型中介層封裝,其中該些金屬塊的該些頂面係低於該成型材質的一頂面或與該成型材質的該頂面共平面,且該些金屬塊的該些底面係高於該成型材質的一底面或與該成型材質的該底面共平面。
- 如申請專利範圍第1項所述之成型中介層封裝,其中該成型材質的一底面未被任何防焊層覆蓋。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括與該第一晶片隔開的至少一電子元件,設置於該成型材質的一頂面上方,且連接至該第一重佈線層圖案。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括一散熱物,覆蓋該第一晶片和該第一重佈線層圖案。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括一成型蓋,覆蓋該第一晶片和該第一重佈線層圖案。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括:一第二晶片,設置於該第一晶片旁或該第一晶片上。
- 如申請專利範圍第15項所述之成型中介層封裝,其中該第二晶片藉由複數個導電接線或複數個導電凸塊連接至該第一重佈線層圖案。
- 如申請專利範圍第3項所述之成型中介層封裝,更包括:一半導體封裝,設置於該第一晶片旁或該第一晶片上。
- 如申請專利範圍第17項所述之成型中介層封裝,其中該半導體封裝藉由複數個導電凸塊連接至該第一重佈線層圖案。
- 如申請專利範圍第2項所述之成型中介層封裝,更包括:一第二晶片,設置於該第一晶片旁或該第一晶片上,其中該第二晶片藉由該中介層連接至該些金屬塊。
- 如申請專利範圍第1項所述之成型中介層封裝,其 中該些金屬塊的至少其中兩個係彼此接觸。
- 如申請專利範圍第1項所述之成型中介層封裝,更包括:一框型金屬加固物,穿過該成型材質,其中該框型金屬加固物的一內側壁係圍繞該些金屬塊。
- 如申請專利範圍第21項所述之成型中介層封裝,更包括:複數個金屬鰭,設置於該框型金屬加固物的一外側壁上,其中該些金屬鰭突出於該成型材質的一邊界。
- 如申請專利範圍第21項所述之成型中介層封裝,更包括:一金屬加固條,穿過該成型材質,連接至該框型金屬加固物的相鄰兩側。
- 如申請專利範圍第23項所述之成型中介層封裝,其中該些金屬塊、該框型金屬加固物和該金屬加固條由銅形成。
- 一種成型中介層封裝的製造方法,包括:提供一金屬片,該金屬片具有一頂面和一底面;進行一第一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,因而於該金屬片中形成複數個第一凹陷;將一載板固著於該金屬片的該頂面,覆蓋該些第一凹陷;進行一第二非等向性蝕刻製程,以從該金屬片的該底面移除位於該些第一凹陷下的一部分該金屬片,因而於該 金屬片中形成複數個第二凹陷,其中該些第一凹陷和該些第二凹陷係分別彼此互連;從該金屬片的該底面填入一成型材質至該些第一凹陷和該些第二凹陷,並使該金屬片的該底面暴露出來;移除該載板;於該金屬片的該頂面上形成一保護層,該保護層具有穿過該保護層的複數個開口;形成穿過該些開口的複數個第一金屬介層孔插塞;以及於該保護層上形成一防焊層,並使該些第一金屬介層孔插塞暴露出來。
- 一種成型中介層封裝的製造方法,包括:提供一金屬片,該金屬片具有一頂面和一底面;進行一第一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,因而於該金屬片中形成複數個第一凹陷;形成一成型材質,覆蓋該金屬片的該頂面,且填入該些第一凹陷;於該成型材質中形成複數個開口,其中該些開口暴露該金屬片的該頂面;於該些開口內形成複數個第一金屬介層孔插塞,且分別於該些第一金屬介層孔插塞上形成複數個第一重佈線層圖案;進行一第二非等向性蝕刻製程,以從該金屬片的該底面移除一部分該金屬片,直到暴露出該成型材質的一底 面,其中蝕刻後的該金屬片係轉變成為複數個金屬塊;以及於該成型材質上形成一防焊層,並使該些第一重佈線層圖案暴露出來。
- 如申請專利範圍第26項所述之成型中介層封裝的製造方法,更包括:形成複數個導電凸塊,穿過該防焊層,以直接連接至該些第一金屬介層孔插塞或該些第一重佈線層圖案;將一晶片接合至該些導電凸塊上,以連接至該些第一金屬介層孔插塞或該些第一重佈線層圖案;以及於該些金屬塊的複數個底面上形成複數個焊球。
- 如申請專利範圍第27項所述之成型中介層封裝的製造方法,更包括:設置一覆晶填充材質於該防焊層之與該晶片接合的位置上。
- 如申請專利範圍第28項所述之成型中介層封裝的製造方法,其中該覆晶填充材質為固態或液態。
- 一種成型中介層封裝的製造方法,包括下列步驟:提供一金屬片,該金屬片具有一頂面和一底面;將一載板固著於該金屬片的該底面;進行一非等向性蝕刻製程,以從該金屬片的該頂面移除一部分該金屬片,直到暴露出該載板,因而形成穿過該金屬片的複數個介層孔,其中蝕刻後的該金屬片係轉變成為複數個金屬塊;從該些介層孔中填入一成型材質,使該些金屬塊的該 頂面暴露出來;移除該載板;於該些金屬塊的該頂面上形成一保護層,該保護層具有複數個開口,穿過該保護層;形成穿過該些開口的複數個第一金屬介層孔插塞;以及於該保護層上形成一防焊層,並使該些第一金屬介層孔插塞暴露出來。
- 如申請專利範圍第30項所述之成型中介層封裝的製造方法,更包括:形成複數個導電凸塊,穿過該防焊層,以直接連接至該些第一金屬介層孔插塞;將一晶片接合至該些導電凸塊上,以連接至該些第一金屬介層孔插塞;以及於該些金屬塊的複數個底面上形成複數個焊球。
- 如申請專利範圍第31項所述之成型中介層封裝的製造方法,更包括於該防焊層之與該晶片接合的位置上設置一覆晶填充材質。
- 如申請專利範圍第32項所述之成型中介層封裝的製造方法,其中該覆晶填充材質為固態或液態。
- 一種成型中介層封裝的製造方法,包括下列步驟:提供一模具;於該模具中裝載複數個金屬塊,其中該些金屬塊的複數個上部和複數個下部分別被該模具夾緊; 於該模具中填入一成型材質,以包裹該些金屬塊;移除該模具,使該些金屬塊的該些上部和該些下部暴露出來;移除超出該成型材質的一頂面和一底面的暴露出來的該些金屬塊的該些上部和該些下部;於該成型材質的該頂面上形成一保護層,該保護層具有複數個開口,穿過該保護層;形成穿過該些開口的複數個第一金屬介層孔插塞;以及於該保護層上形成一防焊層,並使該些第一金屬介層孔插塞暴露出來。
- 如申請專利範圍第34項所述之成型中介層封裝的製造方法,其中該些金屬塊為球狀或釘狀。
- 如申請專利範圍第34項所述之成型中介層封裝的製造方法,更包括:形成複數個導電凸塊,穿過該防焊層,以直接連接至該些第一金屬介層孔插塞;將一晶片接合至該些導電凸塊上,以連接至該些第一金屬介層孔插塞;以及於該些金屬塊的複數個底面上形成複數個焊球。
- 如申請專利範圍第36項所述之成型中介層封裝的製造方法,更包括於該防焊層之與該晶片接合的位置上設置一覆晶填充材質。
- 如申請專利範圍第37項所述之成型中介層封裝的製造方法,其中該覆晶填充材質為固態或液態。
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CN103199077A (zh) | 2013-07-10 |
TWI470754B (zh) | 2015-01-21 |
US8957518B2 (en) | 2015-02-17 |
US9040359B2 (en) | 2015-05-26 |
US20140377913A1 (en) | 2014-12-25 |
US20140127865A1 (en) | 2014-05-08 |
US8859340B2 (en) | 2014-10-14 |
US20130168857A1 (en) | 2013-07-04 |
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