TW201314892A - 化合物半導體裝置及其製造方法 - Google Patents
化合物半導體裝置及其製造方法 Download PDFInfo
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- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
一種化合物半導體裝置之一實施例包括:一基材;一化合物半導體堆疊結構,其形成在該基材上方;及一非晶質絕緣膜,其形成在該基材與該化合物半導體堆疊結構之間。
Description
在此說明之實施例係有關於一種化合物半導體裝置及其製造方法。
具有一GaN層及一AlGaN層依序形成在一基材上之電子裝置(化合物半導體裝置)已有活躍之發展,其中該GaN層係作為一電子通道層使用。其中一化合物半導體裝置稱為以GaN為主之高電子遷移率電晶體(HEMT)。該以GaN為主之HEMT明智地利用一在AlGaN與GaN之間之異接面產生的高密度二維氣體(2DEG)。
該GaN之能帶間隙是高於Si(1.1eV)及GaAs(1.4eV)之能帶間隙的3.4eV。換言之,GaN具有一大擊穿電場強度。GaN亦具有一大飽和電子速度。因此,GaN是一極有希望用於可在高電壓下操作且可產生大輸出之化合物半導體裝置的材料。GaN亦非常有希望作為一用於有關節能之電源裝置的材料。
但是,製造一具有良好結晶度之GaN基材是非常困難的。主要習知解決方法是例如藉由異質磊晶成長在一Si基材上、一藍寶石基材、一SiC基材等上形成一GaN層、AlGaN層等。特別是對於Si基材而言,具有大直徑及高品質者可以低成本輕易地取得。因此,具有形成在該Si基材上之GaN
層及AlGaN層的結構正在積極研究中。這些研究可舉例如為了緩衝該GaN層及該AlGaN層之大晶格失配,相對於該Si基材提供例如AlN層之緩衝層。
但是,已了解的是藉由習知技術進一步改善崩潰電壓將是困難的。
[專利文獻1]日本公開專利公報第2007-258230號
[專利文獻2]日本公開專利公報第2010-245504號
本發明之一目的是提供一種可以進一步改善崩潰電壓之化合物半導體裝置及其製造方法。
依據該等實施例之一方面,一種化合物半導體裝置包括:一基材;一化合物半導體堆疊結構,其形成在該基材上;及一非晶質絕緣膜,其形成在該基材與該化合物半導體堆疊結構之間。
依據該等實施例之另一方面,一種製造一化合物半導體裝置之方法包括:在一基材上形成一非晶質絕緣膜;及在該非晶質絕緣膜上形成一化合物半導體堆疊結構。
第1圖是顯示SIMS之結果的圖表;第2圖是顯示依據一第一實施例之一化合物半導體裝置之結構的橫截面圖;第3A至3I圖是依序顯示製造依據第一實施例之化合物半導體裝置之一方法的橫截面圖;
第4圖是顯示依據一第二實施例之一化合物半導體裝置之結構的橫截面圖;第5圖是顯示依據一第三實施例之一化合物半導體裝置之結構的橫截面圖;第6圖是顯示依據一第四實施例之一獨立封裝體之圖;第7圖是顯示依據一第五實施例之一功率因子修正(PFC)電路之配線圖;第8圖是顯示依據一第六實施例之一電源供應設備之配線圖;第9圖是顯示依據一第七實施例之一高頻放大器之配線圖;第10A與10B圖是顯示實驗樣本之構形之橫截面圖;及第11圖是顯示實驗結果之圖表。
本發明已密集地研究為什麼在習知技術中產生改善崩潰電壓之困難的理由。其中一研究是有關於分析在該AlN緩衝層與該Si基材之間之界面的SIMS(二次離子質譜法)。結果顯示在第1圖中。由第1圖發現,在該Si基材中含有之Si及在該緩衝層中含有之Al互相擴散。如此擴散之原子係作為Si基材與緩衝層之摻雜物,且不利地影響絕緣效能。該現象被認為會使進一步改善在習知技術中之崩潰電壓是困難的。絕緣效能之劣化亦使漏電流更容易流動。因此,對於習知技術而言獲得令人滿意程度之可靠性被認為是困
難的。
以下將參照附圖詳細說明多數實施例。
以下將說明第一實施例。第2圖是顯示依據一第一實施例之一以GaN為主之HEMT(化合物半導體裝置)之結構的橫截面圖。
在該第一實施例中,如第2圖所示,一非晶質絕緣膜2係形成在例如一Si基材之基材1上。該非晶質絕緣膜2可以是一非晶質C、非晶質SiN或非晶質SiC之膜,其中一具有等於或大於2.5g/cm3之密度的非晶質碳膜是較佳的。該高密度非晶質碳膜具有一極佳絕緣效能。此外,即使碳由該高密度非晶質碳膜擴散進入後述之緩衝層中,該碳亦可用以補償可能在成長程序中發生之氮空位,使得該絕緣性能可被恢復。
一化合物半導體堆疊結構8係形成在該非晶質絕緣膜2上。該化合物半導體堆疊結構8包括一緩衝層3,一電子通道層4,一分隔層5,一電子供應層6及一蓋層7。該緩衝層3可以是例如,一大約100nm厚之AlN層。該電子通道層4可以是例如,未刻意以一雜質摻雜之一大約3μm厚之i-GaN層。該分隔層5可以是例如,未刻意以一雜質摻雜之一大約5nm厚之i-AlGaN層。該電子供應層6可以是例如,一大約30nm厚之n型AlGaN層。該蓋層7可以是例如,一大約10nm厚之n型GaN層。該電子供應層6及該蓋層7可例如,以大約5×1018/cm3之Si作為一n型雜質摻雜。
界定一元件區域之一元件隔離區域20係形成在該化合物半導體堆疊結構8中。在該元件區域中,開口10s與10d係形成在該蓋層7中。一源極電極11s係形成在該開口10s中,且一汲極電極11d係形成在該開口10d中。一絕緣膜12係形成為用以在該蓋層7上覆蓋該源極電極11s及該汲極電極11d。一開口13g係形成在該絕緣膜12中在一平面圖中在該源極電極11s與該汲極電極11d之間的一位置,且一閘極電極11g係形成在該開口13g中。一絕緣膜14形成為用以在該絕緣膜12上覆蓋該閘極電極11g。雖然用於該等絕緣膜12與14之材料沒有特別限制,但是,例如,可使用一Si氮化物膜。
在如此構成之以GaN為主之HEMT中,該非晶質絕緣膜2存在該基材1與該緩衝層3之間,且因此在該基材1中含有之原子(例如,Si)及在該3中含有之原子(例如,Al)之互相擴散被抑制。因此,該基材1及該緩衝層3造成非本質地產生電荷載體被抑制,且絕緣效能劣化亦被抑制。透過抑制絕緣效能之劣化,可改善崩潰電壓,且可抑制漏電流。此外,該非晶質絕緣膜2幾乎沒有被認為是崩潰電壓劣化之原因的晶界。又,由這觀點來看,該崩潰電壓亦被認為有改善。
該非晶質絕緣膜2之厚度沒有特別限制。但是,如果該非晶質絕緣膜2之厚度等於或小於1nm,有時無法獲得足夠之效果。因此,該非晶質絕緣膜2具有等於或大於1nm之厚度是較佳的。該非晶質絕緣膜2之厚度越厚,絕緣效能越好。但是超過2nm之非晶質絕緣膜2之厚度會降低在該化合
物半導體堆疊結構8中含有之化合物半導體層的結晶度。因此,該非晶質絕緣膜2之厚度宜等於或小於2nm。
該非晶質絕緣膜2在其整個部份上不一定是非晶質的,而是可包含微結晶等。結晶之比率越大,作為一洩漏路徑之晶界增加越多。因此,該非晶質部份宜等於或大於80體積%。
以下,將說明製造依據第一實施例之以GaN為主之HEMT(化合物半導體裝置)之一方法。第3A圖至第3I圖是依序顯示製造依據第一實施例之以GaN為主之HEMT(化合物半導體裝置)之一方法的橫截面圖。
首先,如第3A圖所示,在該基材1上形成該非晶質絕緣膜2。
雖然形成該非晶質絕緣膜2之方法沒有特別限制,但是一FCA(過濾陰極電弧)程序是較佳的。因為該FCA程序輕易地形成具有一等於或大於2.5g/cm3之大密度的非晶質碳膜。例如,可輕易地形成具有一可影響密度之等於或大於65%之大碳-碳鍵比率(sp3/sp2比率)的非晶質碳膜。依據該FCA程序,與一濺鍍程序及一化學蒸氣沈積法(CVD)程序比較,可得到與鑽石幾乎相當之較高密度。此外,該膜成長不需要加熱,使得該基材1不會因在膜成長程序中加壓而受損。
接著,如第3B圖所示,在該非晶質絕緣膜2上形成該化合物半導體堆疊結構8。在形成該化合物半導體堆疊結構8之程序中,例如,可藉由金屬有機汽相磊晶(MOVPE)形成
該緩衝層3,該電子通道層4,該分隔層5,該電子供應層6及該蓋層7。在形成該等化合物半導體層之程序中,可使用作為一Al源之三甲基鋁(TMA)氣體、作為一Ga源之三甲基鎵(TMG)氣體及作為一N源之氨(NH3)氣的一混合氣體。在該程序中,三甲基鋁氣體及三甲基鎵氣體之供給之開/關及流速係依據欲成長之化合物半導體層之組分適當地設定。一共用於所有化合物半導體層之氨氣之流速係設定為大約100ccm至10Lm。例如,成長壓力可調整為大約50Torr至300Torr,且成長溫度可調整為大約1000℃至1200℃。例如,在成長該等n型化合物半導體層之程序中,可藉由添加包含Si之SiH4氣體以一預定流速加入一混合氣體而將Si摻雜至該等化合物半導體層中。Si之劑量係調整為大約1×1018/cm3至1×1020/cm3,且為,例如,5×1018/cm3左右。
接著,如第3C圖所示,在該化合物半導體堆疊結構8中形成界定元件區域之元件隔離區域20。在形成該元件隔離區域20之程序中,例如,在該化合物半導體堆疊結構8上形成一光阻圖案以選擇性地暴露欲形成該元件隔離區域20之區域,且穿過作為一遮罩使用之光阻圖案植入例如Ar離子之離子。或者,可藉由使用一含氯氣體乾式蝕刻穿過作為一蝕刻遮罩使用之光阻圖案來蝕刻該化合物半導體堆疊結構8。
然後,如第3D圖所示,在該元件區域中之蓋層7中形成該等開口10s與10d。在形成該等開口10s與10d之程序中,例如,在該化合物半導體堆疊結構8上形成一光阻圖案以選
擇性地暴露該等開口10s與10d欲形成之區域,且穿過作為一遮罩使用之光阻圖案植入例如Ar離子之離子。或者,可藉由使用一含氯氣體乾式蝕刻穿過作為一蝕刻遮罩使用之光阻圖案來蝕刻該化合物半導體堆疊結構8。
接著,如第3E圖所示,在該開口10s中形成該源極電極11s,且在該開口10d中形成該汲極電極11d。該源極電極11s及該汲極電極11d可藉由,例如,一剝離程序形成。更詳而言之,形成一光阻圖案以暴露欲形成該源極電極11s及該汲極電極11d之區域,且藉由一蒸發程序同時使用,例如,該光阻圖案作為一成長遮罩而在整個表面上形成一金屬膜,接著與沈積在光阻圖案上之金屬膜之部份一起移除該光阻圖案。在形成該金屬膜之程序中,例如,可形成一大約20nm厚之Ta膜,且可接著形成一大約200nm厚之Al膜。接著,例如,在一氮環境中以400℃至1000℃(例如,以550℃)將該等金屬膜退火以藉此確保歐姆特性。
然後,如第3F圖所示,在整個表面上形成該絕緣膜12。該絕緣膜12宜藉由原子層沈積(ALD),電漿加強化學蒸氣沈積法(CVD),或濺鍍形成。
接著,如第3G圖所示,在該絕緣膜12中在平面圖中在該源極電極11s與該汲極電極11d之間的一位置形成該開口13g。
接著,如第3H圖所示,在該開口13g中形成該閘極電極11g。該閘極電極11g可藉由,例如,一剝離程序形成。更詳而言之,形成一光阻圖案以暴露欲形成該閘極電極11g之
一區域,且藉由一蒸發程序同時使用,例如,該光阻圖案作為一成長遮罩而在整個表面上形成一金屬膜,接著與沈積在光阻圖案上之金屬膜之部份一起移除該光阻圖案。在形成該金屬膜之程序中,例如,可形成一大約30nm厚之Ni膜,且可接著形成一大約400nm厚之Al膜。
然後,如第3I圖所示,在該絕緣膜12上方形成該絕緣膜14以覆蓋該閘極電極11g。
因此可製造依據第一實施例之以GaN為主之HEMT。
以下將說明一第二實施例。第4圖是顯示依據第二實施例之一以GaN為主之HEMT(化合物半導體裝置)之結構的橫截面圖。
與使該閘極電極11g與該化合物半導體堆疊結構8肖特基(Schottky)接觸之第一實施例不同,第二實施例在該閘極電極11g與該化合物半導體堆疊結構8之間採用該絕緣膜12,以便讓該絕緣膜12作為一閘極絕緣膜。簡言之,該開口13g未形成在該絕緣膜12中,且採用一MIS型結構。
又,如此構成之第二實施例,在存在該非晶質絕緣膜2之情形下,類似於第一實施例,成功地達成改善該崩潰電壓及抑制洩漏電流之效果。
用於該絕緣膜12之材料沒有特別限制,其中較佳例包括Si、Al、Hf、Zr、Ti、Ta及W之氧化物、氮化物或氧氮化物。特別理想的是氧化鋁。該絕緣膜12之厚度可以是2nm至200nm,且是例如,10nm左右。
以下將說明一第三實施例。第5圖是顯示依據第三實施例之一以GaN為主之HEMT(化合物半導體裝置)之結構的橫截面圖。
與使該源極電極11s及該汲極電極11d分別形成在該等開口10s與10d之第一實施例不同,在該第三實施例中未形成該等開口10s與10d。該源極電極11s及該汲極電極11d係形成在該蓋層7上。
又,如此構成之第三實施例,在存在該非晶質絕緣膜2之情形下,類似於第一實施例,成功地達成改善該崩潰電壓及抑制洩漏電流之效果。
一第四實施例係有關於包括一以GaN為主之HEMT之一化合物半導體裝置之一獨立封裝體。第6圖是顯示依據第四實施例之獨立封裝體之圖。
在第四實施例中,如第6圖所示,依據第一至第三實施例中任一實施例之化合物半導體裝置之一HEMT晶片210之一背面係使用一例如焊料之晶粒附接劑234固定在一焊墊(晶粒墊)233上。例如一Al線之一線235d之一端係接合於一與該汲極電極11d連接之汲極墊226d,且該線235d之另一端接合於一與該焊墊233一體結合之汲極引線232d。例如一Al線之一線235s之一端係接合於一與該源極電極11s連接之源極墊226s,且該線235s之另一端接合於一與該焊墊233分開之源極引線232s。例如一Al線之一線235g之一端係接合
於一與該閘極電極11g連接之閘極墊226g,且該線235g之另一端接合於一與該焊墊233分開之閘極引線232g。該焊墊233,該HEMT晶片210等係以一模製樹脂231封裝,以使該閘極引線232g之一部份,該汲極引線232d之一部份,及該源極引線232s之一部份向外突出。
該獨立封裝體可例如,藉由以下步驟製造。首先,該HEMT晶片210使用一例如焊料之晶粒附接劑234與一引線框之焊墊233接合。接著,利用該等線235g、235d與235s,分別藉由線結合,該閘極墊226g與該引線框之閘極引線232g連接,該汲極墊226d與該引線框之汲極引線232d連接,且該源極墊226s與該引線框之源極引線232s連接。利用該模製樹脂231模製係藉由一轉移模製程序實行。接著切除該引線框。
以下,將說明一第五實施例。該第五實施例係有關於一PFC(功率因子修正)電路,且該PFC電路裝設有包括一以GaN為主之HEMT之一化合物半導體裝置。第7圖是顯示依據第五實施例之PFC電路之配線圖。
該PFC電路250具有一開關元件(電晶體)251,一二極體252,一扼流線圈253,電容器254與255,一二極體電橋256,及一AC電源(AC)257。該開關元件251之汲極電極,該二極體252之陽極端子,及該扼流線圈253之一端子互相連接。該開關元件251之源極電極,該電容器254之一端子,及該電容器255之一端子互相連接。該電容器254之另一端子及
該扼流線圈253之另一端子互相連接。該電容器255之另一端子及該二極體252之陰極端子互相連接。一閘極驅動器係與該開關元件251之閘極電極連接。該AC257係透過該二極體電橋256連接在該電容器254之兩端子之間。一DC電源(DC)係連接在該電容器255之兩端子之間。在該實施例中,依據第一至第三實施例中任一實施例之化合物半導體裝置係作為該開關元件251使用。
在製造該PFC電路250之程序中,例如,該開關元件251係藉由例如焊料與該二極體252,扼流線圈253等連接。
以下,將說明一第六實施例。該第六實施例係有關於一電源供應設備,且該電源供應設備裝設有包括一以GaN為主之HEMT之一化合物半導體裝置。第8圖是顯示依據第六實施例之電源供應設備之配線圖。
該電源供應設備包括一高電壓一次側電路261,一低電壓二次側電路262,及一配置在該一次側電路261與該二次側電路262之間的變壓器263。
該一次側電路261包括依據第五實施例之PFC電路250,及連接在該PFC電路250中之電容器255之兩端子之間的一反相電路,且該反相電路可為,例如,一全橋式反相器電路260。該全橋式反相器電路260包括多數(在該實施例中為四個)開關元件264a、264b、264c與264d。
該二次側電路262包括多數(在該實施例中為三個)開關元件265a、265b與265c。
在該實施例中,依據第一至第三實施例中任一實施例之化合物半導體裝置係供PFC電路250之開關元件251使用,且供該全橋式反相器電路260之開關元件264a、264b、264c與264d使用。該PFC電路250及該全橋式反相器電路260係該一次側電路261之組件。另一方面,一以矽為主之一般MIS-FET(場效電晶體)係供該二次側電路262之開關元件265a、265b與265c使用。
以下,將說明一第七實施例。該第七實施例係有關於一高頻放大器,且該高頻放大器裝設有包括一以GaN為主之HEMT之一化合物半導體裝置。第9圖是顯示依據第七實施例之高頻放大器之配線圖。
該高頻放大器包括一數位預失真電路271,混合器272a與272b及一功率放大器273。
該數位預失真電路271補償輸入信號中之非直線畸變。該混合器272a混合該非直線畸變已被補償之輸入信號與一AC信號。該功率放大器273包括依據第一至第三實施例中任一實施例的化合物半導體裝置,且放大與AC信號混合之輸入信號。在該實施例之所示例子中,在該輸出側之信號可藉由該混合器272b在開關時與一AC信號混合,且可送回該數位預失真電路271。
供該化合物半導體堆疊結構使用之化合物半導體層之組分沒有特別限制,且可使用GaN、AlN、InN等。又,亦可使用GaN、AlN、InN等之混合結晶。例如,該緩衝層可
以是一AlGaN層,或一AlN層與一AlGaN層之堆疊層。
在該等實施例中,該基材可以是一碳化矽(SiC)基材,一藍寶石基材,一矽基材,一GaN基材,一GaAs基材等。該基材可以是導電,半絕緣及絕緣基材中任一種。
該閘極電極、該源極電極及該汲極電極之構形不限於在上述實施例中所述者。例如,它們可以由一單層構成。形成這些電極之方法不限於該剝離程序。在形成該源極電極及該汲極電極後退火可省略,只要可獲得該歐姆特性即可。該閘極電極可被退火。
用以構成該等獨立層之厚度及材料不限於在該等實施例中所述者。
以下,將說明由本發明人等為研究該非晶質絕緣膜之效果所進行的實驗。
在該實驗中,製備第10A與10B圖所示之兩種樣本31與32。就該樣本31而言,如第10A圖所示,在Si基材21上形成一200nm厚之AlN層23。就該樣本32而言,如第10B圖所示,在Si基材21上形成一2nm厚之非晶質碳膜作為非晶質絕緣膜22,且接著在該非晶質絕緣膜22上形成200nm厚之AlN層23。該AlN層23係藉由一MOVPE程序且使用TMA及NH3作為源氣體在1000℃之成長溫度及20kPa之成長壓力下形成。該非晶質絕緣膜22(非晶質碳膜)係藉由一FCA程序且使用一石墨目標作為一源材料以70A之電流及26V之電弧電壓形成。一用以形成該非晶質絕緣膜22(非晶質碳膜)之設備包括兩過濾器部份。該等過濾器部份係以一設置在其間之
含氟高絕緣樹脂互相絕緣。一可變DC電壓源係與該等過濾器部份連接。
在如上所述地製備該等樣本31與32後,在各樣本31與32之AlN層23之表面上形成一200nm厚之金電極。接著在該Si基材21之背面與該金電極之間連接一IV計,且測量該等樣本31與32之洩漏電流同時連續地掃測該電壓。結果顯示在第11圖中。可發現的是代表習知技術之樣本31之洩漏電流緊接在施加電壓後急劇地增加,且在大約20V產生介電崩潰。相反地,可發現的是代表一實施例之樣本32之洩漏電流非常和緩地增加,且即使電壓到達40V亦只顯示一低程度之洩漏電流,且沒有介電崩潰。
依據上述化合物半導體裝置等,可在該非晶質絕緣膜存在該基材與該化合物半導體堆疊結構之間的情形下,進一步提高崩潰電壓。
1‧‧‧基材
2‧‧‧非晶質絕緣膜
3‧‧‧緩衝層
4‧‧‧電子通道層
5‧‧‧分隔層
6‧‧‧電子供應層
7‧‧‧蓋層
8‧‧‧化合物半導體堆疊結構
10d,10s‧‧‧開口
11d‧‧‧汲極電極
11g‧‧‧閘極電極
11s‧‧‧源極電極
12‧‧‧絕緣膜
13g‧‧‧開口
14‧‧‧絕緣膜
20‧‧‧元件隔離區域
21‧‧‧Si基材
22‧‧‧非晶質絕緣膜
23‧‧‧AlN層
31,32‧‧‧樣本
210‧‧‧HEMT晶片
226d‧‧‧汲極墊
226g‧‧‧閘極墊
226s‧‧‧源極墊
231‧‧‧模製樹脂
232d‧‧‧汲極引線
232g‧‧‧閘極引線
232s‧‧‧源極引線
233‧‧‧焊墊(晶粒墊)
234‧‧‧晶粒附接劑
235d,235g,235s‧‧‧線
250‧‧‧PFC電路
251‧‧‧開關元件(電晶體)
252‧‧‧二極體
253‧‧‧扼流線圈
254,255‧‧‧電容器
256‧‧‧二極體電橋
257‧‧‧AC電源(AC)
260‧‧‧全橋式反相器電路
261‧‧‧一次側電路
262‧‧‧二次側電路
263‧‧‧變壓器
264a,264b,264c,264d‧‧‧開關元件
265a,265b,265c‧‧‧開關元件
271‧‧‧數位預失真電路
272a,272b‧‧‧混合器
273‧‧‧功率放大器
第1圖是顯示SIMS之結果的圖表;第2圖是顯示依據一第一實施例之一化合物半導體裝置之結構的橫截面圖;第3A至3I圖是依序顯示製造依據第一實施例之化合物半導體裝置之一方法的橫截面圖;第4圖是顯示依據一第二實施例之一化合物半導體裝置之結構的橫截面圖;第5圖是顯示依據一第三實施例之一化合物半導體裝置之結構的橫截面圖;
第6圖是顯示依據一第四實施例之一獨立封裝體之圖;第7圖是顯示依據一第五實施例之一功率因子修正(PFC)電路之配線圖;第8圖是顯示依據一第六實施例之一電源供應設備之配線圖;第9圖是顯示依據一第七實施例之一高頻放大器之配線圖;第10A與10B圖是顯示實驗樣本之構形之橫截面圖;及第11圖是顯示實驗結果之圖表。
1‧‧‧基材
2‧‧‧非晶質絕緣膜
3‧‧‧緩衝層
4‧‧‧電子通道層
5‧‧‧分隔層
6‧‧‧電子供應層
7‧‧‧蓋層
8‧‧‧化合物半導體堆疊結構
10d,10s‧‧‧開口
11d‧‧‧汲極電極
11g‧‧‧閘極電極
11s‧‧‧源極電極
12‧‧‧絕緣膜
13g‧‧‧開口
14‧‧‧絕緣膜
20‧‧‧元件隔離區域
Claims (20)
- 一種化合物半導體裝置,包含:一基材;一化合物半導體堆疊結構,其形成在該基材上方;及一非晶質絕緣膜,其形成在該基材與該化合物半導體堆疊結構之間。
- 如申請專利範圍第1項之化合物半導體裝置,其中該非晶質絕緣膜是一非晶質碳膜。
- 如申請專利範圍第2項之化合物半導體裝置,其中該非晶質絕緣膜之碳-碳鍵比率係為65%或大於sp3/sp2比率。
- 如申請專利範圍第1至3項中任一項之化合物半導體裝置,其中該非晶質絕緣膜之厚度係等於或大於1nm。
- 如申請專利範圍第1至3項中任一項之化合物半導體裝置,其中該非晶質絕緣膜之厚度係等於或小於2nm。
- 如申請專利範圍第1至3項中任一項之化合物半導體裝置,其中該化合物半導體堆疊結構包含一形成在該非晶質絕緣膜上方之緩衝層。
- 如申請專利範圍第6項之化合物半導體裝置,其中該基材含有矽,且該緩衝層含有鋁。
- 如申請專利範圍第7項之化合物半導體裝置,其中該緩衝層是一氮化鋁層。
- 如申請專利範圍第6項之化合物半導體裝置,其中該化合物半導體堆疊結構包含: 一電子通道層,其形成在該緩衝層上方;及一電子供應層,其形成在該電子通道層上方。
- 如申請專利範圍第9項之化合物半導體裝置,更包含形成在該電子供應層上或上方之一閘極電極,一源極電極及一汲極電極。
- 一種電源供應設備,包含一化合物半導體裝置,且該化合物半導體裝置包含:一基材;一化合物半導體堆疊結構,其形成在該基材上方;及一非晶質絕緣膜,其形成在該基材與該化合物半導體堆疊結構之間。
- 一種放大器,包含一化合物半導體裝置,且該化合物半導體裝置包含:一基材;一化合物半導體堆疊結構,其形成在該基材上方;及一非晶質絕緣膜,其形成在該基材與該化合物半導體堆疊結構之間。
- 一種製造一化合物半導體裝置之方法,包含:在一基材上方形成一非晶質絕緣膜;及在該非晶質絕緣膜上方形成一化合物半導體堆疊結構。
- 如申請專利範圍第13項之製造一化合物半導體裝置之 方法,其中該非晶質絕緣膜是一非晶質碳膜。
- 如申請專利範圍第13或14項之製造一化合物半導體裝置之方法,其中該非晶質絕緣膜係藉由一過濾陰極電弧(FCA)程序形成。
- 如申請專利範圍第13或14項之製造一化合物半導體裝置之方法,其中形成該化合物半導體堆疊結構之步驟包含在該非晶質絕緣膜上方形成一緩衝層。
- 如申請專利範圍第16項之製造一化合物半導體裝置之方法,其中該基材含有矽,且該緩衝層含有鋁。
- 如申請專利範圍第17項之製造一化合物半導體裝置之方法,其中該緩衝層是一氮化鋁層。
- 如申請專利範圍第16項之製造一化合物半導體裝置之方法,其中形成該化合物半導體堆疊結構之步驟包含:在該緩衝層上方形成一電子通道層;及在該電子通道層上方形成一電子供應層。
- 如申請專利範圍第19項之製造一化合物半導體裝置之方法,更包含在該電子供應層上或上方形成一閘極電極,一源極電極及一汲極電極。
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