TW201216414A - Methods for in-situ passivation of silicon-on-insulator wafers - Google Patents
Methods for in-situ passivation of silicon-on-insulator wafers Download PDFInfo
- Publication number
- TW201216414A TW201216414A TW100123193A TW100123193A TW201216414A TW 201216414 A TW201216414 A TW 201216414A TW 100123193 A TW100123193 A TW 100123193A TW 100123193 A TW100123193 A TW 100123193A TW 201216414 A TW201216414 A TW 201216414A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- chamber
- insulating layer
- split surface
- split
- Prior art date
Links
Classifications
-
- H10P90/1916—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H10P95/11—
-
- H10W10/181—
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
- Pressure Welding/Diffusion-Bonding (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US35999810P | 2010-06-30 | 2010-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW201216414A true TW201216414A (en) | 2012-04-16 |
Family
ID=44653366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100123193A TW201216414A (en) | 2010-06-30 | 2011-06-30 | Methods for in-situ passivation of silicon-on-insulator wafers |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8859393B2 (enExample) |
| EP (1) | EP2589075A2 (enExample) |
| JP (1) | JP5989642B2 (enExample) |
| KR (3) | KR102083688B1 (enExample) |
| CN (1) | CN102959697A (enExample) |
| SG (1) | SG186853A1 (enExample) |
| TW (1) | TW201216414A (enExample) |
| WO (1) | WO2012001659A2 (enExample) |
Families Citing this family (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427097B (zh) * | 2011-11-23 | 2014-05-07 | 中国科学院物理研究所 | 一种硅的氧化钝化方法及钝化装置 |
| US8747598B2 (en) | 2012-04-25 | 2014-06-10 | Gtat Corporation | Method of forming a permanently supported lamina |
| US10079170B2 (en) | 2014-01-23 | 2018-09-18 | Globalwafers Co., Ltd. | High resistivity SOI wafers and a method of manufacturing thereof |
| US9899499B2 (en) | 2014-09-04 | 2018-02-20 | Sunedison Semiconductor Limited (Uen201334164H) | High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss |
| US9853133B2 (en) * | 2014-09-04 | 2017-12-26 | Sunedison Semiconductor Limited (Uen201334164H) | Method of manufacturing high resistivity silicon-on-insulator substrate |
| EP3221884B1 (en) | 2014-11-18 | 2022-06-01 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof |
| EP4170705A3 (en) | 2014-11-18 | 2023-10-18 | GlobalWafers Co., Ltd. | High resistivity semiconductor-on-insulator wafer and a method of manufacturing |
| US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
| EP3367424B1 (en) | 2015-03-03 | 2022-10-19 | GlobalWafers Co., Ltd. | Charge trapping polycrystalline silicon films on silicon substrates with controllable film stress |
| WO2016149113A1 (en) | 2015-03-17 | 2016-09-22 | Sunedison Semiconductor Limited | Thermally stable charge trapping layer for use in manufacture of semiconductor-on-insulator structures |
| US9881832B2 (en) | 2015-03-17 | 2018-01-30 | Sunedison Semiconductor Limited (Uen201334164H) | Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof |
| EP3739620B1 (en) | 2015-06-01 | 2022-02-16 | GlobalWafers Co., Ltd. | A silicon germanium-on-insulator structure |
| CN107667416B (zh) | 2015-06-01 | 2021-08-31 | 环球晶圆股份有限公司 | 制造绝缘体上半导体的方法 |
| SG10201913407TA (en) | 2015-11-20 | 2020-03-30 | Globalwafers Co Ltd | Manufacturing method of smoothing a semiconductor surface |
| US10468294B2 (en) | 2016-02-19 | 2019-11-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface |
| US9831115B2 (en) | 2016-02-19 | 2017-11-28 | Sunedison Semiconductor Limited (Uen201334164H) | Process flow for manufacturing semiconductor on insulator structures in parallel |
| WO2017142849A1 (en) | 2016-02-19 | 2017-08-24 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a buried high resistivity layer |
| JP7002456B2 (ja) | 2016-03-07 | 2022-01-20 | グローバルウェーハズ カンパニー リミテッド | 低温流動性酸化物層を含む半導体オンインシュレータ構造およびその製造方法 |
| US11848227B2 (en) | 2016-03-07 | 2023-12-19 | Globalwafers Co., Ltd. | Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment |
| WO2017155808A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof |
| WO2017155806A1 (en) | 2016-03-07 | 2017-09-14 | Sunedison Semiconductor Limited | Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof |
| SG11201810486VA (en) | 2016-06-08 | 2018-12-28 | Globalwafers Co Ltd | High resistivity single crystal silicon ingot and wafer having improved mechanical strength |
| US10269617B2 (en) | 2016-06-22 | 2019-04-23 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising an isolation region |
| CN110178211B (zh) | 2016-10-26 | 2022-12-13 | 环球晶圆股份有限公司 | 具有增强电荷俘获效率的高电阻率绝缘体上硅衬底 |
| US10468295B2 (en) | 2016-12-05 | 2019-11-05 | GlobalWafers Co. Ltd. | High resistivity silicon-on-insulator structure and method of manufacture thereof |
| EP3653761B1 (en) | 2016-12-28 | 2024-02-28 | Sunedison Semiconductor Limited | Silicon wafers with intrinsic gettering and gate oxide integrity yield |
| FR3061988B1 (fr) * | 2017-01-13 | 2019-11-01 | Soitec | Procede de lissage de surface d'un substrat semiconducteur sur isolant |
| JP7034186B2 (ja) | 2017-07-14 | 2022-03-11 | サンエディソン・セミコンダクター・リミテッド | 絶縁体上半導体構造の製造方法 |
| US10916416B2 (en) * | 2017-11-14 | 2021-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor wafer with modified surface and fabrication method thereof |
| JP7160943B2 (ja) | 2018-04-27 | 2022-10-25 | グローバルウェーハズ カンパニー リミテッド | 半導体ドナー基板からの層移転を容易にする光アシスト板状体形成 |
| EP4210092A1 (en) | 2018-06-08 | 2023-07-12 | GlobalWafers Co., Ltd. | Method for transfer of a thin layer of silicon |
| US11296277B2 (en) | 2018-10-16 | 2022-04-05 | Samsung Electronics Co., Ltd. | Variable resistance memory device having an anti-oxidation layer and a method of manufacturing the same |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3836786A (en) * | 1967-01-04 | 1974-09-17 | Purification Sciences Inc | Dielectric liquid-immersed corona generator |
| CA1030102A (en) | 1972-08-17 | 1978-04-25 | Purification Sciences Inc. | Dielectric liquid-immersed corona generator |
| US5000113A (en) * | 1986-12-19 | 1991-03-19 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
| JPH07118522B2 (ja) * | 1990-10-24 | 1995-12-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 基板表面を酸化処理するための方法及び半導体の構造 |
| JPH05259153A (ja) * | 1992-03-12 | 1993-10-08 | Fujitsu Ltd | シリコン酸化膜の製造方法と製造装置 |
| JPH0766195A (ja) * | 1993-06-29 | 1995-03-10 | Sumitomo Sitix Corp | シリコンウェーハの表面酸化膜形成方法 |
| CN1104264A (zh) * | 1994-09-02 | 1995-06-28 | 复旦大学 | 热壁密装低温低压淀积二氧化硅薄膜技术 |
| US5880029A (en) * | 1996-12-27 | 1999-03-09 | Motorola, Inc. | Method of passivating semiconductor devices and the passivated devices |
| US5972802A (en) * | 1997-10-07 | 1999-10-26 | Seh America, Inc. | Prevention of edge stain in silicon wafers by ozone dipping |
| JP3153162B2 (ja) * | 1997-10-08 | 2001-04-03 | 松下電子工業株式会社 | シリコン酸化膜の形成方法 |
| JP4379943B2 (ja) * | 1999-04-07 | 2009-12-09 | 株式会社デンソー | 半導体基板の製造方法および半導体基板製造装置 |
| US20020175143A1 (en) * | 2001-05-22 | 2002-11-28 | Seh America, Inc. | Processes for polishing wafers |
| US6833322B2 (en) * | 2002-10-17 | 2004-12-21 | Applied Materials, Inc. | Apparatuses and methods for depositing an oxide film |
| JP4614416B2 (ja) | 2003-05-29 | 2011-01-19 | 日東電工株式会社 | 半導体チップの製造方法およびダイシング用シート貼付け装置 |
| JP2007149723A (ja) | 2005-11-24 | 2007-06-14 | Sumco Corp | 貼り合わせウェーハの製造方法 |
| US7939424B2 (en) * | 2007-09-21 | 2011-05-10 | Varian Semiconductor Equipment Associates, Inc. | Wafer bonding activated by ion implantation |
| SG161151A1 (en) * | 2008-10-22 | 2010-05-27 | Semiconductor Energy Lab | Soi substrate and method for manufacturing the same |
| WO2010062852A1 (en) | 2008-11-26 | 2010-06-03 | Memc Electronic Materials, Inc. | Method for processing a silicon-on-insulator structure |
-
2011
- 2011-06-16 US US13/162,122 patent/US8859393B2/en active Active
- 2011-06-30 SG SG2012096020A patent/SG186853A1/en unknown
- 2011-06-30 CN CN2011800328260A patent/CN102959697A/zh active Pending
- 2011-06-30 TW TW100123193A patent/TW201216414A/zh unknown
- 2011-06-30 WO PCT/IB2011/052903 patent/WO2012001659A2/en not_active Ceased
- 2011-06-30 EP EP11757935.9A patent/EP2589075A2/en not_active Withdrawn
- 2011-06-30 JP JP2013517642A patent/JP5989642B2/ja active Active
- 2011-06-30 KR KR1020137002599A patent/KR102083688B1/ko active Active
- 2011-06-30 KR KR1020187009456A patent/KR20180037326A/ko not_active Ceased
- 2011-06-30 KR KR1020197020821A patent/KR20190087668A/ko not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| KR20130129897A (ko) | 2013-11-29 |
| KR20180037326A (ko) | 2018-04-11 |
| JP5989642B2 (ja) | 2016-09-07 |
| KR102083688B1 (ko) | 2020-03-02 |
| CN102959697A (zh) | 2013-03-06 |
| KR20190087668A (ko) | 2019-07-24 |
| US8859393B2 (en) | 2014-10-14 |
| SG186853A1 (en) | 2013-02-28 |
| WO2012001659A3 (en) | 2012-03-01 |
| US20120003814A1 (en) | 2012-01-05 |
| EP2589075A2 (en) | 2013-05-08 |
| JP2013534731A (ja) | 2013-09-05 |
| WO2012001659A2 (en) | 2012-01-05 |
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