TW201115734A - Nanowire mesh FET with multiple threshold voltages - Google Patents
Nanowire mesh FET with multiple threshold voltages Download PDFInfo
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- TW201115734A TW201115734A TW099114781A TW99114781A TW201115734A TW 201115734 A TW201115734 A TW 201115734A TW 099114781 A TW099114781 A TW 099114781A TW 99114781 A TW99114781 A TW 99114781A TW 201115734 A TW201115734 A TW 201115734A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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Description
201115734 、發明說明: 【發明所屬之技術領域】 本發明與奈米線式元件(nanowore-based device)有 關,且更特別是與多臨界電壓(Vt)之奈米線式場效電晶體 (field-effect transistor,FET)及其製造方法有關。 【先前技術】 閘極全圍繞(Gate-all-around,GAA)奈米線通道 (nanowire channel)場效電晶體可於目前平面化互補金屬 氧化物半導體(Complementary-Metal-Oxide Semiconductor,CMOS)技術下進行特徵尺寸變化。在其基 本形式中,一奈米線式FET包括一源極區、一汲極區以及 在該源極與汲極區之間的奈米線通道。圍繞奈米線通道之 閘極調整通過源極與汲極區間之奈米線通道的電子流。 然而’特徵尺寸變1化(feature size scaling)是對現今高 性忐、尚功率電子元件之挑戰。舉例而言,電池啟動之行 ,裝置^例如膝上型電腦)。在未適當提供電力管理時,正 常的計算運作會快速消耗電力儲存。 士在1二電力管理策略都存在於晶片層級(chip ievel),例
dd的此範圍間完善校正。此外,也存
之設計,以及確保 201115734 在著當這些工作未被正確執行時可能 計循環相關的成本的風險。 ,、更新。又 因此,需要允許功率消耗調節之可變化尺 FET的設計。 不木 【發明内容】 本發明,供了奈米線式場效電晶體及其製造方法。在 本發明之-態樣中,所提供之FET具有垂直取向於一堆疊 中之複數個元件層(device iayer),各元件層具有一源極 區、一汲極區以及連接該源極區與該汲極區之複數個奈米 線通道,其中該等元件層之一或多者係配置以具有與一或 多個其他元件層不同之臨界電壓;以及圍_等奈^線通 道之一閘極,其共用(comm〇n)於各該元件層。 在本發明之另一態樣中,提供了一種製造FET的方 法,其具有下列步驟。形成複數個垂直取向於一堆疊中之 兀件層,各元件層具有一源極區、一汲極區以及連接該源 極區與該汲極區之複數個奈米線通道。該等元件層之一或 多者係配置為具有與一或多個其他元件層不同之臨界電 壓。形成圍繞該等奈米線通道之一閘極,其係共用於各該 元件層。 參照下列實施方式與如附圖式,即可完全瞭解本發明 以及本發明之進一步特徵與優勢。 【實施方式】 本申請案是有關於共有的美國專利申請號 12/371,943 ’ 才示為「Nanowire Mesh Device and Method of
Fabricating Same」,指定為代理人參考號 FIS920080350US卜申請日為2〇〇9年2月丨7日,其内容 201115734 於此以參考文件方式併入。 圖1至目12係、說明用於製造一種具有多個臨界電壓 (vt)之閘極全圍繞奈錄式場效電晶體的示例方法的示意 圖如下文所說明,該製程係利用鑲喪間極製程(damascene gate Pr0cess)來建構與閘極自對齊之源極/汲極區。 本發明目標之-在於提供具有多個「可微調㈣·)」 Vt之奈米線式場效電晶體及其製造枝。因可於元件中調 vt’即可有利地節省電力而不會遭遇—般會遇到的性能 衰減(perfonnancedegradation)。僅舉例而言,含具有兩個 =同Vt(例如vt2<Vtl)之場效電晶體的電子元件在低功率 核式(當供,電壓Vdd為Vt2<Vdd<Vtl時)與高功率模式(當 vdd增加至高於vtl時)中皆可有效率地運作。 圖1係一截面圖,其說明了用於FET製造之初始結構 1〇〇。為形成初始結構100,利用淺溝渠隔離(shall〇w Trench Isolation ’ STI)來定義絕緣層上覆矽 (Sil^〇n-〇n-insuiator,s〇I)晶圓中之主動區。意即,提供 一晶圓102,其具有一位於埋藏氧化物⑺虹丨以〇xide,Β〇χ)
層106上方之s〇I層丨04。根據一示範具體實施例,s〇I 層104 有之尽度係介於約5奈米(Nan〇meter,nm)至約 20nm。SOI晶圓通常也包括其他層,例如基板’其並未繪 示於圖中。BOX層1〇6可包含任何適當之絕緣材料,包 括但不限於介電質材料,如二氧化矽(Si02)。圖1說明的 是單一主動區的形成’然應知也可於單一晶圓中形成複數 個主動區。 接著在晶圓上以垂直堆疊形式形成矽(s丨)與犧牲層 (sacrificial |ayer)之交錯序列(例如磊晶成長),以s〇丨層丨〇4 作為序列/堆疊中的第—層。具體而言,從SOI層丨04開 始向上’第一犧牲層丨〇8係磊晶成長於SO丨層丨04上方。 201115734 犧牲層108包含-結晶材料’其可相對於&而被選 擇性蝕刻,例如矽鍺化物(silic〇n germanium , SiGe)。犧牲 層108可含有尚濃度之摻質(d〇pant),當其注入藉由後 續製程中所進行之退火)時,係產生n型或p型Si。舉例 而言,磷(P)或砷(As)係一般的n型摻質,而硼(B)係一般 的P型摻質。使用之摻質濃度係介於約1χ1〇!9個原子每= 方公分(atom/cm3)至約ixl022 at〇m/cm3。摻雜(d〇p㈣係於 原位(in-situ)執行(亦即在犧牲層1〇8成長期間併入摻質” 或非原位(ex-situ)執行(在成長犧牲層1〇8之後利用如離子 佈植等方式進行),其巾當相㈣n型與p型_區需於 同-層中形成相鄰的NFET與PFET時,則以非原位摻雜 較佳。 ^ 在犧牲層1G8上方可蟲晶成長—選擇性未摻雜結晶石夕 層110。此外,可視需要以交錯方式在矽層11〇的頂部磊 晶成長一或多層其他犧牲層及/或結晶矽層,其中所述其他 犧牲層的性質係與犧牲層刚相同,而其他結晶石夕層^性 質係與石夕層110相同。為利於說明與描述,在石夕層11〇頂 部亡係繪示一層其他犧牲層112 ;然而,如上所述,這些 層是非必要的,也可推想出不存在這些層的具體實施例。 此外丄雖未加以綠示,然也可能存在更多或較少層。根據 一不範具體實施例,犧牲層1G8# 112皆經摻 同。 曰在圖1所示之示範配置中,接著在犧牲層112上方磊 晶成長一結晶矽層114。如下文詳細說明,矽層U4係較 佳為比SO丨層104和矽層丨10薄。改變矽層U4的厚度, 因而改變其+所形成之奈米線通道的厚度,其使得在同一 FET元件中呼因量子侷限效應q⑽丨也丨⑴e汗eCt) 而出現多個根據一示範具體實施例,FE丁元件係配置 201115734 以具有第一臨界電壓vtl與第二臨界電壓Vt2(雙v 亦即其因使用兩種不同元件層厚度而產生。 t 广 各犧牲層係藉由遙晶成長製程所沉積而成,因此 -犧牲層包含-單晶材料。根據—示範具體實施例 犧牲層具有之厚度係介於約5nm至約2Gnm。 容降至最低,各犧牲層的厚度應盡量為小.,同時保留 夠空間以符合後續製程中—旦移除齡層 同樣地,各梦層也藉由^成長製程沉積而成因 t各㈣也包含-單晶材料。根據—示範具體 石^層則具有之厚度係介於約5nm至約20nm(亦即與SOI 層1〇4相同厚度)。如上所述,石夕層114比s〇i層刚和 矽層m更薄。根據一示範具體實施例,石夕層ιΐ4 ^度係介於約lrnn至約1()nm。較薄_層叫係藉由調 I儿積材料量及/或研磨或_該層至所需厚度而產生。 一示範具體實施例,係利_成長製程來形成 夕層與犧牲層兩者。蟲晶成長係於賴氏_度以下執 行二例如低於約攝氏650度。該製程可在不破壞直空下, =-層成長之間執行,或者是可破壞層間真㈣進行韻 介地,—如犧牲層之非原位摻雜。無論是否破壞層間真 工 Γ7連5層形成之岐好是騎-清除步驟(pu⑼ = 母一石夕層與犧牲層中所使用的成長壓力係# 丨石曰托耳(torr),例如低於約50托耳。注意由於這歧 成長參數之故,每—矽層與犧牲層的厚度可於不 起過約5%的範圍令變化。如上所述,在後續製程中,# 米tLC將幵/成;^石夕層_,且各犧牲層的厚度將決定Z钟 方向上相鄰奈米線通道之間的距離。 在石夕層丨丨4上方沉積—第—硬遮罩(hard_丨〈)丨丨6。槔 201115734 據一示範具體實施例’硬遮罩U6包含一氧化物,例如 Si〇2(二氧化矽)且其係利用化學氣相沉積(Chemical Vap〇r
Deposition ’ CVD)或電漿增強 CVD(Plasma Enhanced CVD,PECVD)而沉積在矽層114上。 STI係用以平面化及隔離對晶圓主動區之矽/犧牲層 堆疊。STI涉及一般的微影與蝕刻製程,其係該領域技術 人士所習知,因而不在此進一步說明。STI —般係與奈米 特徵尺寸範圍之製程技術一起應用。在堆疊之一或多個側 壁鄰近處係利用沉積製程而形成一氮化物襯層(nitride liner)l 18 ’例如利用CVD、PECVD或原子層沉積(Atomic Layer Deposition,ALD)。現形成於晶圓主動區中之堆疊 在後續製程中係用以形成FET元件的源極與汲極區以及 奈米線通道。在堆疊中各種層的排列定義了奈米線通道在 z軸方向上的位置。 接著在堆疊上沉積一第二硬遮罩120。根據一示範具 體貫施例,硬遮罩120包含一氮化物(例如氮化矽(SiN))且 其係利用低壓化學氣相沉積(Loyv-Pressure Chemical Vapor Deposition ’ LPCVD)而沉積至約Ι5ηηι至約20nm之厚度 (例如約20nm)。如下文將詳細說明者,硬遮罩116與硬遮 罩120將經圖樣化(根據奈米線通道在χ軸方向中的所需 位置)為複數個個別奈米線硬遮罩。 圖2為一截面圖’其說明第一硬遮罩^6與第二硬遮 罩120係圖樣化為複數個個別的奈米線硬遮罩122。如上 所述,硬遮罩的圖樣化係與奈米線的所需位置相應。根據 —示範具體實施例’一阻質膜(resist fiim)(未示)係沉積於 硬遮罩120上,並以各奈米線硬遮罩丨22之覆蓋區 (footprint)與位置予以圖樣化。在一實例中,係使用反應性 離子蝕刻(Reactive丨oil Etching,R1E)(見下文)來形成奈米 201115734 線硬遮罩,因此阻質膜包含一阻質材料,例如氫矽鹽酸類 (hydrogen silsesquioxane,HSQ),其係利用電子束(e bea叫 微影予以圖樣化並轉移至碳阻質(carb〇n_based resist)中。 接著利用一系列的逑擇性RIE步驟來進行硬遮罩開 啟階段(hardmask open stage),其係因第一硬遮罩包含氧化 物,而第二硬遮罩包含氮化物之故。舉例而言,先使用以 阻質膜(未示)作為遮罩之氮化物選擇性 RIE(nitride-selective RIE)來移除除了其下方之硬遮罩j 2〇 部分以外的所有部分,定義出奈米線硬遮罩之氮化物部分 122a。包含氧化物之硬遮罩116係作為氮化物選擇性rie 之蝕刻終止。氮化物選擇性RIE也可以矽層114作為蝕刻 終止而同時蝕刻氮化物襯層118。 其次,利用氮化物部分作為遮罩,使用氧化物選擇性 RIE來移除除了氮化物遮罩下方之硬遮罩116部分以外的 所有部分,定義出奈米線硬遮罩的氧化物部分122b。石夕層 114係作為氧化物選擇性之钱刻終止。在此例中,奈 米線硬遮罩的氮化物部分122a與氧化物部分122b各具有 介於約15nm至約2〇nm之厚度,例如約20nm。 氮化物部分122a與氧化物部分122b形成了雙重奈米 線硬遮罩結構(dual nanowire hardmask structure)。使用雙 重奈米線硬遮罩結構可於矽層中形成更精確且均勻的奈 米線。意即,利用雙重硬遮罩結構,氮化物部分122a會 ,虛擬閘極(dummy gate)定義期間(見圖3,如下所述)保護 氧化物部分122b的整體性,而氧化物部分122b則在間隔 物(spacer)(氮化物選擇性)蝕刻期間(見下述說明)保護奈米 、'泉通道。對於使奈米線維度⑽⑽〔丨丨⑽叩丨训)變異 (pmation)最小化而言,保持奈米線硬遮罩的良好整合度 是重要的。由於元件尺寸逐漸變小,使得不希望的維度變 10 201115734 異效應變得更為明顯。 在此例中,奈米線硬遮罩122係配置以具有低於約 200nm之一線距(pitch),意即一空間頻率(spatiaI frequency) ’舉例而言,介於約ι〇ηΐΏ至約2〇〇nm,例如介 於約4〇nm至約50nm。為使佈局密度(layout density)最大 化並使寄生電容最小化,線距應在圖樣化與處理極限下盡 可能為小。為使線距小於直接微影所定義者,可使用線距 加倍(pitch doubling)技術,例如側壁影像轉移(side image transfer)或雙重圖樣化(d〇uble patterning)/雙重姓刻(d〇uble etching)二各奈米線硬遮罩122的寬度丨23係低於約4〇nm, 舉例而言,介於約5nm至約40nm,如約5ηηι至約20nm。 各奈米線硬遮罩122的線距/寬度一開始係決定各夺米線 通道之線距/寬度;然而,如下文將說明者,元件的一或多 層中奈米線通道的寬度可利用側向細化製程(lateral thmnmg process)而進一步細化(超過奈米線硬遮罩所定義 者)。 Μ戴面圖,其說明了在主動區上方形成虛擬閘 0 在形成虛擬閘極之前,係於>5夕層114上形成 氧化物、.、;止層(〇xlde st〇pping layer),亦即氧化物層 12 V ·根、1—示範具體實綠利用熱氧化⑼⑽1 ⑽da—來成長氧化物層124賴4nm之厚度,例如達 、·勺2nm &熱氧化製程是可使石夕層114細化至其所需厚产 :二^4因ί在熱氧化製程期間會消耗掉-部分; 曰 ^ 之厚度會減少例如2nm,例如減少達lnm)。 "形成虛擬間極結構126以開始镶嵌問極製程。述 5兄明可知’气擬間極結構⑶定義了奈米線在y轴方向上 的=置以及最终F Εγ元件結構的問極位置。根據—示範呈 體貫施例,虛擬間極結構包含多晶卿olysilK:〇n)。,、 201115734 虛擬閘極結構126可藉由下述製程而形成。首先利用 LPCVD在氧化物層124/奈米線硬遮罩122上方沉積一多 晶碎層達約1 OOnm至約150nm(例如約140nm)之厚度。因 為多晶石夕層的厚度將決定虛擬閘極的高度,故可在沉積之 後利用化學機械拋光(chemical-mechanical polishing,CMP) 來達成所需厚度/高度。在多晶矽層上沉積一阻質膜(未 示)’其以虛擬閘極結構之覆蓋區與位置加以遮蔽及圖樣 化。接著利用多晶矽選擇性RIE來移除除了遮罩下方的多 晶石夕層部分以外之全部部分,亦即位於奈米線硬遮罩上方 的部分(集中在y軸方向中奈米線硬遮罩上方),其係虛擬 閘極結構126。根據一示範具體實施例,虛擬閘極126具 有之尚度128係介於約l〇〇nm至約150nm之間(例如約 140nm)、長度no係介於約3〇nm至約50nm之間(例如約 45nm) ° 如箭頭132所示,可視需要利用上下式佈植(t〇p_d〇wn lmplant)來摻雜矽層114,以及可能的話也摻雜其下方之矽 ,110與SOI層104。此佈植的條件為該領域技術人士所 知’其係根據使用之接質種類的類型而改變。舉例而 田犧牲層在先前製程中沒有被摻雜,或在可從犧牲層 ^侍之摻雜量(在下述擴散/活化退火期間)不足時,係可使 用上下式佈植’該上下式佈植_以補充該摻雜。 夕⑽圖4係一戴面圖’其說明了沉積在虛擬閘極126周圍 生)填充層(mler layer)136。i真充層136可包含任何適 —」充—材料’包括但不限於介電質材料,例如⑽2。根據 ::,具體實施例,填充層136係利用高密度電聚 接PlaSma ’⑽^而沉積在虛擬閘極126周圍。 =利用虛擬間極作為_終止,以㈤)來平面化填充 因此,填充層136之厚度將等於虛擬閘極的高度, 201115734 例如介於約⑺如扪至150nm之間,如約14〇nm。 圖5係一截面圖,其說明虛擬閘極係已移除。可利用 化學蝕刻製程來移除虛擬閘極126,例如化學向下流體 (chemical down stream)或氫氧化钟(K〇H)蝕刻或咖。如 圖5所不’虛擬閘極126的移除導致填充層136中溝渠138 的形成。由於溝渠138為虛擬閘極126的負圖樣(neg'ative
Pattern) ’溝渠138也會集中(亦即在y軸方向上)位於奈米 線硬遮罩122的上方。根據一示範具體實施例,溝渠 區分了元件的源極與汲極區以及元件的(奈米線)通道區。 蝕刻也對填充層136有作用而移除其一部分。舉例而 吕,在移除虛擬閘極之蝕刻製程之後,填充層136可 減少至約30nm至約I25nm之間的厚度139,例如約80nm。 虛擬閘極的使用是本發明的一項重要態樣,意即,虛 擬閘極使奈米線硬遮罩可放置於填充層之前,使得在移除 虛擬閘極時,即在溝渠内出現顯露之奈米硬遮罩。對於在 主動區中形成更精確與均勻的奈米線而言,奈米線硬遮罩 是很重要的。 圖6係一截面圖,其說明了蝕刻至更薄之最頂矽層(例 如矽層114)中的奈米線條體(bar)140(元件之奈米線通道的 前驅物(precursor))。用語「條體」係用以表示在產生fet 元件的元整奈米線通道之任何進一步處理(例如細化 (thimng)及/或懸浮化(suspending))前的已蝕刻奈米線結構 (as-etched nanowire structure)。此外,在本文中石夕層也稱 為元件層,因為每一矽層都將用以形成FET元件的一源極 與汲極區以及奈米線通道(亦即各元件層將具有一源極 區、一汲極區以及連接源極與汲極區之奈米線通道)。注 意本發明之敘述係說明較薄的元件層為矽層/犧牲層堆疊 中的單一、最頂部之矽層,然此配置僅為示例。舉例而言, 201115734 堆疊係包含比繪示者更多的石夕/犧牲層,其 頂部矽層係比堆疊中的其他層更薄。 的 示範具體實施例’利用石夕選擇性腿來移除溝 '、中未受奈米線硬遮罩122掩蔽的⑪層114部分。、下 方的犧牲層m作為触刻終止。以此方式 條體H0將具有陡峻、定義良好之邊緣。如上所 使用雙重(氮化物/氧化物)硬遮罩來圖樣化奈米線的: 果。僅舉例說明,以此方式所形成之奈米線條體會且有二 線距(pitch)(亦即-空間頻率),其係基於奈米線硬遮 線距而小於約200nm,舉例而言,線距係介於約i〇nm至 約20〇nm之間,例如介於約40nm至約5〇nm之間。此 在製程中此時間點,奈米線條體14〇將各具有由奈 遮罩m #寬度所定義之寬度141(亦即小於約4(;nm’,^ 例而言,介於約5nm至約4〇nm之間,如介於約5nm至約 20mn之間)以及由矽層114的厚度所定義之厚度143(亦即 介於約Inm至約10nm之間)。然而,奈米線條體的寬度 可進一步減少’例如藉由側向細化製程,如下文中所說明二 本發明的優勢之-在於奈米線條體係僅_於 138内,而使元件的源極/汲極區於填充層136下方保持完 整。此外,以此方式產生之源極/沒極區將與溝渠ι = 對齊,因而與將於溝渠138中形成之元件閘極對齊(見下 文說明)。 圖7係-截面圖,其說明了經側向細化之奈米線條體 具體—而言’如圖7所示,奈米線條體14〇係經側向 細化,其寬度減少至小於奈米線硬遮罩丨22之寬度。 當奈米線通道的維度變為非常小時,由於量^效廊之 故,即可籍由維度來調節V,。在本製程中,奈米線通^的 維度初始是由兩件事所決定,亦即對應之石夕層的厚度、以 201115734 及用以圖樣化奈米線條體的 各石夕層具有厚度為X,且太半、始遮罩之寬度。故,若 已圖樣化之奈米線條體具;罩具有寬度為y’則 於本發明之教示,為與得多 u而寬度為y。然由 度);為此,頂部石夕層⑽、的维度(寬度與厚 (見上述說明η其他㈣作為比初始結構 成於其:元件層中的趙更:二 ==!趙140的寬度(不影響其他元=:使: 選細虫刻來先形成奈米線條 ):= 明),讓其他元件層㈣去油二所不及上述說 體,即使1變窄接接者側向細化奈米線條 奈米線《二)暴:===== i::受未,任何其他‘^ ⑽可二 =…在侧向細化之後,奈米線條體 MU J谷具有;丨於約lnm至約1〇nm之寬度。 =利=何石夕氧化製程來進行氧化’其產生適當厚度 办賴。這些技術包括了爐式氧化(furnacebased 〇Xlda,〇n)、快速熱氧化(rapid thermal oxidation)、以及氧 或臭氧電漿氧化(plasma_base(i oxidation)。 圖8係戴面圖,其說明了截刻至元件的剩餘較厚層 (分別為矽層110與SO[層1〇4)中之奈米線條體146 ^ 148如上所述,奈米線條體為元件奈米線通道的前驅物。 如圖8所示,奈米線條體具有堆疊之配置,其中奈米線條 體丨4〇係位於奈米線條體H6上方,而奈米線條體丨46位 於奈米線條體丨48上方。 根據一示範具體實施例,利用一系列的矽選擇性與氧 化物選擇性RIE步驟來分別移除溝渠丨38内未受奈米線硬 201115734 掩蔽之部分矽層11〇_層1〇4和犧牲層 。下方層係作為各RIE步驟期間的㈣終止。舉 1你ΐ ’在石夕層110的(石夕選擇性)rie期間,犧牲層108 硬遮罩if終止。如上所述’彻雙重(氮化物/氧化物) 生具有㈣、定義良好之邊緣的圖樣化奈 例而言’以此方式所形成之奈米線條體146與 可八有一線距(Pltch)(亦即一空間頻率),其*同一元件 =:條體相同而小於約200nm,舉例而言,介於約1〇細 / OOnm之間’例如介於約4〇nm至約5〇nm之間。此 官:米線條體146與148將各具有由奈米線硬遮罩122 的寬度所定義之寬度,亦即小於約術m :約,至約術m之間,如介於約5nm至約 2件的這些「較厚」層中,奈米線條體f具有鮮米線 硬遮罩之寬度相應的寬度。 …、' 係—截面圖’其說明已移除之奈米線硬遮罩的暴 路亂化物部分122a(亦即溝帛138 _部分)。 =於奈米線硬鮮之氧化物部分選擇移除其氮化物部分 八刻製程。然而理想上’奈米線硬遮罩的氮化物部 刀之厚度應可被選擇,使其於前述條體蝕刻期間可大部分 消耗掉,因此在此時結構上應未遺留太多氮化物部分。。硬 遮罩的氧化物部分mb理想上係經設計,使其在間隔物 餘刻期間(見圖ig,下文說明)可被完全消耗掉。在間隔物 飯刻之後所遺留的任何氧化物硬鮮應薄至能夠在問極 堆疊沉積前清潔步驟期間予以移除。閘極堆疊預清潔係移 除矽表面上有機污染物、金屬污染物與任何天缺 標準製程。可湘雜氧化社濕核乾錢學 製程來移除天然氧化物,其中一個實例為丨〇〇:|之稀釋氫 氟酸(HF)。 ^ 201115734 圖10為一截面圖,其說明溝渠138中所形成之間隔 物142,此步驟為非必要步驟。在將成為元件之源極/汲極 區與元件閘極處(其將形成於溝渠138中,見圖12與下文 說明)之間放置間隔物有助於使完整元件中的寄生電容降 至最低’但其並非在產生源極/汲極(1^此(18〇111^/0以11, RSD)磊晶成長或矽化期間(亦即如一般FET流程中)避免 閘極對源極/汲極短路所必須。間隔物丨42用於使閘極自源 極/汲極區偏移一特定距離。 根據一示範具體實施例,間隔物142係藉由先在溝渠 138中沉積氮化物(&ν)而形成。接著在氮化物層上沉積一 阻質膜(未示)’其以間隔物之位置與覆蓋區予以掩蔽及圖 樣化。接著利用氮化物選擇性RIE於氮化層中定義間隔物 142。需大量時間之過度蝕刻(〇veretch)來清潔奈米線條體 堆疊的側壁,使得間隔物H2僅沿著溝渠138之側壁存在 而未存在於奈米線條體堆疊上。因此間隔物142的最小下 拉里(pulldown)為奈米線條體堆疊與剩餘(氧化物部分 122b)奈米線硬遮罩的高度。舉例而言,過度蝕刻的量係 介於約移除整體氮化物層所需之蝕刻時間的50%至80% 之根據一示範具體實施例,間隔物142具有之寬度144 係介於約5nm至約25nm之間。間隔物142的最大高度等 ^溝渠138的厚度139,小於間隔物下拉高度147。間隔 =最小高度為奈米線條體堆疊的高度149。硬遮罩的氧 晨•部在移除4化物層所需之長過枝刻期間為 IΓ在步财很有可能會_於移除氮化物層之氮 物部擇性而磨蝕。理想上,硬遮罩的氧化 Π ’r'經设计為恰好可在此步驟中完全磨蝕之厚 度0 圖丨丨係—截面圖,其說明了奈米線條體丨4〇、丨恥與 201115734 148之間的犧牲層已經被移除。現釋放之奈米線條體 (140(已細化)、146與148)即元件的奈米線通道。在本文 中,奈米線通道的這些多重層也稱為奈米線「網目 (mesh)」° 可移除奈米線條體之間的犧牲層,如下所述。可使用 化學钮刻劑,其利用比石夕層更低的犧牲層氧化電位;這種 触刻劑的實例包括但不限於1 : 2 : 3之HF ··過氧化氫 (私02):醋酸(CH3COOH)混合物或硫酸(H2S〇4)與過氧化氫 之混合物。或者是,可利用乾式蝕刻製程(例如氧(02)電漿 餘刻或一般蝕刻所用之電漿化學)來選擇性移除犧牲層。 由於經摻雜之犧牲層係自FET的通道區移除,奈米線通道 係保持為未摻雜’其為細通道、完全耗盡之元件(例如奈 米線FET)的重要優勢。 接著進行固體源擴散退火(s〇lid source diffusion anneal)(例如快速熱退火(Rapid Thermal Annel,RTA)、尖_ 峰退火(spike anneal)及/或雷射退火製程)以使摻質從犧牲 層(現在僅在源極與汲極區中)活化與擴散而通過元件層的 ,極/汲極區。此退火之溫度係介於_氏麵度至攝氏 1〇〇度之間,而退火時間係於數毫秒(例如5ms)至數秒(例 ° 間變化。如上所述’通道係保持為未推雜。 鲈太,如圖12之戴面圖所示,在溝渠138中形成圍 =2通道之—替代閘極丨5G,其係藉由在溝渠138中 而形成^此方法中所形成之閉極15〇係為共 15(/前凡Jp層^亦即β多重兀件層之單一閘極)。在放置閘極 氧化物°進m式化學清潔以移除表面污染物與天然 上。二t ϋ極介電質(例如吨)係形成於奈米線通道 f貝將使間極與奈米線通道分隔。為形成介電 .、“使用差別性化學氧化(differential diemical 201115734 oxidation) ’其優先氧化摻㈣鍺化物的暴露部分,而僅於 未心雜之τη米線通道上形成一介面層(interfaciai iayer)(閘 極”電貝)(摻雜矽比未摻雜矽氧化得更快、更容易)。 且閘極材料填充到溝渠138中,即使用CMP來平 面化閘極與作為蝕刻終止之填充層130。可利用過度拋光 來平面化填充層136與閘極材料向下直到間隔物142,以 ,成更垂直性之閘極輪廓。適當的閘極材料包括但不限於 多晶矽、沉積金屬與多重材料(例如金屬多晶矽)之複合堆 疊(hybrid stack)之一或多者。 根據上述製程所形成之FET元件具有複數個元件 層,其係垂直取向於一堆疊中。各元件層包括一源極區、 一汲極區、以及連接源極與汲極區之複數奈米線(亦即奈 米線網目)。其優勢是,一或多個元件層將具有與其他元 件層不同之Vt。舉例而言,在一配置中,具有較細/較窄 之奈米線通道的最頂部的較薄元件層將具有第一臨界電 壓Vtl,而具有較厚/較寬奈米線通道的底部較厚元件層將 具有第二臨界電壓vts。由於這種示例配置,當奈米線尺 寸(寬度/厚度)減少時,vt會因量子效應而增加。例如見 Suk 等人之文獻「investigation 〇f Nan〇wire size
Dependency on TSNWFET」(Electron Devices Meeting, IEEE International,頁 891-894 (2007))所載:「當奈米線尺 寸(亦即直徑)減少’ Vt會因奈米線之受限維度中傳導帶的 增加而增加」’其内容皆藉引用形式而併入本文。因此, 在此示例配置中,Vu係大於vt2。根據本發明教示之其他 配置亦為可行,例如在同一元件中具有兩個以上的Vt。 在運作時’不同的(多個vt)元件層係並聯使用。舉例 而言’在V^V,2之雙vt配置中’若供應電壓為低(亦 即VpV^Vc),則僅低vts元件層將運作;若v[kl增加, 201115734 (亦^卩VrCVt1)、’則並聯的兩元件層會開啟及關閉(元件層 係藉由{ 犧牲層r^於源極與汲極區巾皆—起配合)。 在予貝疋,路中的所有組件都需製作為並聯,而是只 需要在了dd提高時加速的部件(或是當vdd降低時想要消 耗較少功率的部件)。 、月』述j明了本發明之示例具體實施例,然應知本發明 並不限於如述之精確具體實施例,該領域技術人士亦可進 行各種其_化與料,其接*脫離本發明之範嘴。 【圖式簡單說明】 圖1係一截面圖’其根據本發明一具體實施例而說明 用於製造具多個臨界電壓(vt之場效電晶體(FET)之方法的 一初始結構; 圖2係一戴面圖’其根據本發明一具體實施例而說明 複數個奈米線硬遮罩; 圖3係一截面圖,其根據本發明一具體實施例而說明 形成於FET主動區上方之虛擬閘極結構; 圖4係一截面圖,其根據本發明一具體實施例而說明 沉積在虛擬閘極周圍之一填充層; 圖5係一戴面圖,其根據本發明一具體實施例而說明 移除虛擬閘極而產生形成於填充層中之一溝渠; 圖6係一截面圖,其根據本發明一具體實施例而說明 蝕刻至一較薄頂部元件層中之奈米線條體; 圖7係一截面圖,其根據本發明一具體實施例而說明 在圖6中所形成之奈米線條體係經側向細化; 圖8係一戴面圖,其根據本發明一具體實施例而說明 蝕刻至剩餘較厚元件層中之奈米線條體: 0 9係一戴面圖,其根據本發明一具體實施例而說明 20 201115734 移除之奈米線硬遮罩的一暴露氮化物部分; 圖〗〇係一截面圖,其根據本發明一具體實施例而說 明在溝渠中所形成之間隔物, 圖11係一截面圖,其根據本發明一具體實施例而說 明已經移除了奈米線條體之間的犧牲層;以及 圖12係一截面圖,其根據本發明一具體實施例而說 明在溝渠中所形成之一替代閘極。 【主要元件符號說明】 100初始結構 102晶圓 104絕緣層上覆矽(SOI)層 106埋藏氧化物(BOX)層 108第一犧牲層 110未摻雜結晶矽層 112犧牲層 114結晶矽層 116第一硬遮罩 118氮化物襯層 120第二硬遮罩 122奈米線硬遮罩 122a氮化物部分 122b氧化物部分 123寬度 124氧化物層 126虛擬閘極結構 128高度 130長度 201115734 132箭頭 136填充層 138溝渠 139厚度 140奈米線條體 141寬度 142間隔物 143厚度 144寬度 146奈米線條體 147高度 148奈米線條體 149高度 150替代閘極
Claims (1)
- 201115734 七、申請專利範圍: 1. 一種場效電晶體,包含: 垂直取向於一堆疊中之複數個元件層,各元件層具有 一源極區、一没極區以及連接該源極區與該没極區之複數 個奈米線通道,其中該等元件層之一或多者係配置以具有 與一或多個其他元件層不同之一臨界電壓;以及 圍繞該等奈米線通道之一閘極,其共用於各該元件層。 2. 如申請專利範圍第1項之場效電晶體,其中該等元件層 之一或多者係配置以具有一臨界電壓Vtl,而一或多個 其他元件層係配置以具有一臨界電壓Vt2,且其中配置 以具有臨界電壓Vtl之該一或多個元件層係具有奈米 線通道,其寬度與厚度的至少一者小於配置以具有臨 界電壓Vt2之該等元件層中之該等奈米線通道的寬度 與厚度。 3. 如申請專利範圍第2項之場效電晶體,其中Vtl係大於 vt2。 4. 如申請專利範圍第2項之場效電晶體,其中配置以具有 臨界電壓Vtl之該一或多個元件層的該等奈米線通道 係各具有介於約lnm至約10nm之寬度以及介於約 1 nm至約1 Onm之厚度。 5. 如申請專利範圍第2項之場效電晶體,其中配置以具有 臨界電壓Vt2之該一或多個元件層的該等奈米線通道 係各具有介於約5nm至約20ηιτι之寬度以及介於約 5nm至20nm之厚度。 201115734 6. 如申請專利範圍第1項之場效電晶體,其中各該元件層 之該源極與沒極區係摻雜一η型或p型摻質。 7. 如申請專利範圍第1項之場效電晶體,其中各該元件層 之該等奈米線通道係未經摻雜。 8. 如申請專利範圍第1項之場效電晶體,其中該閘極係藉 由一介電質而與該等奈米線通道分隔。 9. 如申請專利範圍第1項之場效電晶體,更包含在該等元 件層之該源極與汲極區和該閘極之間的複數個間隔 物。 10. 如申請專利範圍第1項之場效電晶體,其中該閘極包含 多晶石夕與金屬之一或多者。 11. 一種用於製造一場效電晶體之方法,包含下列步驟: 形成複數個元件層,其係垂直取向於一堆疊中,各元 件層具有一源極區、一没極區以及連接該源極區與該沒極 區之複數個奈米線通道; 配置該等元件層之一或多者為具有與一或多個其他元 件層不同之一臨界電壓;以及 形成圍繞該等奈米線通道之一閘極,其共用於各該元 件層。 丨2.如申請專利範圍第丨丨項之方法,其中該等元件層之一 或多者係配置以具有一臨界電壓V11,而一或多個其他 24 201115734 元件層係配置以具有一臨界電壓V12,該方法更包含下 列步驟: 將具有臨界電壓vtl之該一或多個元件層之該等奈米 線通道配置為具有的寬度與厚度之至少一者比具臨界電壓 vt2之該等元件層中之該等奈米線通道的寬度與厚度小。 13. 如申請專利範圍第11項之方法,更包含下列步驟: 提供一絕緣層上覆矽(SOI)晶圓; 在該晶圓上形成矽與犧牲層之一交錯序列; 將奈米線條體之一堆疊蝕刻至該矽與犧牲層中;以及 自該堆疊移除該等犧牲層。 14. 如申請專利範圍第13項之方法,其中該堆疊之一頂部 層係一矽層,該方法更包含下列步驟: 蝕刻該頂部矽層以於其中形成複數個奈米線條體;以 及 側向細化在該頂部矽層中所形成之該等奈米線條體。 15. 如申請專利範圍第14項之方法,其中該堆疊之該頂部 矽層係比該堆疊中一或多個其他矽層薄。 16. 如申請專利範圍第13項之方法,其中各該犧牲層包含 矽鍺化物,該方法更包含下列步驟: 以一 η型或一 p型摻質摻雜各該犧牲層;以及 使該摻質自該等犧牲層擴散至該等元件層之該等源極 與汲極區中之該等矽層中。 丨7.如申請專利範圍第14項之方法,其中所述側向細化在 201115734 該頂部矽層中所形成之該等奈米線條體之步驟更包含 下列步驟: 氧化在該頂部矽層中所形成之該等奈米線條體。 18. 如申請專利範圍第13項之方法,更包含下列步驟: 於該堆疊上方形成複數個奈米線硬遮罩;以及 在形成該等奈米線條體之蝕刻步驟期間使用該等奈米 線硬遮罩作為遮罩。 19. 如申請專利範圍第11項之方法,更包含下列步驟: 在形成該閘極前,先在該等奈米線通道上形成一介電 質。 26
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CN102428564B (zh) | 2014-12-17 |
US8422273B2 (en) | 2013-04-16 |
US8472239B2 (en) | 2013-06-25 |
JP5744854B2 (ja) | 2015-07-08 |
US20100295022A1 (en) | 2010-11-25 |
US20120217479A1 (en) | 2012-08-30 |
WO2010135206A1 (en) | 2010-11-25 |
JP2012527776A (ja) | 2012-11-08 |
CN102428564A (zh) | 2012-04-25 |
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