CN105359260B - 替代栅极流中的部分凹陷沟道核心晶体管 - Google Patents

替代栅极流中的部分凹陷沟道核心晶体管 Download PDF

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CN105359260B
CN105359260B CN201480037799.XA CN201480037799A CN105359260B CN 105359260 B CN105359260 B CN 105359260B CN 201480037799 A CN201480037799 A CN 201480037799A CN 105359260 B CN105359260 B CN 105359260B
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replacement gate
mos transistor
dielectric layer
gate
ldd
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CN105359260A (zh
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M·楠达库玛
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Texas Instruments Inc
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Abstract

在所描述的例子中，集成电路(100)包括衬底(102)。第一MOS晶体管(106)包括布置在第一介电层(148)上的第一替代栅极(152)以及第一沟道。第一沟道沿水平表面和竖直表面两者邻近第一介电层(148)延伸。第二MOS晶体管(108)包括布置在第二介电层(150)上的第二替代栅极(154)以及第二沟道。第二沟道沿水平表面而不是竖直表面邻近第二介电层(150)延伸。第一介电层(148)和第二介电层(150)具有大体上相同的组成。第一替代栅极(152)和第二替代栅极(154)具有大体上相同的组成。第一MOS晶体管(106)和第二MOS晶体管(108)具有相同极性。

Description

替代栅极流中的部分凹陷沟道核心晶体管
技术领域
本发明总体上涉及集成电路，并且具体地涉及集成电路中的MOS晶体管。
背景技术
集成电路可以包括使用栅极替代工艺形成的金属氧化物半导体(MOS)晶体管。可以期望MOS晶体管的一部分中增加阈值均匀性而不增加晶体管占据的面积。
发明内容
在所描述的例子中，集成电路包括衬底。第一MOS晶体管包括布置在第一介电层上的第一替代栅极以及第一沟道。第一沟道沿水平表面和竖直表面两者邻近第一介电层延伸。第二MOS晶体管包括布置在第二介电层上的第二替代栅极以及第二沟道。第二沟道沿水平表面而不是竖直表面邻近第二介电层延伸。第一介电层和第二介电层具有大体上相同的组成。第一替代栅极和第二替代栅极具有大体上相同的组成。第一MOS晶体管和第二MOS晶体管具有相同极性。
附图说明
图1A至图1H是连续制造阶段中描述的一种集成电路的剖面立体图。
图2是包含具有升高的LDD区的MOS晶体管的集成电路的剖面图。
图3是包含具有凹陷的替代栅极的MOS晶体管的集成电路的剖面图。
具体实施方式
包含具有替代栅极的MOS晶体管的集成电路可以在晶体管的一部分上形成升高的LDD区和/或凹陷的替代栅极，使得沟道和栅极介电层沿水平表面和竖直表面两者延伸。升高LDD区通过在LDD注入之前由选择性外延工艺完成。使替代电极凹陷通过在去除牺牲栅极材料之后和形成替代栅极介电层之前蚀刻衬底材料完成。升高LDD区和使替代栅极凹陷可以增加MOS晶体管的沟道长度，从而期望地增加晶体管的阈值均匀性而不增加晶体管占据的面积。
参考图1A，集成电路100在半导体衬底102中和半导体衬底102上形成，半导体衬底102可以是单晶硅晶片、绝缘体上硅(SOI)晶片、具有不同晶体取向的区域的混合取向技术(HOT)晶片或适于制造集成电路100的其它材料。
场氧化物104在衬底102的顶部表面处形成。在一个例子中，场氧化物104是厚度在200纳米和400纳米之间的二氧化硅，其由浅沟槽隔离(STI)工艺形成。STI工艺可以包括以下步骤：在衬底102上形成氧化物层、在氧化物层上形成氮化硅层、将氮化硅层图案化以暴露场氧化物104的区域、针对场氧化物104期望厚度在所暴露的区域的衬底102中蚀刻沟槽至适当深度、在沟槽的侧壁和底部上生长热氧化物层、通过化学气相沉积(CVD)、高密度等离子体(HDP)或高深宽比工艺(HARP)用二氧化硅填充沟槽、从氮化硅层的顶部表面去除不想要的二氧化硅以及去除氮化硅层。
场氧化物104将第一MOS晶体管106与第二MOS晶体管108横向地隔开。第一MOS晶体管106和第二MOS晶体管108具有相同极性。第一MOS晶体管106可以是需要窄范围阈值电势的电路(诸如静态随机访问存储器(SRAM)电路或放大器电路)的部分。第二MOS晶体管108可以是可容忍较宽范围阈值电势的电路(诸如逻辑电路或多路复用器)的部分。
第一MOS晶体管106包括：在衬底102的顶部表面处形成的第一牺牲栅极介电层110；和在第一牺牲栅极介电层110上方形成的第一牺牲栅极112。可以在第一牺牲栅极112的横向表面上形成第一偏移隔离片114。相似地，第二MOS晶体管108包括：在衬底102的顶部表面处形成的第二牺牲栅极介电层116；和在第二牺牲栅极介电层116上方形成的第二牺牲栅极118。可以在第二牺牲栅极118的横向表面上形成第二偏移隔离片120。在该实施例的一个版本中，第一牺牲栅极112的第一栅极线宽122大体上等于第二牺牲栅极118的第二栅极线宽124。术语“栅极线宽”是指在包含栅极的MOS晶体管中的电流方向上的横向宽度。
在一个替换版本中，第一牺牲栅极112的第一栅极线宽122为第二牺牲栅极118的第二栅极线宽124的80％至90％。
在一个例子中，第一牺牲栅极介电层110和第二牺牲栅极介电层116为沉积或热生长的1纳米至10纳米的二氧化硅。例如，第一牺牲栅极112和第二牺牲栅极118可以是统称为多晶硅的多晶体硅，使用硬掩模和反应离子蚀刻(RIE)工艺被图案化。而且，例如，第一偏移隔离片114和第二偏移隔离片120可以是1纳米至10纳米的氮化硅，通过等离子体增强化学气相沉积(PECVD)使用氨和双(叔丁氨基)硅烷(BTBAS)被共形地(conformally)沉积。
在第二MOS晶体管108上方形成外延阻挡层126以覆盖与第二牺牲栅极118相邻的衬底102的顶部表面。例如，外延阻挡层126可以是10纳米至50纳米的二氧化硅，通过PECVD使用氧和原硅酸四乙酯(也称为正硅酸四乙酯或TEOS)共形地沉积。外延阻挡层126被图案化以暴露第一MOS晶体管106。
参考图1B，执行选择性外延生长工艺，其在与第一牺牲栅极112相邻的衬底102上形成半导体材料(诸如晶体硅)的升高的LDD半导体区128。选择性外延生长工艺可以包括以下步骤：在800℃至1200℃下通过氢和氯化氢来减少硅烷、二氯甲硅烷或四氯化硅。例如，升高的LDD半导体区128的顶部表面可以在衬底102的顶部表面上方2纳米至10纳米处。显著量的半导体材料不通过选择性外延生长工艺在场氧化物104或外延阻挡层126上形成。
参考图1C，诸如通过利用含氟等离子体的RIE工艺，去除外延阻挡层126。随后，执行LDD注入工艺，其将掺杂剂注入到第一MOS晶体管106中的升高的LDD半导体区128中以形成第一LDD注入区130。因此，LDD注入工艺将掺杂剂注入到邻近第二牺牲栅极118的衬底102中，以在第二MOS晶体管108中形成第二LDD注入区132。
参考图1D，集成电路100被退火，使得第一LDD注入区130和第二LDD注入区132中的掺杂剂激活，以分别在与第一牺牲栅极112和第二牺牲栅极118相邻的衬底102中形成升高的第一LDD区134和第二LDD区136。例如，升高的第一LDD区134的顶部表面可以是在衬底102的顶部表面上方2纳米至10纳米处。邻近第一牺牲栅极112和第二牺牲栅极118形成源极/漏极隔离片138。例如，源极/漏极隔离片138可以是10纳米至30纳米的二氧化硅。
可以分别在第一MOS晶体管106和第二MOS晶体管108中形成第一外延源极和漏极区140与第二外延源极和漏极区142。例如，可以通过从升高的LDD半导体区128和邻近源极/漏极隔离片138的衬底102中去除半导体材料，并在其中从升高的LDD半导体区128和衬底102中去除半导体材料的区域中形成具有不同化学计量的外延半导体材料，形成第一外延源极和漏极区140与第二外延源极和漏极区142。升高的第一LDD区134针对第一外延源极和漏极区140提供漏极延伸部；相似地，第二LDD区136针对第二外延源极和漏极区142提供漏极延伸部。
参考图1E，在集成电路100上形成介电层144，以覆盖与第一牺牲栅极112和第二牺牲栅极118相邻的区域并暴露第一牺牲栅极112和第二牺牲栅极118的顶部表面。例如，介电层144可以通过由PECVD使用TEOS或旋涂工艺使用甲基倍半硅氧烷(MSQ)沉积二氧化硅共形层，或通过使用HDP工艺沉积二氧化硅来形成。随后，可以使用化学机械抛光(CMP)工艺和/或回蚀工艺(诸如抗蚀刻回蚀工艺)将二氧化硅的共形层平整化，以暴露第一牺牲栅极112和第二牺牲栅极118的顶部表面并留下覆盖邻近第一牺牲栅极112和第二牺牲栅极118的区域的介电层144。
参考图1F，诸如通过对第一牺牲栅极介电层110和第二牺牲栅极介电层116具有选择性的干法蚀刻或湿法蚀刻，去除图1E的第一牺牲栅极112和第二牺牲栅极118。随后，诸如通过对衬底102具有选择性的另一种干法蚀刻或湿法蚀刻，去除图1E的第一牺牲栅极介电层110和第二牺牲栅极介电层116。也可以诸如通过对源极/漏极隔离片138具有选择性的各向同性等离子体蚀刻，去除图1E的第一偏移隔离片114和第二偏移隔离片120。
参考图1G，蚀刻掩模146在位于图1E的第二牺牲栅极118下方的第二MOS晶体管中的衬底102上形成以暴露位于图1E的第一牺牲栅极112下方的第一MOS晶体管106中的衬底102并可能暴露场氧化物104。例如，蚀刻掩模146可以包括光致抗蚀剂并通过光刻工艺形成。
随后，执行栅极凹陷蚀刻，其从位于第一牺牲栅极112下方的衬底102和场氧化物104(如果场氧化物104暴露)中去除半导体材料。执行栅极凹陷蚀刻使得衬底102的蚀刻表面与场氧化物104的蚀刻表面大体上共面。进一步执行栅极凹陷蚀刻，以避免诸如在源极/漏极隔离片138的边缘处和场氧化物104与衬底102之间的边界处出现缺陷(divot)。例如，栅极凹陷蚀刻可以包括使用CF4和氩并任选地使用O2的等离子体蚀刻。另一种可能的栅极凹陷蚀刻可以包括使用SF6、O2和氩的等离子体蚀刻。可以在两个步骤中执行栅极凹陷蚀刻，其中在一个步骤中衬底102比场氧化物104被更快蚀刻，并且在另一步骤中相反。O2流量可以经调整达到衬底102的期望蚀刻速率。在该实施例的一个替换版本中，栅极凹陷蚀刻可以包括使用NF3、SF6和CHF3的各向同性等离子体蚀刻。在该实施例的一个版本中，可以去除2纳米至50纳米的半导体材料。在另一版本中，可以去除3纳米至10纳米的半导体材料。在栅极凹陷蚀刻完成后去除蚀刻掩模146。
参考图1H，在第一MOS晶体管106和第二MOS晶体管108中的衬底102上同时分别形成第一替代栅极介电层148和第二替代栅极介电层150。第一替代栅极介电层148下方的衬底102的表面与第一替代栅极介电层148下方的场氧化物的表面大体上共面。第一替代栅极介电层148和第二替代栅极介电层150具有大体上相同的组成。随后，在第一替代栅极介电层148和第二替代栅极介电层150上同时分别形成凹陷的第一替代栅极152和第二替代栅极154。在该实施例的一个版本中，凹陷的第一替代栅极152在衬底102的顶部表面下方凹陷2纳米至50纳米。在另一版本中，凹陷的第一替代栅极152被凹陷3纳米至10纳米。凹陷的第一替代栅极152和第二替代栅极154具有大体上相同的组成和结构。例如，凹陷的第一替代栅极介电层148和第二替代栅极介电层150可以具有高介电常数并包括氧化钽、氧化铪和/或氧化锆。例如，凹陷的第一替代栅极152和第二替代栅极154可以包括氮化钛。可以诸如通过以下方式来形成第一替代栅极介电层148、第二替代栅极介电层150、凹陷的第一替代栅极152和第二替代栅极154：沉积栅极介电材料共形层、在栅极介电材料层上沉积替代栅极材料并随后从介电层144上去除栅极介电材料和替代栅极材料。在该实施例的一个版本中，凹陷的第一替代栅极152的第一替代栅极线宽156大体上等于第二替代栅极154的第二替代栅极线宽158。在一个替换版本中，凹陷的第一替代栅极152的第一替代栅极线宽156是第二替代栅极154的第二替代栅极线宽158的80％至90％。
由于升高的第一LDD区134和凹陷的第一替代栅极152，因此第一MOS晶体管106的沟道长度比第二MOS晶体管108的沟道长度长，这可以期望地提供具有比第二MOS晶体管108更接近期望值的阈值电势的第一MOS晶体管106。第一MOS晶体管106的沟道沿水平表面和竖直表面两者延伸；第二MOS晶体管108的沟道沿水平表面而不是竖直表面延伸。
图2是包含具有升高的LDD区的MOS晶体管的集成电路的剖面图。诸如参考图1A所述，在半导体衬底202中和半导体衬底202上形成集成电路200。诸如参考图1A所述，在衬底202的顶部表面处形成场氧化物204。集成电路200包括第一MOS晶体管206和第二MOS晶体管208。第一MOS晶体管206和第二MOS晶体管208具有相同极性。
第一MOS晶体管206包括升高的第一LDD区234，其诸如参考图1A至图1D的升高的第一LDD区134而形成。第二MOS晶体管208包括未升高的第二LDD区236，其诸如参考图1A至图1D的第二LDD区138而形成。
第一MOS晶体管206可以包括第一外延源极和漏极区240，并且第二MOS晶体管208可以包括第二外延源极和漏极区242，如参考图1D所述，同时形成第一外延源极和漏极区240与第二外延源极和漏极区242。第一MOS晶体管206包括衬底202上的第一替代栅极介电层248和第一替代栅极介电层248上形成的第一替代栅极252。第二MOS晶体管208包括衬底202上的第二替代栅极介电层250和第二替代栅极介电层250上形成的第二替代栅极254。第一替代栅极252和第二替代栅极254不凹陷。诸如参考图1H的第二替代栅极介电层250和第二替代栅极254所述，可以形成第一替代栅极介电层248、第二替代栅极介电层250、第一替代栅极252和第二替代栅极254。在该实施例的一个版本中，第一替代栅极252的第一替代栅极线宽256大体上等于第二替代栅极254的第二替代栅极线宽258。在一个替换版本中，第一替代栅极252的第一替代栅极线宽256是第二替代栅极254的第二替代栅极线宽258的80％至90％。
由于升高的第一LDD区234，因此第一MOS晶体管206的沟道长度比第二MOS晶体管208的沟道长度长，这可以期望地提供具有比第二MOS晶体管208更接近期望值的阈值电势的第一MOS晶体管206。形成具有升高的第一LDD区234且不具有凹陷的替代电极的第一MOS晶体管206可以为第一MOS晶体管206提供期望阈值，并为集成电路200提供期望成本和制造顺序复杂性。
图3是包含具有凹陷的替代栅极的MOS晶体管的集成电路的剖面图。诸如参考图1A所述，集成电路300在半导体衬底302中和半导体衬底302上形成。诸如参考图1A所述，在衬底302的顶部表面处形成场氧化物304。集成电路300包括第一MOS晶体管306和第二MOS晶体管308。第一MOS晶体管306和第二MOS晶体管308具有相同极性。
第一MOS晶体管306包括未升高的第一LDD区334，并且第二MOS晶体管308包括未升高的第二LDD区336，未升高的第一LDD区334和未升高的第二LDD区336诸如参考图1C和图1D的第二LDD区136描述而形成。第一MOS晶体管306可以包括第一外延源极和漏极区340，并且第二MOS晶体管308可以包括第二外延源极和漏极区342，第一外延源极和漏极区340和第二外延源极和漏极区342如参考图1D所述而同时形成。
第一MOS晶体管306包括第一替代栅极介电层348和第一替代栅极介电层348上形成的凹陷的第一替代栅极352。诸如参考图1G和图1H的第一替代栅极介电层148和凹陷的第一替代栅极152所述，可以形成第一替代栅极介电层348和凹陷的第一替代栅极352。第二MOS晶体管308包括衬底302上的第二替代栅极介电层350和第二替代栅极介电层350上形成的第二替代栅极354。第二替代栅极354不凹陷。诸如参考图1H的第二替代栅极介电层150和第二替代栅极154所述，可以形成第二替代栅极介电层350和第二替代栅极354。在该实施例的一个版本中，凹陷的第一替代栅极352的第一替代栅极线宽356大体上等于第二替代栅极354的第二替代栅极线宽358。在一个替换版本中，凹陷的第一替代栅极352的第一替代栅极线宽356是第二替代栅极354的第二替代栅极线宽358的80％至90％。
由于凹陷的第一替代栅极352，因此第一MOS晶体管306的沟道长度比第二MOS晶体管308的沟道长度长，这可以期望地提供具有比第二MOS晶体管308更接近期望值的阈值电势的第一MOS晶体管306。形成具有凹陷的第一替代栅极352且不具有升高的LDD区的第一MOS晶体管306可以为第一MOS晶体管306提供期望阈值并为集成电路300提供期望成本和制造顺序复杂性。
在所要求保护的范围内，所描述实施例的修改是可能的，并且其它实施例是可能的。

Claims (20)

1.一种集成电路，所述集成电路包括：
衬底，所述衬底包括半导体材料；
第一金属氧化物半导体晶体管，即第一MOS晶体管，所述第一MOS晶体管包括布置在第一介电层上的第一替代栅极、第一轻掺杂漏极区即第一LDD区、源极和漏极区以及第一沟道长度，其中所述第一沟道长度在所述第一轻掺杂漏极区之间沿水平表面和竖直表面两者邻近所述第一介电层延伸，所述竖直表面延伸以接触所述第一LDD区，并且其中所述第一替代栅极和所述第一介电层在所述第一LDD区的顶部表面下方延伸，并且延伸的距离小于所述源极和漏极区的深度；和
第二MOS晶体管，所述第二MOS晶体管包括布置在第二介电层上的第二替代栅极、第二LDD区以及第二沟道长度，其中所述第二沟道长度沿水平表面而不是竖直表面邻近所述第二介电层延伸，并且其中所述第二替代栅极没有在所述第二LDD区的顶部表面下方延伸；
其中所述第一MOS晶体管是凹陷的使得所述第一介电层和所述半导体材料之间的界面低于所述第二介电层和所述半导体材料之间的界面，所述第一介电层和所述第二介电层具有相同的组成，所述第一替代栅极和所述第二替代栅极具有相同的组成，以及所述第一MOS晶体管和所述第二MOS晶体管具有相同极性。
2.根据权利要求1所述的集成电路，其中凹陷的所述第一替代栅极的第一栅极线宽等于所述第二替代栅极的第二栅极线宽。
3.根据权利要求1所述的集成电路，其中所述第一替代栅极的第一栅极线宽为所述第二替代栅极的第二栅极线宽的80％至90％。
4.根据权利要求1所述的集成电路，其中所述第一MOS晶体管是静态随机访问存储器电路即SRAM电路的部分。
5.根据权利要求1所述的集成电路，其中，所述第二MOS晶体管是逻辑电路的部分。
6.根据权利要求1所述的集成电路，其中所述第一替代栅极在所述衬底的所述顶部表面下方凹陷2纳米至50纳米。
7.根据权利要求6所述的集成电路，其中所述第一介电层下方的所述衬底的表面与所述第一介电层下方的场氧化物的表面共面。
8.根据权利要求6所述的集成电路，其中所述第一MOS晶体管包括升高的轻掺杂漏极区即LDD区，并且所述第二MOS晶体管包括未升高的LDD区。
9.根据权利要求1所述的集成电路，其中所述第一MOS晶体管包括升高的LDD区，并且所述第二MOS晶体管包括未升高的LDD区。
10.一种形成集成电路的方法，所述方法包括以下步骤：
提供包括半导体材料的衬底；
同时去除第一MOS晶体管中的第一牺牲栅极并去除第二MOS晶体管中的第二牺牲栅极；
同时去除所述第一MOS晶体管中的第一牺牲栅极介电层并去除所述第二MOS晶体管中的第二牺牲栅极介电层；
在所述第二MOS晶体管中的所述衬底上方形成蚀刻掩模以暴露所述第一MOS晶体管中的所述衬底；
在所述第一MOS晶体管中的凹陷替代栅极的区域中从所述衬底去除半导体材料并同时从与所述区域相邻的场氧化物去除场氧化物以形成凹陷，使得所述衬底的蚀刻表面和与所述衬底的所述蚀刻表面相邻的场氧化物的蚀刻表面在所述凹陷的底部处共面，并使得半导体材料不从所述第二MOS晶体管中的所述衬底去除；
同时在所述第一MOS晶体管中形成第一替代栅极介电层并在所述第二MOS晶体管中形成第二替代栅极介电层；以及
同时在所述第一替代栅极介电层上形成凹陷的第一替代栅极并在所述第二替代栅极介电层上形成第二替代栅极；
其中所述凹陷的第一替代栅极在所述衬底的顶部表面下方凹陷，并且所述第一MOS晶体管和所述第二MOS晶体管具有相同极性。
11.根据权利要求10所述的方法，其中所述凹陷的第一替代栅极的第一替代栅极线宽等于所述第二替代栅极的第二替代栅极线宽。
12.根据权利要求10所述的方法，其中所述凹陷的第一替代栅极的第一替代栅极线宽为所述第二替代栅极的第二替代栅极线宽的80％至90％。
13.根据权利要求10所述的方法，进一步包括以下步骤：
在所述第二MOS晶体管上方形成外延阻挡层，以覆盖邻近所述第二牺牲栅极的所述衬底并暴露邻近所述第一牺牲栅极的所述衬底；
在所述外延阻挡层处于适当位置时，通过选择性外延生长工艺邻近所述第一牺牲栅极形成升高的LDD半导体区，使得邻近所述第二牺牲栅极不形成升高的LDD半导体区；
去除所述外延阻挡层；以及
随后，在同时去除所述第一牺牲栅极和所述第二牺牲栅极之前，注入掺杂剂到所述升高的LDD半导体区中，以在邻近所述第二牺牲栅极的所述衬底中形成第一LDD注入区，并形成第二LDD注入区，使得所述第二LDD注入区不被升高。
14.根据权利要求10所述的方法，其中所述第一MOS晶体管是SRAM电路的部分。
15.根据权利要求10所述的方法，其中所述第二MOS晶体管是逻辑电路的部分。
16.一种形成集成电路的方法，所述方法包括以下步骤：
提供包括半导体材料的衬底；
在第二MOS晶体管上方形成外延阻挡层，以覆盖邻近所述第二MOS晶体管的第二牺牲栅极的所述衬底并暴露与第一MOS晶体管的第一牺牲栅极相邻的所述衬底；
当所述外延阻挡层处于适当位置时，通过选择性外延生长工艺邻近所述第一牺牲栅极形成升高的LDD半导体区，使得邻近所述第二牺牲栅极不形成所述升高的LDD半导体区；
去除所述外延阻挡层；
随后，注入掺杂剂到所述升高的LDD半导体区中，以在邻近所述第二牺牲栅极的所述衬底中形成第一LDD注入区，并形成第二LDD注入区，使得所述第二LDD注入区不被升高；
同时去除所述第一牺牲栅极并去除所述第二牺牲栅极；
同时去除所述第一MOS晶体管中的第一牺牲栅极介电层并去除所述第二MOS晶体管中的第二牺牲栅极介电层；
同时在所述第一MOS晶体管中形成第一替代栅极介电层并在所述第二MOS晶体管中形成第二替代栅极介电层；以及
同时在所述第一替代栅极介电层上形成凹陷的第一替代栅极并在所述第二替代栅极介电层上形成第二替代栅极；以及
形成与所述第一LDD注入区相邻的第一源极和漏极区以及与所述第二LDD注入区相邻的第二源极和漏极区，其中所述第二源极和漏极区和所述第二LDD注入区与所述第一替代栅极介电层的底部和所述第二替代栅极介电层的底部是共面的，并且其中所述第一源极和漏极区和第一LDD注入区具有共面的顶部表面，所述共面的顶部表面从所述第二源极和漏极区、所述第二LDD注入区、所述第一替代栅极介电层和所述第二替代栅极介电层的底部升高。
17.根据权利要求16所述的方法，其中所述凹陷的第一替代栅极的第一替代栅极线宽等于所述第二替代栅极的第二替代栅极线宽。
18.根据权利要求16所述的方法，其中所述凹陷的第一替代栅极的第一替代栅极线宽为所述第二替代栅极的第二替代栅极线宽的80％至90％。
19.根据权利要求16所述的方法，其中所述第一MOS晶体管是SRAM电路的部分。
20.根据权利要求16所述的方法，其中所述第二MOS晶体管是逻辑电路的部分。
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