TW201034185A - Metal-insulator-semiconductor tunneling contacts - Google Patents

Metal-insulator-semiconductor tunneling contacts Download PDF

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Publication number
TW201034185A
TW201034185A TW098142486A TW98142486A TW201034185A TW 201034185 A TW201034185 A TW 201034185A TW 098142486 A TW098142486 A TW 098142486A TW 98142486 A TW98142486 A TW 98142486A TW 201034185 A TW201034185 A TW 201034185A
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Taiwan
Prior art keywords
transistor
contact
insulator
source
conductive
Prior art date
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TW098142486A
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English (en)
Inventor
Niloy Mukherjee
Gilbert Dewey
Matthew V Metz
Jack Kavalieros
Robert S Chau
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Intel Corp
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW201034185A publication Critical patent/TW201034185A/zh

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

201034185 六、發明說明： L 明所屬技領3 本發明係有關於金屬-絕緣體-半導體穿隧接點。 背景 本發明之背景 在積體電路的製造中，諸如電晶體的裝置形成於一晶
圓上，且使用多個金屬化層連接在一起。該等金屬化層包 括通孔及互連體，如在該技藝中已知的，其等作為用以互 連該等裝置的電氣路徑發揮作用。接點將該等通孔及互連 體連接至該等裝置。 【明内j 依據本發明之一實施例，係特地提出一種裝置，其包 含有.-電晶體’其具有_源極區域及—汲極區域；—第 層間電介質層，其相鄰於該電晶體；一溝槽，兑穿過該 第-層間電介質層至該源極區域；及—傳導源極接點，: 該溝槽巾’簡極接㈣自—歸層與賴極區域相分離。 圖式之簡單描述 圖，=圖是緣示具有—電氣接點之—裝置的1面側視 、.該傳導接點材料藉由—絕緣體與該正受接觸的區 场I分離； 第2圖是繪示可用以製造第1圖所示之該裝置的一方 法的一流程圖； 第3圖是繪示沈積於該電晶體上之該第-ILD層的一 3 201034185 截面側視圖； 第4圖是繪示形成於該第一 ILD層中之溝槽的一截面 側視圖； 第5圖是繪示沈積於該等溝槽中之該絕緣層的一截面 側視圖； 第6圖是繪示沈積於該絕緣層上之該傳導層的一截面 側視圖； 第7圖是繪示該填充材料的一截面側視圖； 第8圖是繪示額外的ILD及傳導層的一截面側視圖； 第9圖是繪示一多閘極電晶體的一等角視圖； 第10圖是穿過該鰭片之該源極區域部分，且繪示該第 一 ILD層的一截面側視圖； 第11圖是繪示形成於該第一 ILD層中之一溝槽的一截 面側視圖； 第12圖是繪示形成於該鰭片之該頂面及側壁上的該絕 緣層、形成於該絕緣層上的該傳導層116及實質上填充該 溝槽之剩餘容積的該填充材料的一截面側視圖； 第13圖是繪示缺乏填充材料之一實施例的一截面側視 圖；以及 第14圖是繪示在同一基體上的一第一電晶體及一第二 電晶體的一截面側視圖。 C實施方式3 詳細描述 在下面的描述中，至一半導體裝置的一接點的各種實 201034185 ⑽料以討論，其中―絕緣體將—傳導接點與該裝置分 離彡該相關技株中具有通常知識者將認識到的是，該等 各種實施例可以不由該等特定細節中—或多個細節來實 行，或由其他替代及/或額外的方法、材料或元件來實行。 在其他實例中’已知的結構、材料或操作沒有予以詳細地 顯示或描述’以避免模糊本發明之各種實施例的層面。類 似地，以解釋為目的，特定的數目、材料及組態被提出， • α提供對本發明的透徹理解。然而，本發明可不由特定的 細節來實行。再者，應理解的是，在該等圖中所示的各種 實施例是說雜的範例表示，且不_定按照比例缚製。 貫穿此說明書對“—實施例，，之參照意指結合該實施例 ‘ 所述之一特定的特徵、結構、材料或特性包括於本發明的 ' 至少—個實施例中，但是不表示其等出現於每一實施例 中因而，在貫穿此說明書出現於各種地方的短語“在一實 施例中’’不-定是指本發明的同_實施例。再者，該等特定 • ㈣徵、結構、材料或特性可以任何適當的方式結合於-或多個實施例中。可包括各種額外的層及/或結構 ，及/或在 其他實施例中可省略所述的特徵。 各種操作將依:欠以最㈣助理解本發明之^•式，而描 述為多個分離的操作。然而，描述的次序不該理解為是暗 =，此等操作必須是:欠序相依的。特制是此等操作不 而要以陳述的次序來執行。與該所述實施例相比，所述操 作可以+同的次序，串聯地或並行地予以執行。各種額 卜的操作可予以執行，及/或在額外實施例中所述操作可予 5 201034185 以省略。 第1圖是繪示具有一電氣接點之一裝置丨00的一截面 側視圖，其中該傳導接點材料116藉由一絕緣體114與正 受接觸的該等區域106、108分離。在一實施例中，該裝置 100是一電晶體。該電晶體包括一源極區域1〇6及一汲極區 域108。存在至該等源極及汲極區域106、1〇8的接點。此 等接點包括藉由一絕緣材料114與該等源極及汲極區域 106、108分離的一傳導材料116。此一安排避免了需要一 般用於電晶體的一矽化物或鍺化物接點。 透過避免一矽化物或鍺化物接點的使用，裝置100的 一些實施例可允許使用保形的接點形成製程，其允許接點 形成於較小的溝槽中’使裝置100能夠縮小尺寸。該裝置 100的一些實施例較容易製造，因為不需要一矽化物或鍺化 物所需的超純的金屬沈積。而且，隨著裝置100變得越來 越小’較少的半導體材料可用來形成一矽化物或鍺化物。 該裝置100的一些實施例透過不使用一矽化物或鍺化物， 而避免了過度消耗形成該裝置1〇〇之一部分的半導體材 料。而且，矽化物等的形成可能將應力施予該裝置，或限 制可能由其他結構及材料所引起的應力。透過省略該石夕化 物’可能增加該等可用應力修改的可能性，且從而允許一 性能較佳的裝置100。 在該所繪示範例中，該裝置1〇〇包括一基體102。此基 體102可包含作為可建立一半導體裝置之基礎的任何材 料。在一範例中，基體102是一包含矽的基體，儘管在其 201034185 :财也可使用其他的材料。該基想ι〇2可使用 緣層切結構來形成。在其財施中，該基想1〇2 他㈣枓形成’該等其他的材料可與或不與石夕結 括{不限於鍺、録化銦、碲化船、_化銦、鱗化姻、 珅:鎵:。綈化鎵或其他的第三至五族材料。該基體1〇2可 =-早「的材料’或具有多個層及/或具有多個結構。雖 ，，、、此知述了可形成該基冑102之材料的-些範例，但是
可作為建立—裝置之基礎的任何材料都在本Μ的精神及 範圍中。 “所、會下之範例中的該裝置_包括一電晶體。該 電的體匕#閘極1〇4、一源極區域_及一没極區域 1〇8/β該電晶體可包括多個其他的區域及結構，但是此等為 了簡單及月晰而予以省略。儘管所緣示的—平面電晶體虫 型地建立於—縣體上，但找電晶體可錢-多閘極電 曰曰體’可以疋基於不同類型的材料(諸如-第三至五族材 料）在此所述的該等接點不限於一特定類型的裝置1〇〇或 電晶體。 在該所繪示的範例中，在該電晶體上存在一第一層間 電介質(ILD)廣110。至該源極區域106及沒極區域108的 接點穿過該第-⑽層UG形成於溝射。應注意的是， 為了清晰，至該閘極1〇4的接點在此沒有予以顯示，但是 其通常是存在的。與所示及所述之至源極及汲極區域1〇6、 108之接點相似，至該閘極104的接點可用於各種實施例 中。在此所述接點不限於用於源極及汲極區域1〇6、1〇8 , 7 201034185 而是可與該閘極H)4或其他元件—起制。料接點允許 操作該電晶體，及在各種電晶體之間及在該裝置1〇〇與外 部裝置之間的電氣通訊。 在該所繪示之實施例中，該接點包括與該溝槽保形且 相鄰於該等源極及汲極區域106、1〇8的一絕緣層ιΐ4。相 鄰於該絕緣層114的是一傳導層116。該絕緣層114將該傳 導層116與該等源極及汲極區域1〇6、1〇8分離（或與該接 點所接觸的任何元件分離）。儘管該傳導層116不直接地與 該等源極及汲極區域106、1〇8相接觸，但是其仍作為一電 氣接點發揮作用。此可藉由該絕緣層114整體或部分地解 釘扎來自該半導體源極或汲極區域1〇6、1〇8的金屬費米能 階而發生。因而，在一傳導體直接地與該源極或汲極區域 106、108相接觸的情況下，若一絕緣層1丨4包含在該傳導 層116與該源極或汲極區域106、1〇8之間，則可實際上減 小該接點的電阻。在一些實施例中，此等接點可允許在低 摻雜(摻雜位準〜1 X 1017 at/cm3)矽上具有接近於】X ι〇_7 ohm-μηι2(歐姆-平方微米）或更小的一特定接點電阻率e c， 其比在相同摻雜位準之Si上的傳統矽化物接點（例如 NiSi、TiSi2、CoSi2)小5X-10X。此類型的接點也可允許按 照所期望的最佳裝置100性能，來調整該蕭特基能障高度 與接點電阻。 在該所繪示之實施例中，存在實質上填充穿過該第一 ILD層11〇之該溝槽的不由該絕緣層114及傳導體層η6 所佔據的剩餘容積的一填充材料118。該填充材料U8可以 201034185 是一金屬或其他的傳導體， 以疋另—類型的材料。在 i體不存在—分離的填充材料•而是，該傳 V體層116可實質上填充穿過 的不由該絕緣層114所佔據的剩餘容積。110之該溝槽 的Γ圖是綠示可製造第1圖所示之裝置咖的一方法 的一流程圖200。其他的方、、玄 干筋方;、 其他的實施射。在此 不範方法開始處，包括該閘 B ^ 104 /原極 10ό 及沒極 1〇8 ❿ 的该電日日體已經形成於該基 沈積搬於該電晶體上。 該第一1⑶層110 第冑疋根據本發明之_實施例，纷示沈積於該 電晶體上之該第-ILD層陶一截面側視圖。該第一⑽ 層110可使用已知地適用於積體電路結構之電介質層中的 材料(諸如低介電常數電介質材料)來形成。此等電介質材料 包括但不限於諸如二氧切(sio·氧化物、及碳摻雜氧化 物（CDO)、氛化石夕、諸如全敦環丁燒或聚四氟乙稀的有機 聚合物、氟石夕酸鹽玻璃（FSG)及諸如倍半石夕氧燒、妙氧 烷或有機矽酸鹽玻璃的有機矽酸鹽。該電介質第一 ild層 110可包括氣孔或其他空隙，以進一步減小其電介質常數。 回顧第2圖，一開口形成2〇4於該第一 ILD層11〇中。 第4圖是繪示形成204於該第一 ild層11〇中之溝样H2 的一裁面側視圖。諸如一或多個濕式或乾式蝕刻的任何適 當方法可用以形成204該等溝槽112〇如所繪示該等溝槽 112僅至該等源極及汲極區域106、108。然而，至間極1〇4 的溝槽112及接點也可予以形成，儘管其等在此沒有予以 9 201034185 特定地顯示及描述。 如第2圖所示，在該等溝槽112形成204之後，一絕 緣層114可沈積206於該等溝槽112中。第5圖是繪示沈 積於該等溝槽112中之該絕緣層114的一截面側視圖。在 一些實施例中，該絕緣層114可藉由諸如化學汽相沈積 (CVD)、原子層沈積(ALD)的一保形沈積製程予以沈積 206 ’可藉由一熱長成製程（諸如該基體材料之一氧化物、 氮化物或氮氧化物的熱長成）來形成206，或藉由另一適當 的沈積製程來形成206。該絕緣層114可包含諸如Hf〇2、 A10、ZrO、Si3N4、Si〇2、SiON或另一絕緣電介質材料的 一電介質材料。在一些實施例中，該絕緣層114的厚度被 選擇’以允許不釘扎隨後所沈積之傳導體的費米能階。在 一些實施例中，該絕緣層114可能極其薄以實現此，諸如 在各種實施例中小於大約4奈米，小於大約3奈米或大約i 奈米或更小。在一實施例中，該絕緣層114在大約5與 埃之間。也可以使用其他厚度的絕緣層114。應注魚的a 儘管該絕緣層114說明成予以保形沈積，但是此不是_、、 要條件。在一些實施例中，諸如具有一熱長成絕緣層Η* 的實施例，該絕緣層114可予以不保形地形成。 再次參照第2圖’一傳導層116沈積208於該絕緣層 114上。第6圖是繪示沈積208於該絕緣層114上的j傳導 層116的一截面側視圖。該傳導層116可藉由諸如化風士 相沈積(CVD)、原子層沈積(ALD)、無電電鍍或另—適也、、尤 積製程的一保形沈積製程予以沈積208。在一些實施例中 10 201034185 ^ ^傳導層116用以填充該等溝槽112的剩餘容 13圖是續示+ —杏 '、此一貫施例的一截面侧視圖）或該等溝槽112足 夠大的實施例中，諸如的非保形沈積技術可用以沈積 208該傳導層。
在-些實施例中，該傳導層ιΐ6可以是一金屬或包含 各種金屬可予以使用。在一些實施例中，該傳導 料1Γ材料可基於該難電晶體的—適當功函數(高功函 於PM〇S電晶體，低功函數金屬帛於-]STMOS 曰曰體其中“功函數在大約5電子伏特以上且“低”功 函數為大約3.2電子伏特歧低)來轉，儘管此並非必要 X用於該傳導層116的材料包括銘、錄、鎮、銅或其他 傳導金屬碳化物、氮化物或其他材料也可用於該傳 16。任何適當的厚度可驗該傳導層則。在一些實 施=中’該傳導層U6大於刚埃，其 該傳導層m遠遠厚於100埃。 -貫 在—些實施例中，該閘極⑽可以是遭移除的一犧牲 及在該第—ILDI11G予以沈積之後所形成的-新 在此一實施例中，該新閉極可由與形成該傳導層m 製程’且在形成該傳導層…相同時間予以形成。 在此所述之該絕緣層114及傳導層ιΐ6的形成可允許 在極其狹㈣溝槽112中形成接點。心形成切化物及 錄化物中所使狀極純金相料製程可能導致在與極其 狹窄的溝槽112 一起使用時出現的問題。因而，透過如在 此所述在絕緣雜社㈣料體，如於如果使时化 11 201034185 物或鍺化物接點，可能將該等溝槽112縮小尺寸。 再次參考第2圖，該溝槽112的剩餘容積予以填充 210。第7圖是繪示該填充材料118的一戴面侧視圖。此填 充材料118可以是一傳導材料或任何其他適當的材料，可 以是一單一材料或多個材料，且可以由任何適當的方法予 以沈積。如先前所述，在實施例中該傳導層116可填充哕 溝槽。一分離的填充材料118不用於如第13圖所綠示之此 等實施例中。 回顧第2圖，額外的ILD及傳導層可接著予以形成 _ 212。第8圖是緣示額外ILD及傳導層的一截面側視圖。在 第8圖中，該絕緣層U4、傳導層116及填充材料118予以 平坦化’以實質上與該第一 ILD層110的一頂面共平面。 在平坦化之後，至該源極區域106的溝槽112中的該傳導 層116不與至該汲極區域108的溝槽112中的該傳導層116 連續。該傳導層116可從而被認為是在該源極區域1〇6之 左側的該溝槽112中的一第一傳導層，及在該沒極區域1〇8 之右側的該溝槽中的一第二傳導層。 參 一第二ILD層120已經沈積於該第一 ild層110上。 s亥第二ILD層120中的通孔122及線124藉由該等溝槽112 中的接點傳導地連接於該等源極及汲極區域106、108。一 第二ILD層126已經沈積於該第二ILD層120上。該第三 乩〇層126中的通孔122及線124藉由該等溝槽112中的 接點傳導地連接於該等源極及汲極區域106、108。額外的 ILD層及傳導體可出現於其他實施例中。 12 201034185 第9圖是繪示一多閘極電晶體的一等角視圖。儘管第1 及3-8圖繪示了對於平面電晶體所形成的接點，但是相同 的絕緣層上傳導體接點也可用於其他類型的電晶體，諸如 二閉極電晶體。第9圖所料之該三閘極電晶體包括-韓 片13〇。在該·辖片130的任一側上存在隔離區域138。在該 ‘铸片130上存在相鄰於該韓# 130之頂部及相對側壁的-閘極電極132。在該難電極132之—側上的是—源極區域 134’且在該閘極電極132之另一側上的是一汲極區域。應 注意的是，儘管對於該等源極及汲極區域134、136，第9 圖僅具有指向朗片132之頂面的㈣，但是該等源極及 汲極區域134、136可沿著該鰭片13〇的頂面及側壁延伸。 第ίο圖是穿過該鰭片130的源極區域134部分，且繪 示忒第一 ILD層11〇的一載面側視圖，該第一 ILD層11〇 以與第3圖所示之-第-1LD層110可能形成於-平面電 晶體上相似的方式來形成。第11圖是繪示形成於該第一 ILD層11〇中之一溝槽112的一截面側視圖。該源極區域 134藉由此溝槽112而暴露。 第12圖是繪示形成於該鰭片130之該源極區域134的 頂面及側壁上的該絕緣層114、形成於該絕緣層U4上之該 傳導層116、及實質上填充該溝槽112之剩餘容積的該填充 材料118的—戴面側視圖。此等材料可與上面針對於一平 面電晶體所述相似地予以形成。因為對於該平面電晶體， 該絕緣層114將該傳導層116與該源極區域134分離，所 以相比於如果—傳導體經由穿隧與該源極區域相接觸，此 13 201034185 可允許-較低電阻的接點。而且，絕緣體ιΐ4及傳導體116 的保形沈積使該鰭片130實質上完整。如果—石夕化物緒 化物或相似接點獲得形成，則該接點將消耗該鰭片的 大量半導體材料，其可能在該韓片13〇是極小的情況下， 製成一無功能的裝置。 第14圖是緣示在同一基體1〇2上的—第—電晶體3〇2 及一第二電晶體304的一截面側視圖。電晶體3〇4具有包 含一矽化物、鍺化物等的接點3〇6,或以另外的方式具有與 該等源極及汲極區域1〇6、108相接觸的—傳導體。曲線 參 A-A表示’該等電晶體302、3〇4可相互分離，而非鄰接於 彼此。在-些實施例中，在-基體1〇2上諸如電晶體3〇2 的-些電晶體可包括具有該傳導體116的接點，該傳導體 116藉由一絕緣層114與該等源極及/或汲極區域1〇6、1〇8 — 相分離，而在同一基體上諸如電晶體3〇4的其他電晶體可 包括由-石夕化物、鍺化物或其他材料所形成，具有與該等 源極及/或汲極區域106、108相接觸之一傳導體的接點 306。例如，具有接點（其具有藉由_絕緣體114輿該等源 〇 極及汲極區域106、108相分離的_傳導體116)的電晶體 302可以是一 NMOS電晶體’而電晶體3〇4可以是一 pM〇s 電晶體’或反之亦然。在一實施例中，—基體上之一種類 型(N-型或P-型）的所有電晶體可具有一種類型的接點，而 該相反類变的所有電晶體可具有另—類型的接點。在另_ 實施例中，-些選定的電晶體可具有多個接點，該等接點 具有藉由一絕緣層114與該等源極及/或汲極區域丨〇6、川8 14 201034185
相分離的傳導體116’而該等電晶體的剩餘部分可具有較多 的傳統接點306。此等選定的電晶體可以是一種類型（N_型 或P-型），或可包括多種類型的電晶體(N-型及Ρ·型）。在其 他實施例中，一基體102上的所有電晶體可具有多個接點， 該等接點具有藉由一絕緣層114與該等源極及/或汲極區域 106、108相分離的傳導體Π6。在再—實施例中，一種類 型的一些或所有電晶體可具有絕緣、傳導及(如果可用的話) 填充層114、116、U8,與其他類型的電晶體的絕緣、傳導 及(如果可用的話)填充層114、116、118相比，其等包含不 同的材料。例如，N-型電晶體可具有包含該等絕緣、傳導 及(如果可用的話)填充層114、116、118的一第一組材料， 且同一基體102上的P-型電晶體可具有包含該等絕緣、傳 導及(如果可用的話)填充層114、116、118的一第二不同組 材料。 本發明之實施例的先前描述已經以說明及描述為目的 予以呈現。其不打算是詳盡的，或將本發明限制為所揭露 的精確形式。此描収料㈣專鄕圍在下面包括諸如 士、右、頂部、底部、在…上、在…下、上方、下方、第 -、第二等的習語’其等僅驗描述之目的且残 是限制性的。例如，表示相對垂直位置的習語是指下面的 情況:其中-基體或積體電路的一裝置側(或主動表面)在此 基體的“頂”面；該基财實際上在任何方財，使得在一 標準的參考地面座標系中—基體的―“頂，，面可低於該“底” 側，且仍在該習語“頂部”的意義卜在此所（包括在該等申 15 201034185 請專利範圍中）所使用之該習語“在…上”不表示“在”一第二 層“上”的一第一層直接地在該第二層上，及直接地與該第 二層相接觸，除非予以特定地描述；在該第一層上可能有 在該第一層與該第二層之間的一第三層或其他結構。在此 所述之一裝置或物品的實施例可以多個位置及方位予以製 造、使用或載運。在該相關技藝中具有通常知識者可理解 的是，根據上面的教示，多個修改及變化是可能的。在該 技藝中具有通常知識者將認識到的是，該等圖中所示之各 種元件的各種等效結合及替換。因而，其企圖在於本發明 之範圍不是由此詳細描述來限制，而是由附加的申請專利 範圍來限制。 I：圖式簡單說明3 第1圖是繪示具有一電氣接點之一裝置的一截面側視 圖，其中該傳導接點材料藉由一絕緣體與該正受接觸的區 域分離； 第2圖是繪示可用以製造第1圖所示之該裝置的一方 法的一流程圖； 第3圖是繪示沈積於該電晶體上之該第一 ILD層的一 截面側視圖； 第4圖是繪示形成於該第一 ILD層中之溝槽的一截面 側視圖； 第5圖是繪示沈積於該等溝槽中之該絕緣層的一截面 側視圖； 第6圖是繪示沈積於該絕緣層上之該傳導層的一截面 16 201034185 側視圖； 第7圖是繪示該填充材料的一截面側視圖； 第8圖是繪示額外的ILD及傳導層的一截面側視圖； 第9圖是繪示一多閘極電晶體的一等角視圖； 第10圖是穿過該鰭片之該源極區域部分，且繪示該第 一 ILD層的一截面側視圖； 第11圖是繪示形成於該第一 ILD層中之一溝槽的一截 面側視圖； 第12圖是繪示形成於該鰭片之該頂面及側壁上的該絕 緣層、形成於該絕緣層上的該傳導層116及實質上填充該 溝槽之剩餘容積的該填充材料的一截面側視圖； 第13圖是繪示缺乏填充材料之一實施例的一截面側視 圖；以及 第14圖是繪示在同一基體上的一第一電晶體及一第二 電晶體的一截面側視圖。 【主要元件符號說明】 100…裝置 122...通孔 102...基體 124…線 104...閘極 126·.·第三ILD層 106、134...源極區域 130...鰭片 108、136...汲極區域 132...閘極電極 110...第一層間電介質/ILD層 138…隔離區域 112...溝槽 200...流程圖 114...絕緣體/絕緣材料 302…第一電晶體 116...傳導層/傳導材料 304…第二電晶體 118...填充材料 306...接點 120...第二 ILD 層 202〜212·.·步驟 17

Claims (1)

  1. 201034185 七、申請專利範圍： 1. 一種裝置，包含： 一電晶體，其具有一源極區域及一汲極區域； 一第一層間電介質層，其相鄰於該電晶體； 一溝槽，其穿過該第一層間電介質層至該源極區 域；及 一傳導源極接點，在該溝槽中，該源極接點藉由一 絕緣層與該源極區域相分離。 2. 如申請專利範圍第1項所述之裝置，其中該電晶體是包 括一鰭片的一多閘極電晶體。 3. 如申請專利範圍第2項所述之裝置，其中該絕緣層在該 鰭片之一頂面及側壁上。 - 4. 如申請專利範圍第1項所述之裝置，其中該絕緣層具有 _ 大約4奈米或更小的一厚度。 5. 如申請專利範圍第1項所述之裝置，其更包含： 一第二層間電介質層； _ 一第一金屬化層，其相鄰於該第二層間電介質層， 且具有多個傳導通孔及多個傳導線； 一第三層間電介質層，其在該第二層間電介質層 上； 一第二金屬化層，其相鄰於該第三層間電介質層， 且具有多個傳導通孔及多個傳導線；及 其中，該第一金屬化層之該等傳導通孔及該等傳導 線中的至少一些及該第二金屬化層之該等傳導通孔及 18 201034185 該等傳導線中的至少一些，傳導地連接於該傳導源極接 點。 6. 如申請專利範圍第1項所述之裝置，其中該傳導源極接 點具有小於100奈米的一厚度。 7. 如申請專利範圍第6項所述之裝置，其更包含在該傳導 源極接點上且實質上填充該溝槽的一填充傳導體。 8. 如申請專利範圍第1項所述之裝置，其中該電晶體是一 P-型電晶體，且該傳導源極接點包含具有在大約5電子 伏特以上之一功函數的一金屬。 9. 如申請專利範圍第1項所述之裝置，其中該電晶體是一 N-型電晶體，且該傳導源極接點包含具有在大約3.2電 子伏特以下之一功函數的一金屬。 10. 如申請專利範圍第1項所述之裝置，其中該傳導源極接 點包含A1或Ni。 11. 一種製成接點的方法，包含以下步驟： 將一電介質層沈積於具有一電晶體的一基體上； 餘刻在該電介質層中延伸至一源極區域的一第一 開口； 在該源極區域上形成一絕緣體； 在該絕緣體上形成一接點金屬，該絕緣體將該接點 金屬與該源極區域相分離；及 填充實質上所有的該第一開口，其中在該第一開口 予以填充之後，該接點金屬保持與該源極區域相分離。 12. 如申請專利範圍第11項所述之方法，其中該絕緣體具 19 201034185 有大約4奈米或更小的一厚度。 13·如申請專利範圍第12項所述之方法，其中該絕緣體具 有大約1奈米或更小的一厚度。 14. 如申請專利範圍第12項所述之方法，其中形成該絕緣 體之步驟包含形成該絕緣體的一保形層。 15. 如申請專利範圍第n項所述之方法，其中該電晶體是 一多閘極電晶體，其中該絕緣體形成於該多閘極電晶體 之一 ·鰭片的一頂部上及側雙上，以產生一絕緣體頂部及 絕緣體側壁，且其中該接點金屬形成於該絕緣體頂部上 及該等絕緣體側壁上。 16. —種裝置，包含： 一電晶體，其具有一源極區域及一没極區域； 一源極接點，其中該源極接點不直接地相鄰於該源 極區域，且其中一第一絕緣層將該源極接點與該源極區 域相分離；及 一汲極接點，其中該汲極接點不直接地相鄰於該汲 極區域’且其中一第二絕緣層將該汲極接點與該汲極區 域相分離。 17. 如申請專利範圍第16項所述之裝置，其中該電晶體是 一多閘極電晶體，該源極區域具有一頂部及側壁，且該 沒極區域具有一頂部及側壁。 18. 如申請專利範圍第μ項所述之裝置，其中該源極接點 及該汲極接點都不包含一石夕化物。 19. 如申請專利範圍第16項所述之裝置，其中該第一及第 20 201034185 二絕緣層包含ΗίΌ2。 20.如申請專利範圍第16項所述之裝置，其中該電晶體具 有包令—第三至五族材料的一通道區域。
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
TWI495107B (zh) * 2012-11-08 2015-08-01 Taiwan Semiconductor Mfg Co Ltd 半導體裝置之接觸結構、金氧半導體場效電晶體、及半導體裝置之製造方法
US10332921B2 (en) 2015-10-09 2019-06-25 Sony Semiconductor Solutions Corporation Solid-state image sensing device and method for manufacturing the same, and electronic device
TWI844516B (zh) * 2017-08-07 2024-06-11 日商索尼半導體解決方案公司 電性連接構造、半導體裝置及電子機器

Families Citing this family (78)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US20100267230A1 (en) 2009-04-16 2010-10-21 Anand Chandrashekar Method for forming tungsten contacts and interconnects with small critical dimensions
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8232627B2 (en) 2009-09-21 2012-07-31 International Business Machines Corporation Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device
US8709948B2 (en) * 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US8912574B2 (en) * 2010-12-14 2014-12-16 International Business Machines Corporation Device isolation with improved thermal conductivity
US8415751B2 (en) * 2010-12-30 2013-04-09 Intel Corporation Method to reduce contact resistance of N-channel transistors by using a III-V semiconductor interlayer in source and drain
US9362376B2 (en) 2011-11-23 2016-06-07 Acorn Technologies, Inc. Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
CN107195684B (zh) * 2011-12-30 2020-12-08 英特尔公司 环绕式沟槽接触部结构和制作方法
TWI602283B (zh) 2012-03-27 2017-10-11 諾發系統有限公司 鎢特徵部塡充
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9136383B2 (en) * 2012-08-09 2015-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9105490B2 (en) 2012-09-27 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of semiconductor device
US9287138B2 (en) 2012-09-27 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET low resistivity contact formation method
US10304826B2 (en) 2012-12-28 2019-05-28 Taiwan Semiconductor Manufacturing Company Complimentary metal-oxide-semiconductor (CMOS) with low contact resistivity and method of forming same
US9397217B2 (en) * 2012-12-28 2016-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact structure of non-planar semiconductor device
CN104051511B (zh) * 2013-03-14 2017-03-01 台湾积体电路制造股份有限公司 半导体器件及其制造方法
US9508716B2 (en) 2013-03-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing a semiconductor device
US9240480B2 (en) * 2013-03-14 2016-01-19 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-oxide-semiconductor field-effect transistor with metal-insulator semiconductor contact structure to reduce Schottky barrier
CN104051530B (zh) * 2013-03-14 2016-12-28 台湾积体电路制造股份有限公司 金属氧化物半导体场效应晶体管
US9153486B2 (en) * 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US9059095B2 (en) * 2013-04-22 2015-06-16 International Business Machines Corporation Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
US9219062B2 (en) * 2013-05-24 2015-12-22 GlobalFoundries, Inc. Integrated circuits with improved source/drain contacts and methods for fabricating such integrated circuits
EP3050091B1 (en) * 2013-09-27 2019-04-10 Intel Corporation Ge and iii-v channel semiconductor devices having maximized compliance and free surface relaxation
US9941271B2 (en) 2013-10-04 2018-04-10 Avago Technologies General Ip (Singapore) Pte. Ltd. Fin-shaped field effect transistor and capacitor structures
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
US9165838B2 (en) 2014-02-26 2015-10-20 Taiwan Semiconductor Manufacturing Company Limited Methods of forming low resistance contacts
US9412836B2 (en) 2014-03-06 2016-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts for transistors
US9299781B2 (en) * 2014-04-01 2016-03-29 Globalfoundries Inc. Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material
US9390939B2 (en) 2014-05-29 2016-07-12 Globalfoundries Inc. Methods of forming MIS contact structures for semiconductor devices and the resulting devices
US9385201B2 (en) 2014-06-06 2016-07-05 Stmicroelectronics, Inc. Buried source-drain contact for integrated circuit transistor devices and method of making same
US9209305B1 (en) 2014-06-06 2015-12-08 Stmicroelectronics, Inc. Backside source-drain contact for integrated circuit transistor devices and method of making same
US9478411B2 (en) 2014-08-20 2016-10-25 Lam Research Corporation Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS
US9887129B2 (en) 2014-09-04 2018-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with contact plug
US9997405B2 (en) 2014-09-30 2018-06-12 Lam Research Corporation Feature fill with nucleation inhibition
US9543438B2 (en) * 2014-10-15 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Contact resistance reduction technique
US9391152B1 (en) 2015-01-20 2016-07-12 International Business Machines Corporation Implantation formed metal-insulator-semiconductor (MIS) contacts
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
FR3033447B1 (fr) * 2015-03-03 2017-03-24 Commissariat Energie Atomique Transistor a connexions mis et procede de fabrication
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9589851B2 (en) * 2015-07-16 2017-03-07 International Business Machines Corporation Dipole-based contact structure to reduce metal-semiconductor contact resistance in MOSFETs
US9735111B2 (en) 2015-09-23 2017-08-15 International Business Machines Corporation Dual metal-insulator-semiconductor contact structure and formulation method
US10217825B2 (en) 2015-11-19 2019-02-26 Toyko Electron Limited Metal-insulator-semiconductor (MIS) contacts and method of forming
US9711402B1 (en) * 2016-03-08 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming contact metal
US9613855B1 (en) 2016-04-05 2017-04-04 Globalfoundries Inc. Methods of forming MIS contact structures on transistor devices in CMOS applications
US9831123B2 (en) 2016-04-05 2017-11-28 Globalfoundries Inc. Methods of forming MIS contact structures on transistor devices
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
US10388576B2 (en) 2016-06-30 2019-08-20 International Business Machines Corporation Semiconductor device including dual trench epitaxial dual-liner contacts
KR101836258B1 (ko) 2016-07-05 2018-03-08 현대자동차 주식회사 반도체 소자 및 그 제조 방법
US9917060B1 (en) * 2016-10-21 2018-03-13 International Business Machines Corporation Forming a contact for a semiconductor device
DE112017005855T5 (de) 2016-11-18 2019-08-01 Acorn Technologies, Inc. Nanodrahttransistor mit Source und Drain induziert durch elektrische Kontakte mit negativer Schottky-Barrierenhöhe
FR3059144B1 (fr) 2016-11-22 2019-05-31 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
FR3059145B1 (fr) * 2016-11-22 2019-07-19 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans un circuit integre et circuit integre correspondant
FR3059146A1 (fr) 2016-11-22 2018-05-25 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre, et circuit integre correspondant
US10516030B2 (en) 2017-01-09 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact plugs and methods forming same
WO2018182665A1 (en) * 2017-03-31 2018-10-04 Intel Corporation Tunneling contacts for a transistor
US10186456B2 (en) 2017-04-20 2019-01-22 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming contact plugs with reduced corrosion
US10141225B2 (en) 2017-04-28 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gates of transistors having reduced resistivity
SG11202001268TA (en) 2017-08-14 2020-03-30 Lam Res Corp Metal fill process for three-dimensional vertical nand wordline
US10366982B2 (en) 2017-11-30 2019-07-30 Taiwan Semiconductor Manufacturing Co., Ltd. Structure with embedded memory device and contact isolation scheme
US10847413B2 (en) * 2017-11-30 2020-11-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming contact plugs for semiconductor device
KR20200140391A (ko) 2018-05-03 2020-12-15 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
US10840335B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance
US10840336B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods
US10847618B2 (en) 2018-11-16 2020-11-24 Atomera Incorporated Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance
US10854717B2 (en) 2018-11-16 2020-12-01 Atomera Incorporated Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance
US10818755B2 (en) 2018-11-16 2020-10-27 Atomera Incorporated Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance
US10840337B2 (en) 2018-11-16 2020-11-17 Atomera Incorporated Method for making a FINFET having reduced contact resistance
CN113424300A (zh) 2018-12-14 2021-09-21 朗姆研究公司 在3d nand结构上的原子层沉积
KR20210141762A (ko) 2019-04-11 2021-11-23 램 리써치 코포레이션 고 단차 커버리지 (step coverage) 텅스텐 증착
KR20220047333A (ko) 2019-08-12 2022-04-15 램 리써치 코포레이션 텅스텐 증착
CN118280825B (zh) * 2024-06-04 2024-08-27 粤芯半导体技术股份有限公司 一种半导体结构及其制作方法

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62298168A (ja) * 1986-06-18 1987-12-25 Hitachi Ltd 半導体装置
US5792703A (en) * 1996-03-20 1998-08-11 International Business Machines Corporation Self-aligned contact wiring process for SI devices
US6004849A (en) 1997-08-15 1999-12-21 Advanced Micro Devices, Inc. Method of making an asymmetrical IGFET with a silicide contact on the drain without a silicide contact on the source
JP2000183178A (ja) 1998-12-16 2000-06-30 Hitachi Ltd 半導体集積回路装置
JP2000216241A (ja) * 1999-01-20 2000-08-04 Applied Materials Inc 半導体装置の製造方法
US6724088B1 (en) * 1999-04-20 2004-04-20 International Business Machines Corporation Quantum conductive barrier for contact to shallow diffusion region
JP4733810B2 (ja) 2000-05-25 2011-07-27 ルネサスエレクトロニクス株式会社 半導体記憶装置およびその製造方法
US6511905B1 (en) * 2002-01-04 2003-01-28 Promos Technologies Inc. Semiconductor device with Si-Ge layer-containing low resistance, tunable contact
US6900481B2 (en) * 2002-02-21 2005-05-31 Intel Corporation Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors
US7084423B2 (en) 2002-08-12 2006-08-01 Acorn Technologies, Inc. Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
JP2004172178A (ja) * 2002-11-18 2004-06-17 Toshiba Corp 半導体装置及び半導体装置の製造方法
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
JP3762378B2 (ja) * 2003-03-20 2006-04-05 株式会社東芝 半導体装置及びその製造方法
US7153784B2 (en) * 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7176090B2 (en) * 2004-09-07 2007-02-13 Intel Corporation Method for making a semiconductor device that includes a metal gate electrode
JP2006100387A (ja) * 2004-09-28 2006-04-13 Toshiba Corp 電界効果トランジスタ及びその製造方法
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7518196B2 (en) * 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US7294890B2 (en) * 2005-03-03 2007-11-13 Agency For Science, Technology And Research Fully salicided (FUSA) MOSFET structure
CN101288179B (zh) * 2005-07-27 2010-05-26 英飞凌科技奥地利股份公司 具有漂移区和漂移控制区的半导体器件
US20070048984A1 (en) * 2005-08-31 2007-03-01 Steven Walther Metal work function adjustment by ion implantation
US7615433B2 (en) * 2005-12-15 2009-11-10 Chartered Semiconductor Manufacturing, Ltd. Double anneal with improved reliability for dual contact etch stop liner scheme
JP2007258481A (ja) 2006-03-23 2007-10-04 Fujitsu Ltd 半導体装置及びその製造方法
US7566605B2 (en) 2006-03-31 2009-07-28 Intel Corporation Epitaxial silicon germanium for reduced contact resistance in field-effect transistors
US7425500B2 (en) 2006-03-31 2008-09-16 Intel Corporation Uniform silicide metal on epitaxially grown source and drain regions of three-dimensional transistors
US20070284662A1 (en) 2006-06-09 2007-12-13 International Business Machines Corporation Microelectronic structure including high current density resistor
US7355254B2 (en) 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts
KR101036771B1 (ko) * 2006-07-25 2011-05-25 닛본 덴끼 가부시끼가이샤 반도체 장치 및 그 제조 방법
KR100809330B1 (ko) * 2006-09-04 2008-03-05 삼성전자주식회사 게이트 스페이서로 인한 응력이 배제된 반도체 소자 및 그제조 방법
US20080206991A1 (en) 2007-02-22 2008-08-28 Nadia Rahhal-Orabi Methods of forming transistor contacts and via openings
JP2008244093A (ja) * 2007-03-27 2008-10-09 Elpida Memory Inc 半導体装置の製造方法
US7861406B2 (en) 2007-03-29 2011-01-04 Intel Corporation Method of forming CMOS transistors with dual-metal silicide formed through the contact openings
US7704858B2 (en) 2007-03-29 2010-04-27 Intel Corporation Methods of forming nickel silicide layers with low carbon content
US7709866B2 (en) 2007-06-26 2010-05-04 Intel Corporation Method for forming semiconductor contacts
JP5148207B2 (ja) 2007-08-24 2013-02-20 株式会社東芝 画像処理システム、ｘ線診断装置およびその画像処理プログラム、並びに画像再構成装置
US7659157B2 (en) * 2007-09-25 2010-02-09 International Business Machines Corporation Dual metal gate finFETs with single or dual high-K gate dielectric
US7968457B2 (en) * 2008-08-26 2011-06-28 Intel Corporation Sandwiched metal structure silicidation for enhanced contact
US9934976B2 (en) 2008-12-18 2018-04-03 Intel Corporation Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
US7964490B2 (en) * 2008-12-31 2011-06-21 Intel Corporation Methods of forming nickel sulfide film on a semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
US8952541B2 (en) 2008-12-19 2015-02-10 Intel Corporation Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
US9437706B2 (en) 2008-12-19 2016-09-06 Intel Corporation Method of fabricating metal-insulator-semiconductor tunneling contacts using conformal deposition and thermal growth processes
TWI495107B (zh) * 2012-11-08 2015-08-01 Taiwan Semiconductor Mfg Co Ltd 半導體裝置之接觸結構、金氧半導體場效電晶體、及半導體裝置之製造方法
US10332921B2 (en) 2015-10-09 2019-06-25 Sony Semiconductor Solutions Corporation Solid-state image sensing device and method for manufacturing the same, and electronic device
TWI844516B (zh) * 2017-08-07 2024-06-11 日商索尼半導體解決方案公司 電性連接構造、半導體裝置及電子機器

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