FR3059144B1 - Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant - Google Patents

Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant Download PDF

Info

Publication number
FR3059144B1
FR3059144B1 FR1661346A FR1661346A FR3059144B1 FR 3059144 B1 FR3059144 B1 FR 3059144B1 FR 1661346 A FR1661346 A FR 1661346A FR 1661346 A FR1661346 A FR 1661346A FR 3059144 B1 FR3059144 B1 FR 3059144B1
Authority
FR
France
Prior art keywords
integrated circuit
electrical discontinuity
level
metallization
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1661346A
Other languages
English (en)
Other versions
FR3059144A1 (fr
Inventor
Christian Rivero
Pascal FORNARA
Guilhem Bouton
Mathieu Lisart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1661346A priority Critical patent/FR3059144B1/fr
Priority to US15/596,877 priority patent/US10049982B2/en
Priority to CN201720572060.XU priority patent/CN206877986U/zh
Priority to CN201710365524.4A priority patent/CN108091577A/zh
Publication of FR3059144A1 publication Critical patent/FR3059144A1/fr
Application granted granted Critical
Publication of FR3059144B1 publication Critical patent/FR3059144B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means

Abstract

Circuit intégré, comprenant une partie d'interconnexion (PITX) comportant au moins un niveau de vias (V1) situé entre un niveau de métallisation inférieur (M2), recouvert d'une couche d'encapsulation isolante (C1) et d'une couche isolante inter niveaux de métallisation (C2), et un niveau de métallisation supérieur (M2), et au moins une discontinuité électrique (CS3) entre au moins un via (V11) dudit niveau de vias et au moins une piste (P1) dudit niveau de métallisation inférieur, ladite au moins une discontinuité électrique comportant une couche isolante additionnelle (CS3), de composition identique à celle de la couche isolante inter niveaux de métallisation (C2), située entre ledit au moins un via (V11) et ladite au moins une piste (P10) et bordée par ladite couche d'encapsulation (C1).
FR1661346A 2016-11-22 2016-11-22 Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant Active FR3059144B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1661346A FR3059144B1 (fr) 2016-11-22 2016-11-22 Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
US15/596,877 US10049982B2 (en) 2016-11-22 2017-05-16 Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuit
CN201720572060.XU CN206877986U (zh) 2016-11-22 2017-05-22 集成电路和物体
CN201710365524.4A CN108091577A (zh) 2016-11-22 2017-05-22 在集成电路的互连部分中形成电中断的方法及集成电路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1661346A FR3059144B1 (fr) 2016-11-22 2016-11-22 Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
FR1661346 2016-11-22

Publications (2)

Publication Number Publication Date
FR3059144A1 FR3059144A1 (fr) 2018-05-25
FR3059144B1 true FR3059144B1 (fr) 2019-05-31

Family

ID=59152931

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1661346A Active FR3059144B1 (fr) 2016-11-22 2016-11-22 Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant

Country Status (3)

Country Link
US (1) US10049982B2 (fr)
CN (2) CN206877986U (fr)
FR (1) FR3059144B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3059144B1 (fr) * 2016-11-22 2019-05-31 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61147551A (ja) * 1984-12-21 1986-07-05 Nec Corp 半導体装置
AU2974297A (en) * 1997-06-13 1998-12-30 Tomasz Kowalski Method for making an integrated circuit and integrated circuit produced by said method
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US6888251B2 (en) 2002-07-01 2005-05-03 International Business Machines Corporation Metal spacer in single and dual damascene processing
US7402514B2 (en) * 2003-01-24 2008-07-22 Texas Instruments Incorporated Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer
US20080174022A1 (en) * 2007-01-22 2008-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and fabrication method thereof
JP2008205019A (ja) 2007-02-16 2008-09-04 Toshiba Corp 半導体集積回路およびその製造方法
US7994042B2 (en) * 2007-10-26 2011-08-09 International Business Machines Corporation Techniques for impeding reverse engineering
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
DE102013224060B4 (de) 2013-11-26 2020-04-02 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Erschweren von optischem Reverse Engineering
US9691709B2 (en) 2015-02-26 2017-06-27 International Business Machines Corporation Semiconductor device security
US9502405B1 (en) 2015-08-27 2016-11-22 International Business Machines Corporation Semiconductor device with authentication code
FR3059144B1 (fr) * 2016-11-22 2019-05-31 Stmicroelectronics (Rousset) Sas Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant

Also Published As

Publication number Publication date
CN206877986U (zh) 2018-01-12
CN108091577A (zh) 2018-05-29
FR3059144A1 (fr) 2018-05-25
US10049982B2 (en) 2018-08-14
US20180145027A1 (en) 2018-05-24

Similar Documents

Publication Publication Date Title
EP3010038A3 (fr) Structure de recouvrement pour alimentation ayant des connexion de fils et son procédé de fabrication
EP2337067A3 (fr) Realisation de structures d'interconnexions TSV formées d'un contour isolant et d'une zône conductrice située dans le contour et disjointe du contour
BR112017003175A2 (pt) pacote de múltiplas matrizes e método para formar um pacote de múltiplas matrizes
FR3059144B1 (fr) Procede de formation d'au moins une discontinuite electrique dans une partie d'interconnexion d'un circuit integre sans ajout de materiau supplementaire, et circuit integre correspondant
WO2012166451A3 (fr) Structures conductrices, systèmes et dispositifs comprenant des structures conductrices et procédés associés
BRPI0415131A (pt) condensar furo cego em núcleo de três camadas
JP2013201441A5 (fr)
FR3069044B1 (fr) Cuve etanche et thermiquement isolante
CA2559372A1 (fr) Element cathodique pour l'equipement d'une cellule d'electrolyse destinee a la production d'aluminium
EP2040295A3 (fr) Agencement doté d'un dispositif de liaison et d'au moins un composant semi-conducteur
MX2020014080A (es) Pelicula de multiples capas con propiedades opticas conmutables electricamente y recubrimiento electrico mejorado.
MX2016005460A (es) Cristal con al menos dos elementos de conexion electrica y un conductor de conexion.
FR2980622B1 (fr) Element electrique comprenant une couche d'un materiau polymerique a gradient de conductivite electrique
EP3876276A3 (fr) Dispositif de mémoire tridimensionnel contenant une isolation de grille de sélection de drain à plusieurs niveaux et procédés de fabrication associés
PH12017501997A1 (en) Lead carrier with print formed package components and conductive path redistribution structures
EP2738796A3 (fr) Procédé de réalisation d'une structure pour l'assemblage de dispositifs microélectroniques en puce retournée comprenant un bloc isolant de guidage d'un élément de connexion et dispositif correspondant
FR3059467B1 (fr) Transistor a heterojonction a structure verticale
US20180247892A1 (en) Semiconductor device, semiconductor integrated circuit, and load driving device
WO2018033510A3 (fr) Dispositif électronique à structures de banc
WO2014165247A3 (fr) Condensateurs utilisant des structures d'alumine poreuse
JP2016525719A5 (fr)
FR3082050B1 (fr) Via interne avec contact ameliore pour couche semi-conductrice superieure d'un circuit 3d
FR3058567B1 (fr) Circuit integre comportant une structure antifusible, et procede de realisation
AR107024A1 (es) Aislamiento equipado con un dispositivo conductor de electricidad que posee una resistencia mejorada a los análisis de ciclos de temperatura
JP2015032733A5 (fr)

Legal Events

Date Code Title Description
PLFP Fee payment

Year of fee payment: 2

PLSC Publication of the preliminary search report

Effective date: 20180525

PLFP Fee payment

Year of fee payment: 3

PLFP Fee payment

Year of fee payment: 4

PLFP Fee payment

Year of fee payment: 5

PLFP Fee payment

Year of fee payment: 6

PLFP Fee payment

Year of fee payment: 7

PLFP Fee payment

Year of fee payment: 8