CN102239546A - 金属-绝缘体-半导体隧穿接触 - Google Patents

金属-绝缘体-半导体隧穿接触 Download PDF

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CN102239546A
CN102239546A CN2009801392360A CN200980139236A CN102239546A CN 102239546 A CN102239546 A CN 102239546A CN 2009801392360 A CN2009801392360 A CN 2009801392360A CN 200980139236 A CN200980139236 A CN 200980139236A CN 102239546 A CN102239546 A CN 102239546A
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transistor
contact
insulator
insulating barrier
source area
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N·慕克吉
G·杜威
M·V·梅茨
J·卡瓦列罗斯
R·S·周
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Intel Corp
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Abstract

一种到源极区或漏极区的接触。所述接触具有导电材料，但是该导电材料通过绝缘体与所述源极区或者漏极区分隔开。

Description

金属-绝缘体-半导体隧穿接触
背景技术
在集成电路的制造中，诸如晶体管之类的器件形成在晶圆上并且使用多个金属化层将其连接在一起。如本领域所公知的，金属化层包括用作对器件进行互连的电气通道的过孔和互连。接触将过孔和互连连接至器件。
附图说明
图1是示出了具有电接触的器件的截面侧视图，其中导电接触材料通过绝缘体与被接触区分隔开。
图2是示出了可以制造如图1所示的器件的一种方法的流程图。
图3是示出了沉积在晶体管上的第一ILD层的截面侧视图。
图4是示出了形成在第一ILD层中的沟槽的截面侧视图。
图5是示出了沉积在沟槽中的绝缘层的截面侧视图。
图6是示出了沉积在绝缘层上的导电层的截面侧视图。
图7是示出了填充材料的截面侧视图。
图8是示出了其它ILD层和导电层的截面侧视图。
图9是示出了多栅极晶体管的等视图。
图10是切过鳍片(fin)的源极区部分且示出了第一ILD层的截面侧视图。
图11是示出了形成在第一ILD层中的沟槽的截面侧视图。
图12是示出了形成在鳍片的源极区的顶表面和侧壁上的绝缘层、形成在绝缘层上的导电层116、以及基本填充沟槽的剩余体积的填充材料的截面侧视图。
图13是示出了缺乏填充材料的实施例的截面侧视图。
图14是示出了同一衬底上的第一晶体管和第二晶体管的截面侧视图。
具体实施方式
以下描述中讨论了具有将导电接触与器件分离开的绝缘体的半导体器件的接触的各种实施例。相关领域的技术人员将意识到可以在没有一个或多个具体细节，或者利用其它替代和/或其它的方法、材料、或部件的情况下来实施各实施例。另外，未具体示出或描述公知的结构、材料或者操作以避免混淆本发明的各实施例的方面。类似地，出于解释的目的，阐述了具体的数字、材料和配置，以提供对本发明的透彻的理解。然而，可以无需具体的细节来实践本发明。此外，应该理解的是，附图中所示的各实施例是示意性表示并且无需按比例绘制。
整个说明书提到的“一个实施例”或“实施例”指的是结合实施例描述的特定特征、结构、材料、或特性被包括在本发明的至少一个实施例中，但不表示它们出现在每一实施例中。因此，出现在整个说明书各地方的短语“在一个实施例中”或“在实施例中”不必指本发明的相同实施例。此外，特定的特征、结构、材料、或特性可以通过任何合适的方式结合到一个或多个实施例中。在其它实施例中，可以包括各种其它层和/或结构，和/或可能省略所描述的特征。
可以以最有助于理解本发明的方式将各操作描述为依次进行的多个离散的操作。然而，不应将描述的顺序理解为暗示这些操作是必须依赖的顺序。特别地，这些操作无需按照所描述的顺序来执行。描述的操作与所描述的实施例相比可能串行或并行地通过不同的顺序来执行。在其它实施例中，可能执行各种其它的操作和/或可能省略描述的操作。
图1是示出了具有电接触的器件100的截面侧视图，其中通过绝缘体114将导电接触材料116与接触的区域106、108分隔开。在实施例中，器件100是晶体管。晶体管包括源极区106和漏极区108。存在到源极区106和漏极区108的接触。这些接触包括通过绝缘体114与源极区106和漏极区108分离开的导电材料116。这种配置避免了用于到晶体管的硅化物或锗化物接触。
通过避免使用硅化物或锗化物接触，器件100的一些实施例可以允许使用共形的接触形成工艺，其允许接触形成在更小的沟槽中，从而使得器件100实现更小的尺寸。器件100的一些实施例更易于制造，例如不再需要用于硅化物或锗化物所需的超纯金属沉积。另外，随着器件100变得更小，可以利用更少的半导电材料来形成硅化物或锗化物。器件100的一些实施例避免了在不使用硅化物或锗化物形成器件100的一部分的半导电材料的过度消耗问题。而且，硅化物等的形成可能对器件施加应变，或限制由其它结构和材料引入的应变。通过省略硅化物，能够增加获得的应变变型可能性，并且从而使得器件100的性能更好。
在示出的示例中，器件100包括衬底102。该衬底102可以包括能够用作在其上制备半导体器件的基础的任何材料。在一个示例中，衬底102是含硅的衬底，但是在其它示例中可以使用其它材料。衬底102可以使用体硅或绝缘体上硅子结构来形成。在其它实施方式中，可以使用替代材料来形成衬底102，可能与硅组合或不组合，所述替代材料包括但并不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、碲化镓、或其它III-V族材料。衬底102可以是单一材料，或具有多层和/或具有多种结构。尽管在这里描述了一些可以形成衬底102的材料的示例，但是任何能够用作在其上制备器件的基础的材料都落入本发明的精神和范围内。
示例中示出的器件100包括晶体管。所述晶体管包括栅极104、源极区106和漏极区108。晶体管可以包括几个其它的区域和结构，出于简洁，此处将其省略。尽管与典型地形成在硅衬底上一样示出为平面晶体管，但是这种晶体管可以是多栅极晶体管，可以位于不同类型的材料(例如III-V族材料)上；这里所描述的接触不限于晶体管或器件100的特定类型。
在示出的示例中，在晶体管上存在第一层间电介质层110(ILD)。到源极区106和漏极区108的接触形成在穿过第一ILD层110的沟槽中。出于简洁，应该注意的是这里未示出到栅极104的接触，但是正常情况下是存在的。到栅极104的接触类似于所描述和示出的到源极区106和漏极区108的接触，这种接触可以用在各种实施例中。这里描述的接触不限于用在源极区106和漏极区108，还能够与栅极104或其它部件一起使用。接触实现了晶体管的操作、各晶体管之间以及器件100和外部器件之间的电气连通。
在所示出的实施例中，接触包括绝缘层114，所述绝缘层114与沟槽共形并且与源极区106和漏极区108相邻。与绝缘层114相邻的是导电层116。绝缘层114将导电层116与源极区106和漏极区108(或任何用于接触的部件)分隔开。虽然导电层116并不直接接触源极区106和漏极区108，但仍用作电接触。这通过绝缘层114全部或部分从半导体源极区106和漏极区108解除金属费米能级的钉扎来实现。因此，与导体直接接触源极区106和漏极区108的情况相比，在导电层116和源极区106、漏极区108之间包括绝缘层114实际上可以减小接触的电阻。在一些实施例中，在低掺杂(掺杂水平～1×1017原子/平方厘米)硅上的这种接触允许获得特定的接触电阻率ρc，其近似为1×10-7欧姆-平方微米(欧姆-平方米)或更低，低于相同硅掺杂水平的传统硅化物(例如硅化镍、硅化钛、硅化钴)接触的5-10倍。这种类型的接触还能够根据需要调节肖特基势垒的高度和接触电阻来优化器件100的性能。
在所示出的实施例中，存在填充材料118，所述填充材料118基本上填充了穿过第一ILD层110的未被绝缘层114和导电层116占据的沟槽的剩余部分。填充材料118可能是金属或其它导体，或其它类型的材料。在一些实施例中，没有分离的填充材料118。相反地，导体层116可以基本上填充了穿过第一ILD层110的未被绝缘层114占据的沟槽的剩余部分。
图2是示出了可以用来制造图1所示的器件100的一种方法的流程图200。在其它的实施例中其它的方法也是可能的。在该示例方法的开始处，包括栅极104、源极106和漏极108的晶体管已经形成在衬底102上。在晶体管上沉积202第一ILD层。
图3是示出了根据本发明一个实施例的在晶体管上沉积202的第一ILD层110的截面侧视图。可以使用在集成电路结构中常用的电介质层公知的材料来形成第一ILD层110，例如低k电介质材料。这种电介质材料包括但不限于诸如二氧化硅(SiO2)和掺碳氧化物(CDO)的氧化物、氮化硅、诸如全氟环丁烷或聚四氟乙烯，氟硅酸盐玻璃(FSG)的有机聚合物、以及诸如硅倍半氧烷、硅氧烷或硅酸盐玻璃的有机硅酸盐。电介质的第一ILD层110可以包括微孔或其它空隙以进一步减小其介电常数。
返回图2，在第一ILD层110中形成开口204。图4是示出了在第一ILD层110中形成204的沟槽112的截面侧视图。可以采用任何适当的方法来形成204沟槽112，例如采用一个或多个湿法或干法刻蚀工艺。如图所示，沟槽112仅到达源极区106和漏极区108。然而，也可以形成到栅极104的接触和沟槽112，尽管在这里未特别示出和描述。
如图2所示，在形成204沟槽112之后，可以在沟槽112中沉积206绝缘层114。图5是示出了在沟槽112中沉积206的绝缘层114的截面侧视图。在一些实施例中，绝缘层114可以通过诸如化学气相沉积(CVD)、原子层沉积(ALD)的共形沉积工艺来沉积206，可以通过热生长工艺(例如衬底材料的氧化物、氮化物或氧氮化物的热生长)来形成206，或者通过另一适当的沉积工艺来形成206。绝缘层114可以包括诸如HfO2、A1O、ZrO、Si3N4，SiO2、SiON或其它绝缘电介质材料的介电材料。在一些实施例中，选择绝缘层114的厚度以实现随后沉积的导体的费米能级的不钉扎。为此，在一些实施例中绝缘层114可以非常薄，例如大约小于4nm，在其它实施例中大约小于3nm，或者1nm或者更小。在实施例中，绝缘层114为5埃和10埃之间。绝缘层114也可以使用其它的厚度。应该注意的是，尽管将绝缘层114示出为共形沉积的，但这并不是必须的。在一些实施例中，例如在利用热生长绝缘层114的实施例中，绝缘层114可以是非共形沉积的。
再次参考图2，在绝缘层114上沉积208导电层116。图6是示出了在绝缘层114上沉积208的导电层116的截面侧视图。可以通过诸如化学气相沉积(CVD)、原子层沉积(ALD)的共形沉积工艺、化学电镀或其它适当的沉积工艺来沉积208导电层116。在一些实施例中，例如在导电层116填充沟槽112的剩余部分(图13为示出了这种实施例的截面侧视图)或者沟槽112足够大的实施例中，可以使用诸如PVD的非共形沉积技术来沉积208导电层。
在一些实施例中，导电层116可以是金属或包含金属。可以使用各种金属。在一些实施例中，可以基于针对晶体管的类型的适当逸出功来选择导电层116的材料(用于PMOS晶体管的高逸出功金属，用于NMOS的低逸出功金属，其中“高”逸出功为5ev以上，“低”逸出功为大约3.2ev或以下)，尽管这并不是必须的。用于导电层116的材料包括铝、镍、镁、铜或其它金属。导电金属碳化物、氮化物或其它材料也可以用于导电层116。可以将任何适当的厚度用于导电层116。在一些实施例中，导电层116厚度大于100埃，其中在一些实施例中，导电层116比100埃厚得多。
在一些实施例中，栅极104可以是被去除的牺牲栅极，并且是在沉积第一ILD层110之后形成的新的栅极。在这种实施例中，新栅极可以利用相同的工艺且与导电层114同时形成。
这里所描述的绝缘层114和导电层116的形成允许在非常窄的沟槽112中形成了接触。用来形成在硅化物和锗化物中使用的超纯金属的工艺在与非常窄的沟槽112一起使用时可能出问题。因此，通过使用这里所描述的绝缘体上导体接触，比使用硅化物或锗化物接触能够缩小沟槽112至更小尺寸。
再次参考图2，填充210沟槽112的剩余体积。图7是示出了填充材料118的截面侧视图。该填充材料118可以是导电材料或其它任何合适的材料，可以是单一材料，也可以是多种材料，并且可以通过任何适当的方法来沉积。如先前所提到的，在实施例中导电层116可以填充沟槽。在这种实施例中未使用独立的填充材料118，如图13所示。
再次参考图2，然后可以形成其它的ILD层和导电层。图8是示出了其它ILD层和导电层的截面侧视图。在图8中，对绝缘层114、导电层116和填充材料118进行平坦化以基本上与第一ILD层110的顶表面共面。在平坦化之后，沟槽112中到源极区106的导电层116就与沟槽112中到漏极区108的导电层116不连续了。因此可以将导电层116考虑为左边到源极区106的沟槽112中的第一导电层和右边到漏极区108的沟槽中第二导电层。
第二ILD层120沉积在第一ILD层110上。在第二ILD层120中的过孔122和引线124通过沟槽112中的接触被导电连接到源极区106和漏极区108。第三ILD层126沉积在第二ILD层120上。在第三ILD层126中的过孔122和引线124穿过沟槽112中的接触被导电连接到源极区106和漏极区108。其它实施例中可能还存在其它ILD层和导体。
图9是示出了多栅极晶体管的等视图。尽管图1和3-8示出了形成为平面晶体管的接触，但相同的绝缘体上导体的接触也可用到其它类型的晶体管中，例如三栅极晶体管。图9所示的三栅极晶体管包括鳍片130。在鳍片130的任一侧有隔离区138。在鳍片130上邻近鳍片130的顶部和相对两侧壁上有栅极电极132。在栅极电极132的一侧上是源极区134，在栅极电极132另一侧上是漏极区。注意尽管图9仅具有指向用于源极区134和漏极区136的鳍片132的顶表面的箭头，但是源极区134和漏极区136可以沿着鳍片130的顶表面和侧壁延伸。
图10是从切过鳍片130的源极区134的截面侧视图，其示出了与如图3所示如何在平面晶体管上形成第一ILD层110类似形成的第一ILD层110。图11是示出了在第一ILD层110中形成的沟槽112的截面侧视图。由该沟槽112暴露源极区134。
图12是截面侧视图，其示出了形成在鳍片130的源极区134的顶表面和侧壁上的绝缘层114、形成在绝缘层114上的导电层116以及基本上填充沟槽112的剩余体积的填充材料118。这些材料可以如上所述关于平面晶体管类似地来形成。与平面晶体管一样，绝缘层114将导电层116与源极区134分离开，然而这样通过隧穿可以实现比导体接触源极区更低的接触电阻。而且，绝缘体114和导体116的共形沉积也使得鳍片130基本上完整。如果形成硅化物、锗化物或类似的接触，接触可能消耗更多的鳍片130的半导体材料，在鳍片130非常小的情况下这将形成非功能(non-functioning)器件。
图14是示出了同一衬底102上的第一晶体管302和第二晶体管304的截面侧视图。晶体管304包括硅化物、锗化物等等的接触306、或具有与源极区106和漏极区108接触的导体。曲线A-A表明晶体管302、304可以彼此分隔开，而不是正好彼此相邻。在一些实施例中，衬底102上的一些晶体管，例如晶体管302，可以包括具有导体116的接触，其通过绝缘层114与源极区106和/或漏极区108分隔开，然而同一衬底上的其它晶体管，例如晶体管304，可以包括由硅化物、锗化物或其它材料形成的接触306，其具有与源极区106和/或漏极区108接触的导体。例如，具有通过绝缘体114与源极区106和漏极区108分隔开的导体116的接触的晶体管302是NMOS晶体管，而晶体管304可以是PMOS晶体管，或反之亦然。在实施例中，衬底上的一种类型(N或P型)的所有晶体管具有同一类型的接触，而所有相反类型的晶体管可以具有另一类型的接触。在替换实施例中，一些选择晶体管可以具有由通过绝缘层114与源极区106和/或漏极区108分隔开的导体116组成的接触，而其余的晶体管具有更传统的接触306。这些选择的晶体管可以是一种类型(N或P型)，或者可以包括多种类型(N和P型)的晶体管。在另一实施例中，衬底102上的所有晶体管具有导体116的接触，其中116通过绝缘层114与源极区106和漏极区108分隔开。在再一实施例中，一种类型的一些或所有晶体管可以具有绝缘层114、导电层116和填充层118(如果用的话)，其与另一种类型的晶体管的绝缘层114、导电层116和填充层118(如果用的话)相比包括不同的材料。例如，N型晶体管可以具有第一组材料，其包括绝缘层114、导电层116和填充层118(如果用的话)，同一衬底102上的P型晶体管可以具有第二组材料，其包括绝缘层114、导电层116和填充层118(如果用的话)。
出于例示和描述的目的，已经描述了本发明的实施例。并不是旨在穷举或者限制本发明到所公开的精确形式。该描述和所附的权利要求包括如下术语，例如左、右、顶部、底部、上方、下方、上部、下部、第一、第二等等，所述术语仅用于说明目的且不应被理解为限制。例如，定义相对垂直位置的术语指的是其中衬底或集成电路的器件侧(或有源表面)为衬底的“顶部”表面的情况；实际上衬底可以处于任何取向，使得在标准地球参考系中衬底的“顶部”侧可以低于“底部”侧，并且仍然落入术语“顶部”的含义中。除非特别说明，这里(包括权利要求)使用的术语“上”不表示第二层“上”的第一层位于第二层正上方且与第二层直接接触；在第一层和位于第一层之上的第二层之间可能存在第三层或其它结构。能够在多个位置和取向上来制造、使用或运送这里描述的器件或产品的实施例。相关领域的技术人员能够根据以上教导意识到各种可能的修改和变型。本领域的技术人员将意识到如图所示的各种部件的各种等效组合和替代。因此，本发明的范围并不限于上述详细说明，而应该是由所附权利要求来限定。

Claims (20)

1.一种器件，包括：
具有源极区和漏极区的晶体管；
与所述晶体管相邻的第一层间电介质层；
穿过所述第一层间电介质层到达所述源极区的沟槽；以及
所述沟槽中的导电源极接触，所述源极接触通过绝缘层与所述源极区分隔开。
2.根据权利要求1所述的器件，其中所述晶体管是包括鳍片的多栅极晶体管。
3.根据权利要求2所述的器件，其中所述绝缘层位于所述鳍片的顶表面和侧壁上。
4.根据权利要求1所述的器件，其中所述绝缘层的厚度大约为4nm或更小。
5.根据权利要求1所述的器件，还包括：
第二层间电介质层；
第一金属化层，所述第一金属化层与所述第二层间电介质层相邻并且具有多个导电过孔和多条导电线；
位于所述第二层间电介质层之上的第三层间电介质层；
第二金属化层，所述第二金属化层与所述第三层间电介质层相邻并且具有多个导电过孔和多条导电线；并且
其中所述第一金属化层的所述多个导电过孔和所述多条导电线中的至少一些以及所述第二金属化层的所述多个导电过孔和所述多条导电线中的至少一些导电连接到所述导电源极接触。
6.根据权利要求1所述的器件，其中所述导电源极接触的厚度小于100nm。
7.根据权利要求6所述的器件，还包括填充导体，所述填充导体位于所述导电源极接触上并且基本上填充所述沟槽。
8.根据权利要求1所述的器件，其中所述晶体管为P型晶体管，并且所述导电源极接触包括逸出功大于大约5ev的金属。
9.根据权利要求1所述的器件，其中所述晶体管为N型晶体管，并且所述导电源极接触包括逸出功低于大约3.2ev的金属。
10.根据权利要求1所述的器件，其中所述导电源极接触包括铝或镍。
11.一种制造接触的方法，包括：
在具有晶体管的衬底上沉积电介质层；
在所述电介质层中蚀刻延伸至源极区的第一开口；
在所述源极区上形成绝缘体；
在所述绝缘体上形成接触金属，所述绝缘体将所述接触金属与所述源极区分隔开；
基本上填充所述第一开口的全部，其中在填充所述第一开口之后，所述接触金属保持与所述源极区分隔开。
12.根据权利要求11所述的方法，其中所述绝缘体的厚度大约为4nm或更小。
13.根据权利要求12所述的方法，其中所述绝缘体的厚度大约为1nm或更小。
14.根据权利要求12所述的方法，其中形成所述绝缘体包括：形成所述绝缘层的共形层。
15.根据权利要求11所述的方法，其中所述晶体管是多栅极晶体管，其中所述绝缘体形成在所述多栅极晶体管的鳍片的顶部和侧壁上，以形成绝缘体顶部和绝缘体侧壁，并且其中所述接触金属形成在所述绝缘体顶部和所述绝缘体侧壁上。
16.一种器件，包括：
具有源极区和漏极区的晶体管；
源极接触，其中所述源极接触不直接与所述源极区相邻，并且其中第一绝缘层将所述源极接触与所述源极区分隔开；以及
漏极接触，其中所述漏极接触不直接与所述漏极区相邻，并且其中第二绝缘层将所述漏极接触与所述漏极区分隔开。
17.根据权利要求16所述的器件，其中所述晶体管是多栅极晶体管，所述源极区具有顶部和侧壁，所述漏极区具有顶部和侧壁。
18.根据权利要求16所述的器件，其中所述源极接触和所述漏极接触都不包括硅化物。
19.根据权利要求16所述的器件，其中所述第一绝缘层和所述第二绝缘层包括HfO2。
20.根据权利要求16所述的器件，其中所述晶体管具有包括III-V族材料的沟道区。
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KR20110084166A (ko) 2011-07-21
US20100155846A1 (en) 2010-06-24
EP2359394A2 (en) 2011-08-24

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