TW200949838A - Method for electrically trimming an NVM reference cell - Google Patents

Method for electrically trimming an NVM reference cell Download PDF

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Publication number
TW200949838A
TW200949838A TW098110897A TW98110897A TW200949838A TW 200949838 A TW200949838 A TW 200949838A TW 098110897 A TW098110897 A TW 098110897A TW 98110897 A TW98110897 A TW 98110897A TW 200949838 A TW200949838 A TW 200949838A
Authority
TW
Taiwan
Prior art keywords
voltage
reference cell
predetermined
cell
trimming
Prior art date
Application number
TW098110897A
Other languages
English (en)
Chinese (zh)
Inventor
Horacio P Gasquet
Richard K Eguchi
Peter J Kuhn
Ronald J Syzdek
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200949838A publication Critical patent/TW200949838A/zh

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14—Dummy cell management; Sense reference voltage generators

Landscapes

  • Read Only Memory (AREA)
TW098110897A 2008-05-30 2009-04-01 Method for electrically trimming an NVM reference cell TW200949838A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/130,186 US7782664B2 (en) 2008-05-30 2008-05-30 Method for electrically trimming an NVM reference cell

Publications (1)

Publication Number Publication Date
TW200949838A true TW200949838A (en) 2009-12-01

Family

ID=41379603

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098110897A TW200949838A (en) 2008-05-30 2009-04-01 Method for electrically trimming an NVM reference cell

Country Status (4)

Country Link
US (1) US7782664B2 (enExample)
JP (1) JP5406920B2 (enExample)
TW (1) TW200949838A (enExample)
WO (1) WO2009148688A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI466122B (zh) * 2012-05-18 2014-12-21 Elite Semiconductor Esmt 具有參考晶胞調整電路的半導體記憶體元件以及包含此元件的並列調整裝置
CN109785896A (zh) * 2018-12-17 2019-05-21 珠海博雅科技有限公司 一种上电同时读取修调位的电路、方法及装置
TWI894222B (zh) * 2020-03-06 2025-08-21 美商高通公司 提供寫入終止給一次性可編程記憶單元之系統及方法

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011187104A (ja) * 2010-03-05 2011-09-22 Renesas Electronics Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法
US8248855B2 (en) * 2010-03-10 2012-08-21 Infinite Memories Ltd. Method of handling reference cells in NVM arrays
US8427877B2 (en) * 2011-02-11 2013-04-23 Freescale Semiconductor, Inc. Digital method to obtain the I-V curves of NVM bitcells
US8363477B2 (en) * 2011-03-09 2013-01-29 Ememory Technology Inc. Method of setting trim codes for a flash memory and related device
US8687428B2 (en) 2011-10-31 2014-04-01 Freescale Semiconductor, Inc. Built-in self trim for non-volatile memory reference current
CN114664355B (zh) * 2022-03-16 2022-11-25 珠海博雅科技股份有限公司 非易失性存储器的参考电流产生模块和参考电流设置方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3454520B2 (ja) * 1990-11-30 2003-10-06 インテル・コーポレーション フラッシュ記憶装置の書込み状態を確認する回路及びその方法
US6078518A (en) 1998-02-25 2000-06-20 Micron Technology, Inc. Apparatus and method for reading state of multistate non-volatile memory cells
US6490203B1 (en) 2001-05-24 2002-12-03 Edn Silicon Devices, Inc. Sensing scheme of flash EEPROM
JP4118623B2 (ja) * 2002-07-23 2008-07-16 松下電器産業株式会社 不揮発性半導体記憶装置
US6839280B1 (en) 2003-06-27 2005-01-04 Freescale Semiconductor, Inc. Variable gate bias for a reference transistor in a non-volatile memory
JP2005222625A (ja) * 2004-02-06 2005-08-18 Sharp Corp 不揮発性半導体記憶装置
JP4554613B2 (ja) * 2004-07-30 2010-09-29 Ｓｐａｎｓｉｏｎ Ｊａｐａｎ株式会社 半導体装置および半導体装置にデータを書き込む方法
JP2006228277A (ja) * 2005-02-15 2006-08-31 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP4942990B2 (ja) * 2005-12-12 2012-05-30 パナソニック株式会社 半導体記憶装置
JP5067836B2 (ja) * 2005-12-19 2012-11-07 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置及びその動作方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI466122B (zh) * 2012-05-18 2014-12-21 Elite Semiconductor Esmt 具有參考晶胞調整電路的半導體記憶體元件以及包含此元件的並列調整裝置
CN109785896A (zh) * 2018-12-17 2019-05-21 珠海博雅科技有限公司 一种上电同时读取修调位的电路、方法及装置
CN109785896B (zh) * 2018-12-17 2020-12-15 珠海博雅科技有限公司 一种上电同时读取修调位的电路、方法及装置
TWI894222B (zh) * 2020-03-06 2025-08-21 美商高通公司 提供寫入終止給一次性可編程記憶單元之系統及方法

Also Published As

Publication number Publication date
JP2011522347A (ja) 2011-07-28
JP5406920B2 (ja) 2014-02-05
US20090296464A1 (en) 2009-12-03
WO2009148688A1 (en) 2009-12-10
US7782664B2 (en) 2010-08-24

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