TW200924196A - High-k/metal gate MOSFET with reduced parasitic capacitance - Google Patents

High-k/metal gate MOSFET with reduced parasitic capacitance Download PDF

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TW200924196A
TW200924196A TW097123385A TW97123385A TW200924196A TW 200924196 A TW200924196 A TW 200924196A TW 097123385 A TW097123385 A TW 097123385A TW 97123385 A TW97123385 A TW 97123385A TW 200924196 A TW200924196 A TW 200924196A
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gate
dielectric
metal
conductor
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TW097123385A
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Kang-Guo Cheng
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Ibm
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Description

200924196 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體結構及其製造方法。更具體 地，本發明係關於一種金屬氧化物半導體場效電晶體 (MOSFET)，其包含一高介電常數（k)的閘極介電質及一含 金屬的閘極導體，並且減少寄生電容。本發明亦提供製造 此種Μ Ο S F E T的方法。 【先前技術】 在半導體產業中，含有高k閘極介電質（介電常數大於 4.0且典型大於7.0的閘極介電質）及金屬閘極的閘極堆疊 是最有希望用於縮減互補金氧半導體（CMOS)尺寸規格的 選項之一。 製造高k/金屬閘極MOSFET之製程方案之一為閘極取 代法（replacement gate method)。在取代閘極製程中，可使 用犧牲閘極電極來製造MOSFET。在這類製程中，首先形 成一犧牲閘極電極，之後，利用含有高k閘極介電質及金 屬閘極的閘極堆疊來取代掉該犧牲閘極電極。由於包含高 k閘極介電質及金屬閘極的閘極堆疊是在高溫處理步驟 (例如源極/汲極活化退火）之後形成，取代閘極製程具有在 高 k閘極介電質及金屬閘極上造成最小損害的優點。此 外，廣範圍的金屬可選擇作為閘極導體。 習用閘極取代製程的其中一項嚴重缺點是導致高k閘 極介電質不僅存在金屬閘極下方，且亦出現在金屬閘極的 5 200924196 垂直側壁上。 第1圖為先前技術之MO SFET之示意圖，其包 極堆疊，該堆疊包含一高k閘極介電質及一金屬閘 使用如上文所提及的習用閘極取代製程製造。明確 第1圖顯示先前技術之MOSFET結構，其包含一内 源極/汲極擴散區1 004的半導體基板 1 000。半導 1 000亦包含多個溝渠隔離區1 006，其填滿溝渠介 料。在半導體基板之頂部，顯示具有形成「U」形 閘極介電質1 〇 〇 8，以及位於U形高k閘極介電質 部的金屬閘極1 0 1 0。介電質間隙壁1 〇 1 2位於U形 極介電質1 〇 〇 8的外部垂直側壁上。第1圖所示結構 一層間介電質材料 1 0 2 0，其内具有延伸至源極/汲 區1004上表面的接觸通孔1022。層間介電質材料 由介電質間隙壁1 0 1 2橫向地與閘極堆疊隔離開來。 金屬閘極出現在U形高k閘極介電質1 0 0 8之 壁上會導致不想要的高接觸-閘極導體寄生電 contect to gate conductor parasitic capacitance) ° 與高k閘極介電質相關的另一個問題是位於閘 (由第1圖所示之虛線圓形表示）處的高k閘極介電 因為於厚度及/或化學成分的差異而不盡理想。習用 再氧化製程無法用來強化位於閘極轉角處的高k閘 質，因為高k閘極介電質被金屬閘極及介電質間隙 住。位於閘極轉角處不理想的高k閘極介電質會導 電電流以及低可靠度。 含一閘 極，並 而言 ， 部具有 體基板 電質材 的南 k 1 008 内 南k閘 亦包含 極擴散 1 020 藉 垂直側 容（high 極轉角 質可能 的閘極 極介電 壁密封 致尚漏 6 200924196 鑑於上述問題，需要一種新穎且改良的高k/金屬閘極 MOSFET，其具有減小的接觸至閘極導體寄生電容，並且 選用性地，位於閘極轉角處具有改善的高k閘極介電質。 【發明内容】 本發明提供一種高k閘極介電質/金屬閘極MOSFET， 與使用習用的閘極取代製程所製造的高 k閘極介電質/金 屬閘極MOSFET相比，其具有減少的接觸至閘極導體寄生 電容（contact-to-gate conductor)。與使用習用閘極取代製 程所製造的習知高 k閘極介電質/金屬導體 MOSFET相 比，本發明可達成使接觸至閘極導體寄生電容減少約1 〇 % 或更多。 本發明亦提供一種高 k 閘極介電質/金屬閘極 MOSFET，其在閘極轉角處存在有一改善的高k閘極介電 質。 在某些實施例中，本發明進一步提供一種高k閘極介 電質/金屬閘極MOSFET，其包含一位於金屬閘極之垂直側 壁上的低k介電質間隙壁。所用的低k介電質間隙壁具有 小於4，較佳為小於3.5的介電常數。低k介電質間隙壁 的存在幫助進一步降低該接觸至閘極導體寄生電容。 本發明甚至進一步提供一種高 k閘極介電質/金屬閘 極Μ Ο S F E T，其中位於該高k閘極介電質/金屬閘極堆疊下 方的通道區具有約2微米（// m)或更小的長度。 概括地說，本發明提供一種半導體結構，其包含： 7 200924196 至少一個金屬氧化物半導體場效電晶體（MO SFET)，其 位於一半導體基板的一表面上，該至少一個MOSFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 電質及一含金屬閘極導體，該含金屬閘極導體具有閘極轉 角，其位於該含金屬閘極導體的基段，其中該含金屬閘極 導體具有垂直側壁，除了在該閘極轉角處外，該些垂直側 壁缺少該高k閘極介電質； 一閘極介電質，橫向鄰接存在於該閘極轉角處的該高 k閘極介電質；以及 一閘極間隙壁，橫向鄰接該含金屬閘極導體，且位於 該閘極介電質及存在於該閘極轉角處之該高k閘極介電質 兩者的上表面上。 本發明結構進一步包含一層間介電質材料，其包含多 個導電地填滿的接觸通孔，該些接觸通孔延伸至該半導體 基板之表面，該基板包含該至少一個 Μ Ο S F E T的源極/汲 極擴散區。 在本發明某些實施例中，本發明結構可進一步包含一 間隙壁襯料（spacer liner)，其存在於該閘極間隙壁和該層 間介電質材料、該含金屬閘極導體、以及該閘極介電質與 存在於該閘極轉角處之該高k閘極介電質兩者的上表面之 間。 在本發明的又另一實施例中，該閘極間隙壁為一低k 介電質材料（介電常數小於 4)。在進一步的實施例中，該 閘極間隙壁包含一存在於其内部中的空隙，該空隙降低該 8 200924196 閘極間隙壁的有效介電常數。 在本發明又進一步的實施例中，藉由引入氧及/或氮至 位於該閘極轉角處的材料中，來強化存在於該閘極轉角處 的該高k閘極介電質。 除了上文提及的一般半導體結構外，本發明亦提供一 種半導體結構，其包含： 至少一個金屬氧化物半導體場效電晶體（MOSFET)，其 位於一半導體基板的一表面上，該至少一個MOSFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 電質及一含金屬閘極導體，該含金屬閘極導體具有閘極轉 角，其位於該含金屬閘極導體的基段處，其中該含金屬閘 極導體具有多個垂直側壁，除了在該閘極轉角外，該些垂 直側面缺少該高k閘極介電質，並且與直接位於該含金屬 閘極導體下方的該高k閘極介電質相比，位於該閘極轉角 處之該高k閘極介電質具有增強的鍵結； 一閘極介電質，其橫向鄰接位於該閘極轉角處的該高 k閘極介電質；以及 一閘極間隙壁，其橫向鄰接該含金屬閘極導體，且位 於該閘極介電質及存在於該閘極轉角處之該高k閘極介電 質兩者的上表面上。 在另一實施例中，本發明提供一種半導體結構，包含： 至少一個金屬氧化物半導體場效電晶體（MOSFET)，其 位於一半導體基板的一表面上，該至少一個MOSFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 9 200924196 電質及一含金屬閘極導體，該含金屬閘極導體具有多個閘 極轉角，其位於該含金屬閘極導體的基段處，其中該含金 屬閘極導體具有多個垂直側壁，除了在該閘極轉角外，該 些垂直側壁缺少該高k閘極介電質； 一閘極介電質，橫向鄰接存在於該閘極轉角處之該高 k閘極介電質；以及 一低k閘極間隙壁，在其内部中包含空隙，並且該低 k閘極間隙壁橫向鄰接該含金屬閘極導體且位於該閘極介 電質及存在於該閘極轉角處之該高k閘極介電質兩者的上 表面上。 除了上文所述之半導體結構外，本發明亦提供製造這 類半導體結構的方法。概括地說，本發明之方法包含： 提供一結構，其包含位於一半導體基板上的一犧牲閘 極導體及一閘極介電質，該結構進一步包含一層間介電 質，該層間介電質位於該半導體基板上並且藉由一犧牲間 隙壁將之與該犧牲閘極分隔開來； 移除該犧牲閘極及一部分未被該犧牲間隙壁保護的該 閘極介電質，以形成一開口，該開口暴露出該半導體基板 的一表面； 在該開口内形成一 U形高k閘極介電質以及一含金屬 閘極導體； 移除該犧牲間隙壁以暴露出一部分橫向鄰接該含金屬 閘極導體側壁的該U形高k閘極介電質； 實質上從該閘極側壁移除橫向鄰接該含金屬閘極導體 10 200924196 側壁之該高k閘極介電質的所有暴露部分；以及 在一先前包含該犧牲間隙壁及一部分該U形高k閘極 介電質的區域中形成一閘極間隙壁。 【實施方式】 本發明提供一種具有至少減少接觸至閘極導體寄生電 容的高k閘極介電質/含金屬MOSFET及其製造方法；現 將參照下列敘述及伴隨本申請案之圖式而更詳細地敘述本 發明。須注意本申請案之圖式僅提供示範說明之目的，因 此，該些圖式並未按比例繪製。 在下列敘述中，提出諸多特定細節，例如特定結構、 成分、材料、尺寸、處理步驟及技術，以提供對本發明之 徹底了解。不過，在此技術領域中具有通常技術者將了解 本發明可在無須遵照這些特定細節的情況下實行。在其他 例子中，眾所周知的結構或處理步驟並未詳細敘述，以避 免與本發明混淆。 須了解到，當指稱例如一層、區或基板等元件位在另 一元件「之上」或「上方」時，其表示該元件可直接位於 另一元件上，或是存在有介於中間的元件。相對地，當指 稱一元件「直接位於另一元件之上」或「直接位於另一元 件上方」時，則表示沒有任何介於中間的元件存在。亦可 了解到當指稱一元件在另一元件「之下」或「下方」時， 其表示該元件可直接位於另一元件之下或直接位於另一元 件下方，或是可存在介於中間的元件。相對地，當指稱一 200924196 元件「直接位在另一元件之下」或「直接位在另一元件下 方」時，則表示沒有任何介於中間的元件存在。 亦觀察到雖然下列敘述及圖式顯示單一個高k閘極介 電質/含金屬導體MOSFET，但本發明並未受限於此。而 是，可利用本發明方法來形成複數個高k閘極介電質/含金 屬導體MOSFET。形成的複數個高k閘極介電質/含金屬導 體MOSFET可全都具有相同的傳導性（亦即，nMOSFETs或 pMOSFETs)。或者，該複數個高k閘極介電質/含金屬導體 MOSFET可包含第一組 MOSFET，其具有第一傳導性 (nMOSFET 或 pMOSFET);及第二組 MOSFET，其具有與 該第一傳導性型MOSFET相異的第二傳導性。 如上文所述，本發明提供一種高k閘極介電質/金屬閘 極MOSFET，與使用習用閘極取代製程所製造的高k閘極 介電質/金屬閘極MOSFET相比，其具有減少的接觸至閘 極導體寄生電容。 第2 A至2 C圖顯示本發明多種不同結構的實施例。在 第2A圖中，顯示本發明之第一實施例。第2A圖所示結構 包含至少一個金屬氧化物半導體場效電晶體（MOSFET) 100位於半導體基板12的一表面上。該至少一個M0SFET 1 0 0包含一閘極堆疊，該閘極堆疊由底部至頂部包含一高k 閘極介電質28及一含金屬閘極導體30。含金屬閘極導體 3 〇具有多個閘極轉角31位於該含金屬閘極導體的基段。 該含金屬閘極的基段在此處定義為閘極導體之垂直側壁與 閘極導體之底壁接觸的區域。此外’含金屬閘極導體3 0 12 200924196 具有多個垂直側壁 1 2 0 A及1 2 0 B，其除了在閘極轉角 處外，垂直側壁1 2 Ο A及1 2 Ο B缺少高k閘極介電質2 8 ;「 直側壁」一詞用於表示與共用底壁垂直的側壁，或該些 壁可能具有傾斜度（tapering)。第2A圖中亦顯示閘極介 質1 8，其橫向鄰接該位於閘極轉角3 1處的高k閘極介 質2 8，以及閘極間隙壁3 6，其橫向鄰接該含金屬閘極導 3 0。閘極間隙壁3 6位於閘極介電質1 8及存在於閘極轉 31處之高k閘極介電質28兩者的上表面上。 本發明之新穎結構進一步包含一層間介電質材 24，其包含多個導電地填滿的接觸通孔40，該些接觸通 40延伸至半導體基板12的表面，該基板包含該至少一 Μ 0 S F E T 1 0 0的源極/汲極擴散區14。 在本發明某些實施例中，間隙壁襯料3 4存在於閘極 隙壁3 6和層間介電質材料2 4、含金屬閘極導體3 0、以 閘極介電質1 8與存在於閘極轉角3 1處之高k閘極介電 28兩者的上表面之間。 參閱第2B圖，其顯示本發明之第二結構實施例， 包含如第 2A圖所示之相同的基本元件，只除了位於閘 轉角處之高k閘極介電質相較於直接位於含金屬閘極導 下方的高k閘極介電質而言具有改善的鍵結。在第2 B 中元件符號2 8 ’表示位在閘極轉角3 1處之具有改善鍵結 高k閘極介電質，而元件符號2 8表示直接位於含金屬閘 導體30下方的高k閘極介電質。 第2 C圖說明本發明之第三結構實施例。具體的說 3 1 垂 側 電 電 體 角 料 孔 個 間 及 質 其 極 體 圖 的 極 13 200924196 第2 C圖所示結構包含第2 B圖中之相同.元件，只除了在閘 極間隙壁3 6的内部中含有空隙3 8。空隙3 8的存在降低閘 極間隙壁3 6之有效介電常數。 現參照第3 A至3 Η圖，其說明可用於製造第2 A至2 C 圖所示之本發明結構的基本處理步驟。本發明之處理步驟 包括首先形成一習用MOSFET，其具有一假閘極（亦即，犧 牲閘極）、一閘極介電質、一犧牲間隙壁以及一層間介電 質。接著移除未受犧牲間隙壁所保護的犧牲閘極和閘極介 電質以形成一開口 ，該開口暴露出半導體基板的一表面。 在該開口内形成一 U形高k閘極介電質，然後形成一含金 屬閘極導體。接著移除犧牲間隙壁，以暴露出一部分的橫 向鄰接該含金屬閘極導體側壁的高k閘極介電質。接著將 橫向鄰接該含金屬閘極導體側壁之高k閘極介電質的暴露 部分從閘極側壁上移除，之後形成一間隙壁。 首先參照第3 A圖，其說明可用於本發明中的初始半 導體結構1 〇。如圖所示，初始半導體結構1 〇包含半導體 基板1 2，其已經過處理而包含至少一個隔離區1 6及源極/ 汲極區1 4。矽化物層（未顯示）可存在於源極/汲極區的表面 以降低電阻。半導體基板1 2進一步包含閘極介電質1 8， 其位於基板1 2的一表面上。閘極介電質1 8具有一中心部 分和外部邊緣部分，該中心部分上具有犧牲閘極2 0，而該 些外部邊緣部分鄰接該中心部分且其上各自具有一犧牲間 隙壁2 2。在第3 A圖中設有垂直虛線以顯示介於閘極介電 質之中心部分和閘極介電質之外部部分之間的虛構邊界。 14 200924196 第3 A圖所示結構亦包含一層間介電質材料2 4，其位 於半導體基板1 2不含閘極介電質1 8、犧牲閘極2 0及犧牲 間隙壁22的部分上。如所示，層間介電質24的上表面與 犧牲閘極20之上表面共平面。 第3 A圖所示之半導體基板1 2包含任何呈現半導體性 質之材料。呈現半導體性質之材料的範例包含，但不限於， 石夕、梦鍺、碳化發、碳化梦鍺、錄、蘇、坤化嫁、神化銦、 磷化銦及所有其他第III/V族或第II/VI族之化合物半導 體。半導體基板12亦可包含有機半導體或成層半導體，例 如，矽/矽鍺、絕緣層上覆矽或絕緣層上覆矽鍺。在本發明 之某些實施例中，較佳半導體基板1 2包含一含矽半導體材 料，亦即，包含矽的半導體材料。除了上述的半導體基板 類型外，用於本發明之半導體基板1 2亦可包含一混合定向 (HOT)的半導體基板，其中該HOT基板具有不同晶格位向 的表面區。 半導體基板12可經過摻雜、未經摻雜，或在其内包含 摻雜區及未摻雜區。半導體基板1 2可經過應變、未應變、 其内包含應變區及未應變區，或是包含拉伸應變區及壓縮 應變區。 第3A圖所示之各個隔離區16可包含一溝渠介電質材 料，例如氧化物，且可選用性地，包含一襯料（liner)，例 如，氮化石夕或氮氧化叾夕，其可存在於溝渠之側壁上。在形 成第3 A圖所示的其他元件之前，使用習知溝渠隔離製程 於半導體基板1 2中形成溝渠隔離區1 6，該溝渠隔離製程 15 200924196 包含首先在半導體基板12中蝕刻i少一溝渠，可選用性地 將一溝渠襯料填入該至少一個溝渠，之後以一溝渠介電質 材料填滿該溝渠。在溝渠填滿後’使用習知平坦化製程， 例如，化學機械拋光及/或研磨’來提供平坦的結構。在某 些實施例中，可在以溝渠介電質材料填滿該溝渠後執行緻 密化製程（densification)。 須注意，通常在有一墊層（Pad layer，未顯示）存在下 執行溝渠隔離區的形成製程，五於半導體基板12中形成至 少一個溝渠隔離區1 6後從該結構移除該墊層。該墊層可包 含氮化矽，並且可選用性地包含一下層的氧化矽。任何可 選擇性移除該墊層的習知剝除製程（stripping process)可 用來從結構移除該墊層。 或者，可藉由其他眾所周知的方法來形成各個隔離區 16，例如，LOCOS(矽的局部氧化法）。 在本發明此處，可使用兩種不同處理製程的其中一種 來製造第3A圖所示之結構。在第一處理製程中，使用— 習知的CMOS處理流程，閘極介電質1 8的毯覆層形成在 包含在溝渠隔離區16頂部在内的半導體基板12之整個表 面上。閘極介電質18之毯覆層可藉由習用的沈積製程來形 成，包括，例如化學氣相沈積（CVD)、低壓化學氣相沈積 (LPCVD)、電漿增強化學氣相沈積（PECVD)、蒸鍍法、化 學溶液沈積及原子層沈積（ALD)。或者，熱氧化法、氮化 法或氮氧化法可用於形成閘極介電質1 8之毯覆層。閘極介 電質1 8之毯覆層的厚度較隨後欲形成之高k閘極介電質的 16 200924196 厚度更厚。典型地，閘極介電質1 8之厚度從約2奈米至約 20奈米（nm)，更典型者厚度為約3奈米至約1 0奈米。閘 極介電質18典型為半導體材料之氧化物，更典型為矽之氧 化物。 在形成閘極介電質1 8之毯覆層後，犧牲閘極材料（例 如，多晶矽或矽鍺）之毯覆層利用習用的沈積製程來形成， 包含例如C V D、L P C V D、P E C V D、蒸鍍、化學溶液沈積及 物理氣相沈積（PVD)。犧牲閘極材料之毯覆層（其形成犧牲 閘極20)在沈積後具有約20奈米至約200奈米的厚度，更 典型為約5 0至約1 0 0奈米的厚度。 接著使用包含微影及蝕刻的圖案化製程來圖案化該犧 牲閘極材料之毯覆層，使其成為第3 A圖所示的犧牲閘極 2 0。微影步驟包含施加一光阻至犧牲閘極材料毯覆層的表 面、將光阻暴露至一所欲的輻射圖案，接著顯影該已曝光 的光阻。蚀刻步驟包含乾蚀刻或濕14刻。較佳利用一乾# 刻製程，例如，反應性離子蝕刻、離子束蝕刻及電漿蝕刻。 蝕刻製程止於閘極介電質1 8的一表面上。在蝕刻後，利用 習知去光阻製程（例如，灰化）將該已暴光及顯影的光阻從 該結構上移除。 此時，源極/汲極區1 4形成至半導體基板1 2中。各源 極/汲極區1 4可進一步包含一源極/汲極延伸區，其部分與 犧牲閘極2 0重疊。形成源極/汲極和源極/汲極延伸可包含 利用在此技術領域中習知的離子佈植製程、間隙壁形成及 摻雜物活化退火。 17 200924196 接著藉由沈積和钱刻而在犧牲閘極 20之垂直側壁上 以及閘極介電質1 8之毯覆層表面上形成犧牲間隙壁2 2。 犧牲間隙壁2 2係由含氮化物之材料組成’例如’氮化矽或 氮氧化矽。可在源極和汲極區形成之前或之後形成犧牲間 隙壁2 2。如果形成源極/汲極延伸’可在源極/汲極延伸形 成之前或之後形成犧牲間隙壁22 ° 接下來，利用犧牲間隙壁2 2和犧牲閘極2 0作為蝕刻 遮罩來蝕刻閘極介電質1 8之毯覆層。 形成層間介電質材料2 4之毯覆層，以覆蓋住該結構的 所有暴露表面。層間介電質材料2 4係利用任何習用的沈積 製程來形成，包含例如’化學氣相沈積（CVD)、低壓化學 氣相沈積（LPCVD)、電漿增強化學氣相沈積（PECVD)、次 大氣壓化學氣相沈積（SACVD)、蒸鍍、化學溶液沈積及旋 轉塗佈。層間介電質材料2 4包含任何習用的介電質材料， 例如，二氧化矽、矽酸鹽玻璃、倍半矽氧烷 (silsesquioxane)、包含石夕、碳、氧及氫原子的有機梦酸鹽， 以及熱固性聚亞芳香 ϋ (thermosetting polyarylene ether)。「聚亞芳基（p〇lyarylene)」一詞用於表示藉由鍵結、 稠環或惰性連接基團，例如氧、硫、砜、亞颯、羰基及其 類似物等連接在一起的芳香基部分。 接著使用於平坦化製程，例如化學機械拋光及/或研 磨’來形成一共平面結構，例如第3 A圖所示。 在另一處理製程中，係藉由首先處理基板1 2，使其包 含隔離區1 6而形成第3 A圖所示之初始結構。接下來，形 18 200924196 成該層間介電質材料2 4，且使用微影及 個位於介電質材料中的開口，該開口暴 的一表面。源極/汲極區1 4可在此時形 底部形成閘極介電質1 8。接下來，犧相 已圖案化之層間介電質材料24的暴露 牲閘極2 0。接著典型使用一平坦化製卷 示之共平面結構。本發明之此實施例典 通道，其長度約為2微米（y m)或更短’ 在提供第3 A圖所示之初始結構1 0 及直接位於犧牲閘極2 0下方之犧牲閘本 構上移除。移除犧牲閘極2 0及犧牲閘木 電質18提供開口 26，其暴露出半導體 在執行本發明之此步驟後所形成的結果 於第3 B圖。依犧牲閘極2 0及閘極介電 不同的適當製程可用於移除該些材料。 氨系化學劑之钮刻劑的濕#刻製程，或 蝕刻劑進行電漿蝕刻的乾蝕刻製程，可 之犧牲閘極2 0。使用氫氟酸蝕刻劑的濕 除含氧化矽的閘極介電質1 8。 接下來，在開口 26内部形成U形高 之後在U形高k閘極介電質2 8之暴露 導體3 0，從而提供，例如第3 C圖所示 閘極介電質2 8包含任何介電常數大於 的介電質材料。 钮刻來定義至少一 露出半導體基板12 成，之後則在開口 .間隙壁2 2形成在 ij壁上，接著形成犧 來提供第3 A圖所 型用於形成一裝置 後，將犧牲閘極2 0 έ介電質1 8從該結 i 20下方之閘極介 基板12的一表面。 結構，係例如顯示 質1 8之材料而定， 舉例來說，使用含 例如使用含氟化硫 用於移除含多晶石夕 蝕刻製程可用於移 k閘極介電質2 8， 表面上形成含金屬 之結構。U形向k 4.0，典型大於7.0 19 200924196 這類高k閘極介電質材料之範例包含，但不受限於， 二氧化鈦、三氧化二鋁、二氡化錯、二氧化給、五氧化_ 组、三氧化二鋼、混合的金屬氧化物’例如約鈦镇型氧化 物（perovskite-type oxides)及其組合物與多層。前述金屬氧 化物的矽酸鹽及氮化物亦可做為高k閘極介電質材料。可 選擇地，一第一界面層（未顯示）可形成在U形高k閘極介 電質2 8和基板1 2之間的界面處，以改善裝置特性，例如， 減少界面陷解（interface traps)。第一界面層，如果存在的 話’可包含氧化矽、氮化矽或氮氧化物，其可藉由熱氧化、 化學氧化、熱氮化及化學氮化來形成。此外，可在形成含 金屬閘極導體30之前，在U形高k介電質28之頂部或内 部沈積一第二界面層（未顯示）。第二界面層（如果存在的話） 可藉由調整功函數（work function)及/或穩定平帶電麼及臨 界電壓（threshold voltage)幫助裝置特性最佳化。第二界面 層（如果存在的話）可包含一含稀土元素層，其包括三氧化 二鑭、氮化鑭或任何其他適當的材料。u形高k閘極介t 質28可藉由習用的沈積製程來形成’包含，但不受限於， 原子層沈積（ALD)、化學氣相沈積（CVD)、低壓化學氣相 積（LPCVD)、電漿增強化學氣相沈積（PECVD)、快速熱化 學氣相沈積（RTCVD)、限制反應處理化學氣相、士 九積 (LRPCVD)、超高真空化學氣相沈積（UHVCVD)、有機 化學氣相沈積（MOCVD)、分子束磊晶（MBE)、物理氣 、不目洗 積、離子束沈積、電子束沈積及雷射輔助沈積。 U形高k閘極介電質2 8的厚度小於該閘極介電科 ^ 1 8 20 28 200924196 之剩餘外部部分的厚度。典型地，U形高k閘極介電質 具有約1奈米至約2 0奈米之厚度，更典型為約2奈米至 1 0奈米之厚度。 含金屬閘極導體3 0係利用習用的沈積製程來形成， 如，原子層沈積（ALD)、化學氣相沈積（CVD)、有機金屬 學氣相沈積（MOCVD)、分子束磊晶（MBE)、物理氣相沈相 藏射、電鑛、蒸鑛、離子束沈積、電子束沈積、雷射輔 沈積及化學溶液沈積。含金屬閘極導體3 0包含一導電 屬，例如，但不受限於，铭、鎢、銅、翻、銀、金、釕 銥、錢及銖、導電金屬之合金，例如铭銅合金、導電金 之矽化物，例如矽化鎢和矽化鉑、導電金屬之氮化物， 如氮化铭，以及其上述之組合與多層。習用的平坦化製禾 例如化學機械研磨（C Μ P )，可用於移除任何沈積在層間 電質24與犧牲間隙壁2 2頂部的含金屬閘極導體3 0。習 的蝕刻製程，例如濕蝕刻或乾蝕刻，可用於移除任何沈 在層間介電質2 4與犧牲間隙壁2 2頂部的U形高k閘極 電質。 接下來，如第3 D圖所示，將犧牲間隙壁2 2從結構 移除，暴露出閘極介電質1 8剩餘的外部部分、U形高 閘極介電質 2 8之外部側壁以及層間介電質材料 2 4之 壁。犧牲間隙壁22係利用一蝕刻製程移除，該製程會相 於層間介電質材料24及剩餘的閘極介電質1 8而選擇性 除犧牲間隙壁2 2之材料。此類可用蝕刻製程的其一範例 括使用含有碟酸或氫氟酸和乙二醇（H F / E G)混合物之餘 約 例 化 、 助 金 屬 例 介 用 積 介 上 k 側 對 移 包 刻 21 200924196 劑的濕蝕刻製程，以移除由氮化矽形成之犧牲間隙壁2 2。 或者，當犧牲間隙壁2 2包含氮化矽時，其可藉由例如化學 下游蝕刻（CDE)之乾蝕刻製程來移除。 第3E圖顯示在從實質上所有含金屬閘極導體30之垂 直側壁移除U形高k閘極介電質2 8後所形成的結構。較 厚的閘極介電質18可確保在不會使含金屬閘極導體30下 方之高k閘極介電質材料產生底切的情況下，從含金屬閘 極側壁上實質完全移除高k閘極材料。由含金屬閘極導體 3 0的垂直側壁實質上移除所有高k閘極介電質材料可減少 該接觸至閘極導體電容。 須注意到，某部分的U形高k閘極介電質28仍餘留 在含金屬的閘極導體3 0之垂直側壁上，而覆蓋住位在含金 屬閘極導體3 0之基段處的閘極轉角。在第3 E圖中，以元 件符號3 1標明閘極轉角。在本發明中，餘留在閘極轉角 3 1處之高k閘極材料的高度小於剩餘閘極介電質1 8的高 度。 從實質所有含金屬閘極導體3 0之垂直側壁上移除U 形高k閘極介電質2 8係利用一蝕刻製程來執行，相對於其 他暴露於蝕刻製程中的材料而言，該製程選擇移除高k閘 極介電質材料。此類蝕刻製程的其中一範例包括硼一鹵素 電漿，其包含硼一鹵素化合物（例如，三氯化硼）及氮氣。 或者，可在移除犧牲間隙壁2 2時，同時從含金屬閘極導體 3 0之垂直側壁移除高k閘極介電質2 8。 在本發明之某些實施例中，可強化未受含金屬閘極導 22 200924196 體3 0保護且鄰接閘極轉角3 1之U形高k閘極介電質2 8 的剩餘部份，以減少可能存在於閘極轉角3 1處的漏電和可 靠度問題。當使用高 k閘極介電質材料時，由於應力及/ 或薄膜沈積的緣故，可能造成在閘極轉角處增加漏電流且 減少可靠度。剩餘U形高k閘極介電質2 8之強化區在第 3F圖中標明為28,。 在本發明中，強化作用係利用低能量（約20 KeV或更 小）氧離子及/或氮離子佈植製程來達成。所用的氧及/或氮 離子之劑量典型介於約1 E 1 2至約1 E 1 5原子/平方公分之範 圍内，而更典型的劑量範圍介於約1 E 1 3至約1 E 1 4原子/ 平方公分内。或者，可使用低溫氧化、氮化或氮氧化製程（溫 度約9 5 0 °C或更小），來產生上述位在閘極轉角3 1處之高k 閘極材料的強化作用。執行其中一種上述技術的淨效應為 改善高k閘極介電質材料中的化學鍵結。 此處提及，在本發明中，直接位於閘極導體下方之高 k閘極介電質2 8具有高度h3，該高度h3小於位於閘極轉 角處之剩餘高k閘極介電質的高度h2，且位於閘極轉角處 之剩餘高k閘極介電質的高度h2實質上等於或小於剩餘閘 極介電質18的高度h!。換言之，閘極介電質具有第一高 度，存在於閘極轉角處之高k閘極介電質具有第二高度， 且直接位於該含金屬閘極導體下方之高k閘極介電質具有 第三高度，其中該第一高度實質上等於或大於該第二高 度，而該第二高度大於該第三高度。 其餘圖式顯示強化後的高k閘極介電質區2 8 ’位在閘 23 200924196 極轉角3 1處。雖然顯示於其餘圖式中，但若省略該選用性 的強化步驟時，仍可使用後續的處理步驟。 第3 G圖顯示，當移除犧牲間隙壁2 2以及移除實質所 有位於含金屬閘極導體3 0之側壁上的高k閘極材料之後， 於所產生的空間内形成可選用性間隙壁襯料 3 4及閘極間 隙壁3 6之後所形成的結果結構。該選用性間隙壁襯料3 4 包含一第一介電質材料，其與用來形成閘極間隙壁3 6的第 二介電質材料不相同。典型地，間隙壁襯料3 4係由氮化矽 組成，而閘極間隙壁3 6係由二氧化矽組成。在某些實施例 中，閘極間隙壁3 6為一低k(介電常數小於4.0)介電質材 料，例如，包含至少石夕、碳、氧及氫原子的有機石夕酸鹽， 而間隙壁襯料3 4包含氧化矽。 選用性的間隙壁襯料3 4在沈積後具有約1奈米至約 1 0奈米之厚度，而更典型為約2至5奈米。選用性的間隙 壁襯料34可由沈積製程形成，例如，原子層沈積（ALD)、 化學氣相沈積（CVD)、低壓化學氣相沈積（LPCVD)、電漿 增強化學氣相沈積（PECVD)、次大氣壓化學氣相沈積 (SACVD)、快速熱化學氣相沈積（RTCVD)、高溫氧化物沈 積（HTO)、低溫氧化物沈積（LTO)、限制反應處理 CVD(LRPCVD)、旋轉塗佈、化學溶液沈積或任何其他適當 的製程。閘極間隙壁3 6係由任何適當的沈積製程形成，例 如，CVD及旋轉塗佈。此處指出閘極間隙壁3 6的一底部 表面係位於剩餘閘極介電質1 8及存在於閘極轉角3 1處之 高k閘極介電質兩者的頂部上方或直接位於其上。在一習 24 200924196 知結構中，閘極間隙壁係直接位於半導體基板的一 4 在本發明某些與欲形成閘極間隙壁 3 6之空間 形狀以及所使用之沈積製程相依的實施例中，空隙 第2 C圖）可存在於閘極間隙壁3 6之内部部分中。空 在具有進一步減少本發明中所用之閘極間隙壁 3 6 介電常數的效果。 第3 Η圖顯示出於層間介電質材料2 4中形成導 之接觸通孔4 0以後的結構，其中該些接觸通孔4 0 含有源極/汲極擴散區1 4之半導體基板1 2的表面。 微影、蝕刻並且以一導電材料填滿所形成的接觸通 成該些導電填滿的接觸通孔4 0。可選用性地，可在 材料填滿該些通孔之前，先在該些接觸通孔的暴露 形成一擴散阻障層，例如氮化鈦或氮化钽。用於填 開口的導電材料包含任何導電材料，包括任一種可 成含金屬閘極導體3 0的導電材料。 在本發明之某些實施例中，可在從含金屬閘極 之垂直側壁上移除高k閘極介電質2 8和犧牲間隙兵: 前，先在層間介電質材料2 4中形成多個導電填滿的 孔40。 雖然已參照較佳實施例具體展示及敘述本發明 悉此技術者將了解可在不偏離本發明精神及範圍的 做出形式及細節上的前述及其他變化。因而，其意 明並不僅限於所述及顯示的確切形式與細節，而是 附申請專利範圍之範圍内。 I面上。 的幾何 38(見 隙的存 之有效 電填滿 延伸至 可利用 孔來形 以導電 側壁上 滿接觸 用於形 導體30 I 22之 接觸通 ，但熟 情況下 指本發 落在後 25 200924196 【圖式簡單說明】 第1圖為一剖面視角的示意圖，以說明利用習用閘極 取代製程所製造的習知高 k閘極介電質/金屬導體 MOSFET。 第2A、2B及2C圖為示意剖面圖，以說明根據本發明 實施例之高k閘極介電質/金屬導體MOSFET。 第3A至3H圖為示意剖面圖，說明可用來製造第2A 至2 C圖所示結構的基本處理步驟。 【主 要 元 件 符 號 說 明 1 hi 南 度 h2 南度 h3 1¾ 度 10 初始結 構 12 半 導 體 基 板 14 源極/汲 .極 L區 16 隔 離 18 閘極介 電 質 20 犧 牲 閘 極 22 犧牲間 隙 壁 24 層 間 介 電 質 材 料 26 開口 28 南 k 閘 極 介 電 質 28， 具 有 改 善 的 鍵 結之T% k閘 極介電質 30 含 金 屬 的 閘 極 導 體 3 1 閘極轉 角 34 間 隙 壁 襯 料 36 閘極間 隙 壁 38 空 隙 40 接觸通 孔 100 金屬氧化物半導體場效電！ 晶體（MOSFET) 1 02A 垂 直 側 壁 102B 垂直 側 壁 26 200924196 1000 半導體基板 1004 源極/汲極擴散區 1006 溝渠 隔離 區 1008 高k閘極介電質 10 10 金屬 閘極 10 12 介電質間隙壁 1020 層間 介電 質材料 1022 接觸通孔 27

Claims (1)

  1. 200924196 十、申請專利範圍： 1. 一種半導體結構，包含： 至少一個金屬氧化物半導體場效電晶體（MOSFET)，其 位於一半導體基板的一表面上，該至少一個MOSFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 電質及一含金屬閘極導體，該含金屬閘極導體具有多個閘 極轉角，該些閘極轉角位於該含金屬閘極導體的一基段 處，其中該含金屬閘極導體具有多個垂直側壁，除了在該 閘極轉角外，該些垂直側壁缺少該高k閘極介電質； 一閘極介電質，其橫向鄰接存在於該閘極轉角處之該 高k閘極介電質；以及 一閘極間隙壁，其橫向鄰接該含金屬閘極導體，且位 於該閘極介電質及存在於該閘極轉角處之該高k閘極介電 質兩者的上表面上。 2. 如申請專利範圍第1項所述之半導體結構，更包含一層 間介電質材料，其具有多個導電填滿的接觸通孔，該些 接觸通孔延伸至該半導體基板的表面，該基板包含該至 少一個Μ Ο S F E T的源極區與汲極區。 3. 如申請專利範圍第2項所述之半導體結構，更包含一間 隙壁襯料，其存在於該閘極間隙壁和該層間介電質材 料、該含金屬閘極導體、以及該閘極介電質與存在於該 閘極轉角處之該高k閘極介電質兩者的上表面之間。 28 200924196 4 _如申請專利範圍第1項所述之半導體結構 > 其中該閘極 間隙壁為一低k介電質材料，其具有小於4之介電常數。 5 .如申請專利範圍第1項所述之半導體結構，其中該閘極 間隙壁包含一空隙，其存在於該閘極間隙壁之内部，該 空隙降低該閘極間隙壁之有效介電常數。 6 .如申請專利範圍第1項所述之半導體結構，其中該閘極 介電質具有一第一高度，存在於該閘極轉角處之該高k 閘極介電質具有一第二高度，且直接位於該含金屬閘極 導體下方之該高k閘極介電質具有一第三高度，其中該 第一高度實質上等於或大於該第二高度，而該第二高度 大於該第三高度。 7. 如申請專利範圍第1項所述之半導體結構，其中與直接 位於該含金屬閘極導體下方之該高 k閘極介電質相 比，位於該閘極轉角處之該高k閘極介電質具有增強的 鍵結。 8. 如申請專利範圍第1項所述之半導體結構，其中該高k 閘極介電質包含下列其中一者：二氧化鈦、三氧化二 鋁、二氧化锆、二氧化铪、五氧化二钽、三氧化二鑭、 鈣鈦礦型氧化物、及其矽酸鹽或氮化物。 29 200924196 9.如申請專利範圍第1項所述之半導體結構，其中該含金 屬閘極導體為導電金屬、導電金屬合金、導電金屬矽化 物、及導電金屬氮化物其中之一。 1 〇. —種半導體結構，包含： 至少一個金屬氧化物半導體場效電晶體（MOSFET)，其 位於一半導體基板的一表面上，該至少一個MOSFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 電質及一含金屬閘極導體，該含金屬閘極導體具有多個閘 極轉角，該些閘極轉角位於該含金屬閘極導體的一基段， 其中該含金屬閘極導體具有多個垂直側壁，除了在該閘極 轉角處外，該些垂直側壁缺少該高k閘極介電質，與直接 位於該含金屬閘極導體下方的該高k閘極介電質相比，位 於該閘極轉角處之該高k閘極介電質具有增強的鍵結； 一閘極介電質，其橫向鄰接存在於該閘極轉角處之該 高k閘極介電質；及 一閘極間隙壁，其橫向鄰接該含金屬閘極導體，且位 於該閘極介電質及存在於該閘極轉角處之該高k閘極介電 質兩者的上表面上。 1 1 .如申請專利範圍第1 0項所述之半導體結構，更包含一 層間介電質材料，其具有導電填滿的接觸通孔，該接觸 通孔延伸至該半導體基板的表面，該基板包含該至少一 30 200924196 個Μ O S F E T的源極區與没極區。 1 2 .如申請專利範圍第1 1項所述之半導體結構， 間隙壁襯料，該間隙壁襯料存在於該閘極間隙 間介電質材料、該含金屬閘極導體、以及該閘 與位於該閘極轉角處之該高 k閘極介電質兩 面之間。 1 3 .如申請專利範圍第1 0項所述之半導體結構， 極間隙壁為一低k介電質材料，其具有小於4 數。 1 4.如申請專利範圍第1 0項所述之半導體結構， 極間隙壁包含一空隙，其存在於該閘極間隙壁 該空隙降低該閘極間隙壁的有效介電常數。 1 5 .如申請專利範圍第1 0項所述之半導體結構， 極介電質具有一第一高度，存在於該閘極轉角 k閘極介電質具有一第二高度，以及直接位於 閘極導體下方的該高k閘極介電質具有一第三 中該第一高度實質上等於或大於該第二高度， 高度大於該第三高度。 1 6 .如申請專利範圍第1 0項所述之半導體結構， 更包含一 壁和該層 極介電質 者的上表 其中該閘 之介電常 其中該閘 的内部， 其中該閘 處的該向 該含金屬 .高度，其 而該第二 其中該南 31 200924196 k閘極介電質包含下列其中一者：二氧化鈦、三氧化二 鋁、二氧化锆、二氧化給、五氧化二鈕、三氧化二鑭、 飼鈦礦型氧化物（perovsjite type oxide)、及其石夕酸鹽 (silicate)或氮化物。 1 7.如申請專利範圍第1 0項所述之半導體結構，其中該含 金屬閘極導體為導電金屬、導電金屬合金、導電金屬矽 化物、及導電金屬氮化物其中之一。 18. —種半導體結構，包含： 至少一個金屬氧化物半導體場效電晶體（M0SFET)，其 位於一半導體基板的一表面上，該至少一個M0SFET包含 一閘極堆疊，該閘極堆疊由底部至頂部包含一高k閘極介 電質及一含金屬閘極導體，該含金屬閘極導體具有多個閘 極轉角，該些閘極轉角位於該含金屬閘極導體的基段，其 中該含金屬閘極導體具有多個垂直側壁，除了在該閘極轉 角外，該些垂直側壁缺少該高k閘極介電質； 一閘極介電質，其橫向鄰接存在於該閘極轉角處的該 高k閘極介電質；以及 一低k閘極間隙壁，在其内部包含多個空隙，並且該 低k閘極間隙壁橫向鄰接該含金屬閘極導體且位於該閘極 介電質及存在於該閘極轉角處之該高k閘極介電質兩者的 上表面上。 32 200924196 1 9 .如申請專利範圍第1 8項所述之半導體結構，更包含 層間介電質材料，其具有導電性填滿的接觸通孔，該 接觸通孔延伸至該半導體基板的表面，該基板包含該 少一個Μ Ο S F E T的源極區與没極區。 2 〇.如申請專利範圍第1 9項所述之半導體結構，更包含 間隙壁襯料，其位於該閘極間隙壁和該層間介電質 料、和該含金屬閘極導體、以及和該閘極介電質與存 於該閘極轉角處之該高 k閘極介電質兩者的上表面 間。 2 1 .如申請專利範圍第1 8項所述之半導體結構，其中該 極介電質具有一第一高度，存在於該閘極轉角處之該 k閘極介電質具有一第二高度，且直接位於該含金屬 極導體下方的該高k閘極介電質具有一第三高度，其 該第一高度實質等於或大於該第二高度，而該第二高 大於該第三高度。 2 2.如申請專利範圍第1 8項所述之半導體結構，其中該 k閘極介電質包含下列其中一者：二氧化鈦、三氧化 鋁、二氧化锆、二氧化铪、五氧化二鈕、三氧化二销 妈鈦礦型氧化物（perovskite type oxide)、及其石夕酸鹽 氮化物。 些 至 材 在 之 閘 閘 中 度 或 33 200924196 2 3 .如申請專利範圍第1 8項所述之半導體結構，其中該含 金屬閘極導體為導電金屬、導電金屬合金、導電金屬矽 化物及導電金屬氮化物的其中之一，。 24.如申請專利範圍第1 8項所述之半導體結構，其中與直 接位於該含金屬閘極導體下方的該高 k閘極介電質相 比，位於該閘極轉角處的該高k閘極介電質具有增強的 鍵結。 2 5 . —種形成一半導體結構的方法，其包含： 提供一結構，該結構包含位於一半導體基板上的一犧 牲閘極及一閘極介電質，該結構更包含一層間介電質，該 層間介電質位於該半導體基板上並且藉由一犧牲間隙壁將 之與該犧牲閘極分隔開； 移除該犧牲閘極以及一部分未被該犧牲間隙壁保護的 該閘極介電質，以形成一開口 ，該開口暴露出該半導體基 板的一表面； 在該開口内形成一 U形高k閘極介電質以及一含金屬 閘極導體； 移除該犧牲間隙壁以暴露出一部分橫向鄰接該含金屬 閘極導體側壁的該U形高k閘極介電質； 從該閘極側壁上移除與該含金屬閘極導體側壁橫向鄰 接之該高k閘極介電質的所有暴露部分；以及 在一先前包含該犧牲間隙壁及一部分該U形高k閘極 34 200924196 介電質的區域中形成一閘極間隙壁。 2 6 .如申請專利範圍第2 5項所述之方法，更包含形 間介電質材料，其具有導電性填滿之接觸通孔， 通孔延伸至該半導體基板的表面，該半導體基板 至少一個Μ Ο S F E T的源極區與没極區。 2 7 .如申請專利範圍第2 6項所述之方法，更包含形 隙壁襯料，位在於該閘極間隙壁以及該層間介 料、該含金屬閘極導體、和該閘極介電質及位於 轉角處之該高k閘極介電質兩者的上表面之間。 2 8 .如申請專利範圍第2 6項所述之方法，更包括強 分位於該含金屬閘極導體之閘極轉角處的該高 介電質，使得與直接位於該含金屬閘極導體下方 k閘極介電質相比，增加位於該含金屬閘極導體 轉角處之該高k閘極介電質中的鍵結。 2 9 ·如申請專利範圍第2 8項所述之方法，其中該強 係藉由離子佈植氧離子及氮離子其中一者或藉 製程來達成。 3 0 .如申請專利範圍第2 6項所述之方法，其中形成 間隙壁包含在該閘極間隙壁的一内部區域内形 成一層 該接觸 包含該 成一間 電質材 該閘極 化一部 k閘極 的該向 之閘極 化步驟 由一熱 該閘極 成一空 35 200924196
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