CN101681841B - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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CN101681841B
CN101681841B CN2008800160376A CN200880016037A CN101681841B CN 101681841 B CN101681841 B CN 101681841B CN 2008800160376 A CN2008800160376 A CN 2008800160376A CN 200880016037 A CN200880016037 A CN 200880016037A CN 101681841 B CN101681841 B CN 101681841B
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程慷果
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Tessera Inc
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Abstract

本发明提供一种高k栅极介质/金属栅极MOSFET，其具有减少的寄生电容。所述新颖结构包括至少一个金属氧化物半导体场效应晶体管(MOSFET)100，其位于半导体衬底12的表面上。所述至少一个MOSFET 100包括栅极叠层，其从底部至顶部包括高k栅极介质28及含金属的栅极导体30。所述含金属的栅极导体30具有栅极拐角31，其位于含金属的栅极导体的基段处。此外，除了在栅极拐角31处之外，含金属的栅极导体30的垂直侧壁102A及102B不具有高k栅极介质28。栅极介质18横向邻接位于栅极拐角31处的高k栅极介质28，而栅极间隔物36横向邻接含金属的栅极导体30。栅极间隔物36位于栅极介质18和栅极拐角31处的高k栅极介质两者的上表面上。

Description

一种半导体结构及其制造方法
技术领域
本发明涉及一种半导体结构及其制造方法。更具体地，本发明涉及一种金属氧化物半导体场效应晶体管(MOSFET)，其包含高介电常数(k)的栅极介质及具有减少的寄生电容的含金属的栅极导体。本发明还提供制造这种MOSFET的方法。
背景技术
在半导体产业中，含有高k栅极介质(介电常数大于4.0且典型大于7.0的栅极介质)及金属栅极的栅极叠层是最有希望用于缩放互补金属氧化物半导体(CMOS)的选项之一。
制造高k/金属栅极MOSFET的工艺方案之一为取代栅极法(replacement gate method)。在取代栅极工艺中，可使用牺牲栅极电极来制造MOSFET。在这类工艺中，首先形成牺牲栅极电极，随后，利用含有高k栅极介质及金属栅极的栅极叠层来取代该牺牲栅极电极。由于包含高k栅极介质及金属栅极的栅极叠层是在高温处理步骤(例如源极/漏极激活退火)之后形成，取代栅极工艺具有的优点为对高k栅极介质和金属栅极造成的损害最小。此外，大范围的金属可被选择作为栅极导体。
常规栅极取代工艺的其中一个严重缺点是导致高k栅极介质不仅出现在金属栅极下方，而且还出现在金属栅极的垂直侧壁上。
图1为现有技术的MOSFET的示意图，其包含栅极叠层，该叠层包含高k栅极介质及金属栅极，并使用如上文所提及的常规栅极取代工艺制造。具体地，图1示出了现有技术的MOSFET结构，其包括在其中具有源极/漏极扩散区1004的半导体衬底1000。半导体衬底1000还包含多个沟 槽隔离区1006，其被填充有沟槽介质材料。在半导体衬底1000的顶部，示出了以“U”的形状形成的高k栅极介质1008，以及位于U形高k栅极介质1008内的金属栅极1010。介质间隔物1012位于U形高k栅极介质1008的外部垂直侧壁上。图1所示结构还包括层间介质材料1020，在其中具有延伸至源极/漏极扩散区1004的上表面的接触过孔1022。层间介质材料1020通过介质间隔物1012与栅极叠层横向隔离。
金属栅极1010存在于U形高k栅极介质1008的垂直侧壁上会导致不希望的高的接触到栅极导体寄生电容。
与高k栅极介质相关的另一个问题是位于栅极拐角处的高k栅极介质(由图1所示的虚线圆形表示)可能因为厚度和/或化学成分的差异而不是理想的。常规的栅极再氧化工艺无法用来强化位于栅极拐角处的高k栅极介质，因为高k栅极介质被金属栅极和介质间隔物密封。位于栅极拐角处的不理想的高k栅极介质会导致高漏电以及低可靠性。
鉴于上述问题，需要一种新颖且改善的高k/金属栅极MOSFET，其具有减小的接触至栅极导体寄生电容和可选的改善的位于栅极拐角处的高k栅极介质。
发明内容
本发明提供一种高k栅极介质/金属栅极MOSFET，与使用常规的栅极取代工艺所制造的高k栅极介质/金属栅极MOSFET相比，其具有减少的接触至栅极导体(contact-to-gate conductor)寄生电容。与使用常规栅极取代工艺所制造的现有高k栅极介质/金属导体MOSFET相比，本发明可实现使接触至栅极导体寄生电容减少约10％或更多。
本发明还提供一种高k栅极介质/金属栅极MOSFET，其中在栅极拐角处存在改善的高k栅极介质。
在某些实施例中，本发明还提供一种高k栅极介质/金属栅极MOSFET，其包括位于金属栅极的垂直侧壁上的低k介质间隔物。所用的低k介质间隔物具有小于4，优选小于3.5的介电常数。低k介质间隔物 的存在帮助进一步降低所述接触至栅极导体寄生电容。
本发明还提供一种高k栅极介质/金属栅极MOSFET，其中位于该高k栅极介质/金属栅极叠层下方的沟道区具有约2μm或更小的长度。
概括地说，本发明提供一种半导体结构，其包含：
至少一个金属氧化物半导体场效晶体管(MOSFET)，其位于半导体衬底的表面上，所述至少一个MOSFET包含栅极叠层，所述栅极叠层从底部至顶部包括高k栅极介质和含金属栅极导体，所述含金属栅极导体具有栅极拐角，所述栅极拐角位于所述含金属栅极导体的基段处，其中所述含金属栅极导体具有垂直侧壁，除了在所述栅极拐角处之外所述垂直侧壁缺少所述高k栅极介质；
栅极介质，其横向邻接存在于所述栅极拐角处的所述高k栅极介质；以及
栅极间隔物，其横向邻接所述含金属栅极导体，且位于所述栅极介质及存在于所述栅极拐角处的所述高k栅极介质两者的上表面上。
本发明结构还包含层间介质材料，其包含导电填充的接触过孔，所述接触过孔延伸至该半导体衬底的表面，所述衬底包含所述至少一个MOSFET的源极/漏极扩散区。
在本发明某些实施例中，本发明结构还可包含间隔物衬里，其存在于所述栅极间隔物与所述层间介质材料、所述含金属栅极导体、以及所述栅极介质与存在于所述栅极拐角处的所述高k栅极介质两者的上表面之间。
在本发明的另一实施例中，所述栅极间隔物为低k介质材料(介电常数小于4)。在其他的实施例中，所述栅极间隔物包括存在于其内部中的空隙，所述空隙降低该栅极间隔物的有效介电常数。
在本发明其他的实施例中，通过引入氧和/或氮至存在于该栅极拐角处的材料中，来强化存在于该栅极拐角处的该高k栅极介质。
除了上文提及的一般半导体结构外，本发明还提供一种半导体结构，其包括：
至少一个金属氧化物半导体场效应晶体管(MOSFET)，其位于半导体衬底的表面上，所述至少一个MOSFET包含栅极叠层，所述栅极叠层 从底部至顶部包含高k栅极介质及含金属栅极导体，所述含金属栅极导体具有栅极拐角，所述栅极拐角位于所述含金属栅极导体的基段处，其中所述含金属栅极导体具有垂直侧壁，除了在所述栅极拐角处外所述垂直侧壁缺少所述高k栅极介质，与直接位于所述含金属栅极导体下方的所述高k栅极介质相比，位于所述栅极拐角处的所述高k栅极介质具有增强的接合；
栅极介质，其横向邻接存在于所述栅极拐角处的所述高k栅极介质；以及
栅极间隔物，其横向邻接所述含金属栅极导体，且位于所述栅极介质及存在于所述栅极拐角处的所述高k栅极介质两者的上表面上。
在另一实施例中，本发明提供一种半导体结构，包括：
至少一个金属氧化物半导体场效应晶体管(MOSFET)，其位于半导体衬底的表面上，所述至少一个MOSFET包括栅极叠层，所述栅极叠层从底部至顶部包括高k栅极介质及含金属栅极导体，所述含金属栅极导体具有栅极拐角，所述栅极拐角位于所述含金属栅极导体的基段处，其中所述含金属栅极导体具有垂直侧壁，除了在所述栅极拐角处外所述垂直侧壁缺少所述高k栅极介质；
栅极介质，其横向邻接存在于所述栅极拐角处的所述高k栅极介质；以及
低k栅极间隔物，在其内部包含多个空隙，并且所述低k栅极间隔物横向邻接所述含金属栅极导体，且位于所述栅极介质及存在于所述栅极拐角处的所述高k栅极介质两者的上表面上。
除了上文所述的半导体结构外，本发明还提供制造这类半导体结构的方法。概括地说，本发明的方法包括：
提供一结构，所述结构包含位于半导体衬底上的牺牲栅极及栅极介质，所述结构还包括层间介质，所述层间介质位于所述半导体衬底上并且通过牺牲间隔物与所述牺牲栅极分隔开；
去除所述牺牲栅极以及所述栅极介质的未被所述牺牲间隔物保护的一部分，以形成开口，所述开口暴露出所述半导体衬底的表面；
在所述开口内形成U形高k栅极介质以及含金属栅极导体；
去除所述牺牲间隔物以暴露出横向邻接所述含金属栅极导体的侧壁的所述U形高k栅极介质的一部分；
从所述栅极侧壁去除与所述含金属栅极导体的侧壁横向邻接的所述高k栅极介质的基本上所有的暴露部分；以及
在先前包括所述牺牲间隔物和所述U形高k栅极介质的一部分的区域中形成栅极间隔物。
附图说明
图1为(通过截面图)示出利用常规栅极取代工艺所制造的现有技术的高k栅极介质/金属导体MOSFET的示意图。
图2A、2B及2C为(通过截面图)示出根据本发明实施例的高k栅极介质/含金属导体MOSFET的示意图。
图3A至3H为(通过截面图)示出可用来制造图2A至2C所示结构的基本处理步骤。
具体实施方式
本发明提供一种至少具有减少的接触至栅极导体寄生电容的高k栅极介质/含金属MOSFET及其制造方法；现将参照下列描述及伴随本申请的附图而更详细地描述本发明。应注意本申请的附图仅提供示范说明的目的，因此，该些附图并未按比例绘制。
在下列描述中，提出诸多特定细节，例如特定结构、成分、材料、尺寸、处理步骤及技术，以提供对本发明的彻底了解。不过，本领域普通技术人员将了解本发明可在无须遵照这些特定细节的情况下实行。在其它例子中，众所周知的结构或处理步骤并未详细描述，以避免与本发明混淆。
应理解，当提到例如层、区或衬底等组件位于另一组件“上”或“上方”时，其表示该组件可直接位于另一组件上，或是存在有介于中间的组件。相对地，当提到组件“直接位于另一组件上”或“直接位于另一组件上方”时，则表示没有任何介于中间的组件存在。还可了解到当提到组件 在另一组件“下”或“下方”时，其表示该组件可直接位于另一组件的下或直接位于另一组件下方，或是可存在介于中间的组件。相对地，当提到组件“直接位于另一组件下”或“直接位于另一组件下方”时，则表示没有任何介于中间的组件存在。
还观察到虽然下列描述和附图示出了一个高k栅极介质/含金属导体MOSFET，但本发明并未受限于此。相反，可利用本发明方法来形成多个高k栅极介质/含金属导体MOSFET。形成的多个高k栅极介质/含金属导体MOSFET可全都具有相同的导电性(即，nMOSFET或pMOSFET)。或者，多个高k栅极介质/含金属导体MOSFET可包括第一组MOSFET，其具有第一导电性(nMOSFET或pMOSFET)；及第二组MOSFET，其具有与该第一导电性类型MOSFET不同的第二导电性。
如上文所述，本发明提供一种高k栅极介质/金属栅极MOSFET，与使用常规栅极取代工艺所制造的高k栅极介质/金属栅极MOSFET相比，其具有减少的接触至栅极导体寄生电容。
图2A至2C示出了本发明的各种不同结构的实施例。在图2A中，示出了本发明的第一实施例。图2A所示结构包括位于半导体衬底12的表面上的至少一个金属氧化物半导体场效应晶体管(MOSFET)100。至少一个MOSFET 100包括栅极叠层，该栅极叠层由底部至顶部包括高k栅极介质28及含金属栅极导体30。含金属栅极导体30具有位于该含金属栅极导体的基段处的多个栅极拐角31。该含金属栅极的基段在此处定义为栅极导体的垂直侧壁与栅极导体的底壁接触的区域。此外，含金属栅极导体30具有多个垂直侧壁102A和102B，除了在栅极拐角31处之外垂直侧壁102A和102B缺少高k栅极介质28；术语“垂直侧壁”用于表示与公共底壁垂直的侧壁，或这些侧壁可能具有倾斜度(tapering)。图2A中还示出了栅极介质18，其横向邻接位于栅极拐角31处的高k栅极介质28，以及栅极间隔物36，其横向邻接该含金属栅极导体30。栅极间隔物36位于栅极介质18及存在于栅极拐角31处的高k栅极介质28两者的上表面上。
本发明的新颖结构进一步包括层间介质材料24，其包含多个导电填充 的接触过孔40，该些接触过孔40延伸至半导体衬底12的表面，该衬底包括至少一个MOSFET 100的源极/漏极扩散区14。
在本发明某些实施例中，间隔物衬里34存在于栅极间隔物36与层间介质材料24之间、栅极间隔物36与含金属栅极导体30之间、以及栅极间隔物36与栅极介质18和存在于栅极拐角31处的高k栅极介质28两者的上表面之间。
参阅图2B，其示出了本发明的第二结构实施例，其包括如图2A所示的相同的基本组件，除了位于栅极拐角处的高k栅极介质相比于直接位于含金属栅极导体下方的高k栅极介质具有改善的接合之外。在图2B中，参考标号28’表示位于栅极拐角31处的具有改善的接合的高k栅极介质，而参考标号28表示直接位于含金属栅极导体30下方的高k栅极介质。
图2C说明本发明的第三结构实施例。具体地，图2C所示结构包括图2B中的相同组件，除了在栅极间隔物36的内部中含有空隙38之外。空隙38的存在降低了栅极间隔物36的有效介电常数。
现参照图3A至3H，其说明可用于制造图2A至2C所示的本发明结构的基本处理步骤。本发明的处理步骤包括首先形成常规MOSFET，其具有虚栅极(即，牺牲栅极)、栅极介质、牺牲间隔物以及层间介质。接着去除未被牺牲间隔物保护的牺牲栅极和栅极介质以形成开口，该开口暴露出半导体衬底的表面。在该开口内形成U形高k栅极介质，然后形成含金属栅极导体。接着去除牺牲间隔物，以暴露横向邻接该含金属栅极导体的侧壁的高k栅极介质的一部分。接着将横向邻接该含金属栅极导体的侧壁的高k栅极介质的暴露部分从栅极侧壁上去除，随后形成间隔物。
首先参照图3A，其示例可用于本发明中的初始半导体结构10。如图所示，初始半导体结构10包括半导体衬底12，其已经过处理而包括至少一个隔离区16和源极/漏极区14。硅化物层(未示出了)可存在于源极/漏极区的表面以降低电阻。半导体衬底12进一步包括栅极介质18，其位于衬底12的表面上。栅极介质18具有中心部分和外部边缘部分，该中心部分上具有牺牲栅极20，而这些外部边缘部分邻接该中心部分且在其上各 自具有牺牲间隔物22。在图3A中提供垂直虚线以示出在栅极介质的中心部分与栅极介质的外部部分之间的虚构边界。
图3A所示结构还包括层间介质材料24，其位于半导体衬底12的不包括栅极介质18、牺牲栅极20及牺牲间隔物22的部分上。如图所示，层间介质24的上表面与牺牲栅极20的上表面共平面。
图3A所示的半导体衬底12包含任何呈现半导体性质的材料。呈现半导体性质的材料的范例包含，但不限于，Si、SiGe、SiC、SiGeC、Ge、Ga、GaAs、InAs、InP及所有其它第III/V族或第II/VI族的化合物半导体。半导体衬底12还可包括有机半导体或成层半导体，例如，硅/硅锗、绝缘体上硅或绝缘体上硅锗。在本发明的某些实施例中，优选地，半导体衬底12包括含硅半导体材料，即，包含硅的半导体材料。除了上述类型的半导体衬底之外，用于本发明的半导体衬底12还可包括混合定向(HOT)的半导体衬底，其中该HOT衬底具有不同晶体取向的表面区。
半导体衬底12可经过掺杂、未经掺杂，或在其内包含掺杂区和未掺杂区。半导体衬底12可是应变的、非应变的、其内包含应变区和未应变区，或是包含拉伸应变区及压缩应变区。
图3A所示的各个隔离区16包括沟槽介质材料，例如氧化物，且可选地，包含衬里(liner)，例如，氮化硅或氮氧化硅，其可存在于沟槽的侧壁上。在形成图3A所示的其它组件前，使用常规沟槽隔离工艺在半导体衬底12中形成沟槽隔离区16，该沟槽隔离工艺包括首先在半导体衬底12中蚀刻至少一个沟槽，可选地用沟槽衬里填充该至少一个沟槽，随后以沟槽介质材料填充该沟槽。在沟槽填充之后，使用常规平坦化工艺，例如，化学机械抛光和/或研磨，来提供平坦的结构。在某些实施例中，可在以沟槽介质材料填充该沟槽之后执行致密化工艺(densification)。
应注意，通常在有垫层(未示出)存在的条件下执行沟槽隔离区的形成工艺，且在半导体衬底12中形成了至少一个沟槽隔离区16之后从该结构去除该垫层。垫层包括氮化硅，并且可选地包含下伏的氧化硅。任何可选择性地去除垫层的常规剥离工艺可用来从结构去除垫层。
可选地，可通过其它众所周知的方法来形成各个隔离区16，例如，LOCOS(硅的局部氧化)。
在本发明的此处，可使用两种不同的处理序列中的一种来制造图3A所示的结构。在第一处理序列中，使用常规的CMOS处理流程，栅极介质18的均厚层(blanket layer)形成在包含在沟槽隔离区16顶部在内的半导体衬底12的整个表面上。栅极介质18的均厚层可通过常规的沉积工艺来形成，包括，例如化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、蒸发、化学溶液沉积及原子层沉积(ALD)。可选地，热氧化、氮化或氮氧化法可用于形成栅极介质18的均厚层。栅极介质18的均厚层的厚度比随后将形成的高k栅极介质的厚度更厚。典型地，栅极介质18的厚度从约2纳米至约20纳米(nm)，更典型者厚度为约3纳米至约10纳米。栅极介质18典型为半导体材料的氧化物，更典型为硅的氧化物。
在形成栅极介质18的均厚层之后，利用常规的沉积工艺形成牺牲栅极材料(例如，多晶硅或硅锗)的均厚层，常规的沉积工艺包括例如CVD、LPCVD、PECVD、蒸发、化学溶液沉积及物理气相沉积(PVD)。在沉积之后，牺牲栅极材料的均厚层(其形成牺牲栅极20)具有约20纳米至约200纳米的厚度，更典型为约50至约100纳米的厚度。
接着使用包含光刻和蚀刻的构图工艺来构图牺牲栅极材料的均厚层，使其成为图3A所示的牺牲栅极20。光刻步骤包含施加光致抗蚀剂至牺牲栅极材料均厚层的表面、将光致抗蚀剂暴露至期望的辐射图案，接着显影该已曝光的光致抗蚀剂。蚀刻步骤包括干法蚀刻或湿法蚀刻。优选地，利用干法蚀刻工艺，例如，反应离子蚀刻、离子束蚀刻及等离子体蚀刻。蚀刻工艺停止于栅极介质18的表面上。在蚀刻之后，利用常规光致抗蚀剂剥离工艺(例如，灰化)将该已曝光及显影的光致抗蚀剂从该结构上去除。
此时，源极/漏极区14被形成到半导体衬底12中。各源极/漏极区14可进一步包括源极/漏极扩展区，其与牺牲栅极20部分重叠。形成源极/漏极和源极/漏极扩展包括利用本领域中公知的离子注入工艺、间隔物形成及 掺杂剂激活退火。
接着，通过沉积和蚀刻而在牺牲栅极20的垂直侧壁上以及在栅极介质18的均厚层的表面上形成牺牲间隔物22。牺牲间隔物22由含氮化物的材料组成，例如，氮化硅或氮氧化硅。可在源极和漏极区形成之前或之后形成牺牲间隔物22。如果形成源极/漏极扩展，可在形成源极/漏极扩展之前或之后形成牺牲间隔物22。
接下来，利用牺牲间隔物22和牺牲栅极20作为蚀刻掩模来蚀刻栅极介质18的均厚层。
形成层间介质材料24的均厚层，以覆盖该结构的所有暴露表面。层间介质材料24利用任何常规的沉积工艺来形成，包含例如，化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、次大气压化学气相沉积(SACVD)、蒸发、化学溶液沉积及旋转涂布。层间介质材料24包括任何常规的介质材料，例如，二氧化硅、硅酸盐玻璃、倍半硅氧烷(silsesquioxane)、包含硅、碳、氧及氢原子的有机硅酸盐，以及热固性聚芳撑醚。使用术语“聚芳撑(polyarylene)”代表通过化学键、稠环、或例如氧、硫、砜、亚砜、羰基等的惰性链接基团链接在一起的芳基部分。
接着使用平坦化工艺，例如化学机械抛光和/或研磨，来形成共面结构，如图3A所示。
在另一处理序列中，通过首先处理衬底12，使其包含隔离区16而形成图3A所示的初始结构。接下来，形成层间介质材料24，且使用光刻及蚀刻来限定位于介质材料中的至少一个开口，该开口暴露出半导体衬底12的表面。源极/漏极区14可在此时形成，随后则在开口底部形成栅极介质18。接下来，牺牲间隔物22形成在已构图的层间介质材料24的暴露的侧壁上，接着形成牺牲栅极20。接着，典型地使用平坦化工艺来提供图3A图所示的共面结构。本发明的此实施例典型地用于形成器件沟道，其长度约为2μm或更小。
在提供第3A图所示的初始结构10后，将牺牲栅极20和直接位于牺 牲栅极20下方的牺牲栅极介质18从该结构上去除。去除牺牲栅极20和牺牲栅极20下方的栅极介质18提供开口26，其暴露出半导体衬底12的表面。例如，图3B示出了在执行本发明的此步骤之后所形成的结构。根据牺牲栅极20和栅极介质18的材料，各种适当的工艺可用于去除这些材料。举例来说，使用包含基于氨的化学剂的蚀刻剂的湿法蚀刻工艺，或干法蚀刻工艺(例如使用包含氟化硫的蚀刻剂的等离子体蚀刻)，可用于去除包括多晶硅的牺牲栅极20。使用氢氟酸蚀刻剂的湿法蚀刻工艺可用于去除包括氧化硅的栅极介质18。
接下来，在开口26内部形成U形高k栅极介质28，随后在U形高k栅极介质28的暴露表面上形成含金属导体30，从而提供，例如图3C所示的结构。U形高k栅极介质28包括任何介电常数大于4.0，典型大于7.0的介质材料。这类高k栅极介质材料的范例包含，但不受限于，TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、混合的金属氧化物，例如钙钛矿型氧化物(perovskite-type oxide)及其组合物与多层。前述金属氧化物的硅酸盐及氮化物也可作为高k栅极介质材料。可选择地，第一界面层(未示出)可形成在U形高k栅极介质28与衬底12之间的界面处，以改善器件特性，例如，减少界面陷阱。第一界面层，如果存在，可包括氧化硅、氮化硅或氮氧化物，其可通过热氧化、化学氧化、热氮化及化学氮化来形成。此外，可在形成含金属栅极导体30之前，在U形高k介质28的顶部或内部沉积第二界面层(未示出)。第二界面层(如果存在)可通过调整功函数和/或稳定平带电压和阈值电压以有助于器件特性最佳化。第二界面层(如果存在)包括含稀土的层，其包括La2O3、LaN或任何其它适当的材料。U形高k栅极介质28可通过常规的沉积工艺来形成，包含，但不受限于，原子层沉积(ALD)、化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、快速热化学气相沉积(RTCVD)、限制反应处理CVD(LRPCVD)、超高真空化学气相沉积(UHVCVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、物理气相沉积、离子束沉积、电子束沉积及激光辅助沉积。
U形高k栅极介质28的厚度小于栅极介质18的剩余外部部分的厚度。典型地，U形高k栅极介质28具有约1纳米至约20纳米的厚度，更典型为约2纳米至约10纳米的厚度。
含金属栅极导体30利用常规的沉积工艺来形成，例如，原子层沉积(ALD)、化学气相沉积(CVD)、金属有机化学气相沉积(MOCVD)、分子束外延(MBE)、物理气相沉积、溅射、镀敷、蒸发、离子束沉积、电子束沉积、激光辅助沉积及化学溶液沉积。含金属栅极导体30包含导电金属，例如，但不受限于，Al、W、Cu、Pt、Ag、Au、Ru、Ir、Rh及Re、导电金属的合金，例如Al-Cu、导电金属的硅化物，例如硅化钨和硅化铂、导电金属的氮化物，例如AlN，以及其组合和多层。常规的平坦化工艺，例如化学机械抛光(CMP)，可用于去除任何沉积在层间介质24与牺牲间隔物22顶部的含金属栅极导体30。常规的蚀刻工艺，例如湿法蚀刻或干法蚀刻，可用于去除任何沉积在层间介质24与牺牲间隔物22顶部的U形高k栅极介质。
接下来，如图3D所示，将牺牲间隔物22从结构上去除，暴露出栅极介质18的剩余的外部部分、U形高k栅极介质28的外部侧壁以及层间介质材料24的侧壁。牺牲间隔物22利用蚀刻工艺去除，该工艺会相对于层间介质材料24和剩余的栅极介质18而选择性地去除牺牲间隔物22的材料。这样的可以使用的蚀刻工艺的范例包括使用含有磷酸或氢氟酸和乙二醇(HF/EG)的混合物的蚀刻剂的湿法蚀刻工艺，以去除由氮化硅形成的牺牲间隔物22。可选地，当牺牲间隔物22包含氮化硅时，其可通过例如化学下游蚀刻(CDE)的干法蚀刻工艺来去除。
图3E示出了在从基本上所有的含金属栅极导体30的垂直侧壁去除U形高k栅极介质28之后所形成的结构。存在较厚的栅极介质18可确保在不会使含金属栅极导体30下方的高k栅极介质材料产生底切的情况下，基本上从含金属栅极侧壁完全去除高k栅极材料。基本上从含金属栅极导体30的垂直侧壁去除所有的高k栅极介质材料可以减少接触至栅极导体电容。
应注意到，某部分的U形高k栅极介质28仍保留在含金属的栅极导体30的垂直侧壁上，覆盖在含金属栅极导体30的基段处的栅极拐角。在图3E中，以参考标号31标明栅极拐角。在本发明中，保留在栅极拐角31处的高k栅极材料的高度小于剩余的栅极介质18的高度。
从基本上含金属栅极导体30的所有垂直侧壁去除U形高k栅极介质28利用蚀刻工艺来执行，相对于其它暴露于蚀刻工艺中的材料而言，该工艺选择性地去除高k栅极介质材料。这样的蚀刻工艺的范例包括硼-卤素等离子体，其包含硼-卤素化合物(例如，BCl3)和氮气。可选地，可在去除牺牲间隔物22时，同时从含金属栅极导体30的垂直侧壁去除高k栅极介质28。
在本发明的某些实施例中，可强化未受含金属栅极导体30保护且邻接栅极拐角31的剩余的U形高k栅极介质28的一部份，以减少存在于栅极拐角31处的泄漏和可靠性问题。当使用高k栅极介质材料时，由于应力和/或薄膜沉积的缘故，可使得在栅极拐角处增加泄漏电流并减少可靠性。剩余的U形高k栅极介质28的强化区在图3F中被标示为28’。
在本发明中，通过利用低能量(约20KeV的量级或更小)氧离子和/或氮离子注入工艺实现强化。所用的氧和/或氮离子的剂量范围典型为约1E12至约1E15原子/cm2，而更典型的剂量范围为约1E13至约1E14原子/cm2。可选地，可使用低温氧化、氮化或氮氧化工艺(温度约950℃或更小)，来产生在栅极拐角31处的上述高k栅极材料的强化。执行上述技术中的一种的净效果为改善高k栅极介质材料中的化学接合。
此处提及，在本发明中，直接位于栅极导体下方的高k栅极介质28具有高度h3，该高度h3小于位于栅极拐角处的剩余的高k栅极介质的高度h2，且位于栅极拐角处的剩余的高k栅极介质的高度h2基本上等于或小于剩余的栅极介质18的高度h1。换言之，栅极介质具有第一高度，存在于栅极拐角处的高k栅极介质具有第二高度，且直接位于该含金属栅极导体下方的高k栅极介质具有第三高度，其中该第一高度基本上等于或大于该第二高度，而该第二高度大于该第三高度。
剩余的附图示出了位于栅极拐角31处的强化后的高k栅极介质区28’。虽然这被示出在剩余的附图中，但若省略该可选的强化步骤时，仍可使用后续的处理步骤。
图3G示出了，在去除基本上所有的位于含金属栅极导体30的侧壁上的高k栅极材料之后，在当去除牺牲间隔物22时所产生的空间内形成可选的间隔物衬里34和栅极间隔物36之后所形成的结构。该可选的间隔物衬里34包括第一介质材料，其与用来形成栅极间隔物36的第二介质材料不相同。典型地，间隔物衬里34包括氮化硅，而栅极间隔物36包括二氧化硅。在某些实施例中，栅极间隔物36为低k(介电常数小于4.0)介质材料，例如，包含至少硅、碳、氧及氢原子的有机硅酸盐，而间隔物衬里34包括氧化硅。
可选的间隔物衬里34在沉积后具有约1纳米至约10纳米的厚度，而更典型为约2至5纳米。可选的间隔物衬里34可由沉积工艺形成，例如，原子层沉积(ALD)、化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、次大气压化学气相沉积(SACVD)、快速热化学气相沉积(RTCVD)、高温氧化物沉积(HTO)、低温氧化物沉积(LTO)、限制反应处理CVD(LRPCVD)、旋转涂布、化学溶液沉积或任何其它适当的工艺。栅极间隔物36由任何适当的沉积工艺形成，例如，CVD及旋转涂布。此处指出栅极间隔物36的底部表面位于剩余的栅极介质18和存在于栅极拐角31处的高k栅极介质两者的顶部上方或直接位于其上。在常规结构中，栅极间隔物直接位于半导体衬底的表面上。
在本发明某些取决于要形成栅极间隔物36的空间的几何形状以及所使用的沉积工艺的实施例中，空隙38(见图2C)可存在于栅极间隔物36的内部部分中。空隙的存在具有进一步减少本发明中所用的栅极间隔物36的有效介电常数的效果。
图3H示出了出在层间介质材料24中形成导电填充的接触过孔40之后的结构，其中这些接触过孔40延伸至包括源极/漏极扩散区14的半导体 衬底12的表面。可利用光刻、蚀刻并且以导电材料填充所形成的接触过孔来形成导电填充的接触过孔40。可选地，可在以导电材料填充过孔之前，在接触过孔的暴露的侧壁上形成扩散阻挡层，例如TiN或TaN。用于填充接触开口的导电材料包括任何导电材料，其包括任一种可用于形成含金属栅极导体30的导电材料。
在本发明的某些实施例中，可在从含金属栅极导体30的垂直侧壁上去除高k栅极介质28和牺牲间隔物22之前，在层间介质材料24中形成导电填充的接触过孔40。
虽然已参照优选实施例具体示出并描述了本发明，但本领域的普通技术人员将了解可在不偏离本发明精神和范围的情况下做出形式和细节上的前述及其它变化。因而，其意指本发明并不局限于所描述和示出的确切形式与细节，而是落入在所附权利要求的范围内。
工业适用性
本发明发现了在集成电路芯片中的MOSFET半导体器件的设计和制造中的工业适用性，其发现了在大范围电子和电气装置中的应用。

Claims (33)

1.一种半导体结构，包括：
至少一个金属氧化物半导体场效应晶体管(100)，其位于半导体衬底(12)的表面上，所述至少一个金属氧化物半导体场效应晶体管包括栅极叠层，所述栅极叠层从底部至顶部包括高k栅极介质(28)和含金属栅极导体(30)，所述含金属栅极导体(30)具有栅极拐角(31)，所述栅极拐角(31)位于所述含金属栅极导体(30)的基段处，其中所述含金属栅极导体具有垂直侧壁(102A、102B)，除了在所述栅极拐角处之外所述垂直侧壁缺少所述高k栅极介质(28)；
栅极介质(18)，其横向邻接存在于所述栅极拐角(31)处的所述高k栅极介质(28)；以及
栅极间隔物(36)，其横向邻接所述含金属栅极导体(30)，且位于所述栅极介质(18)及存在于所述栅极拐角(31)处的所述高k栅极介质两者的上表面上。
2.如权利要求1所述的半导体结构，还包含层间介质材料，其具有导电填充的接触过孔，所述接触过孔延伸至包括所述至少一个金属氧化物半导体场效应晶体管的源极区与漏极区的所述半导体衬底的表面。
3.如权利要求2所述的半导体结构，还包括间隔物衬里，所述间隔物衬里存在于所述栅极间隔物与所述层间介质材料之间、所述栅极间隔物与所述含金属栅极导体之间、以及所述栅极间隔物与所述栅极介质和存在于所述栅极拐角处的所述高k栅极介质两者的上表面之间。
4.如权利要求1所述的半导体结构，其中所述栅极间隔物为低k介质材料，其具有小于4的介电常数。
5.如权利要求1所述的半导体结构，其中所述栅极间隔物包括空隙，其存在于所述栅极间隔物的内部，所述空隙降低所述栅极间隔物的有效介电常数。
6.如权利要求1所述的半导体结构，其中所述栅极介质具有第一高度， 存在于所述栅极拐角处的所述高k栅极介质具有第二高度，以及直接位于所述含金属栅极导体下方的所述高k栅极介质具有第三高度，其中所述第一高度基本上等于或大于所述第二高度，而所述第二高度大于所述第三高度。
7.如权利要求1所述的半导体结构，其中与直接位于所述含金属栅极导体下方的所述高k栅极介质相比，位于所述栅极拐角处的所述高k栅极介质具有增强的接合。
8.如权利要求1所述的半导体结构，其中所述高k栅极介质包括下列其中一个：TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物、及TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物的硅酸盐或氮化物。
9.如权利要求1所述的半导体结构，其中所述含金属栅极导体为导电金属、导电金属硅化物、及导电金属氮化物其中之一。
10.如权利要求9所述的半导体结构，其中所述导电金属包括导电金属合金。
11.一种半导体结构，包括：
至少一个金属氧化物半导体场效应晶体管(100)，其位于半导体衬底(12)的表面上，所述至少一个金属氧化物半导体场效应晶体管(100)包括栅极叠层，所述栅极叠层从底部至顶部包括高k栅极介质(28)和含金属栅极导体(30)，所述含金属栅极导体(30)具有栅极拐角(31)，所述栅极拐角(31)位于所述含金属栅极导体(30)的基段处，其中所述含金属栅极导体具有垂直侧壁(102A、102B)，除了在所述栅极拐角处之外所述垂直侧壁缺少所述高k栅极介质(28)，与直接位于所述含金属栅极导体(30)下方的所述高k栅极介质(28)相比，位于所述栅极拐角(31)处的所述高k栅极介质(28)具有增强的接合；
栅极介质(18)，其横向邻接存在于所述栅极拐角(31)处的所述高k栅极介质(28)；以及
栅极间隔物(36)，其横向邻接所述含金属栅极导体(30)，且位于 所述栅极介质(18)及存在于所述栅极拐角(31)处的所述高k栅极介质(28)两者的上表面上。
12.如权利要求11所述的半导体结构，还包括层间介质材料，其具有导电填充的接触过孔，所述接触过孔延伸至包括所述至少一个金属氧化物半导体场效应晶体管的源极区与漏极区的所述半导体衬底的表面。
13.如权利要求12所述的半导体结构，还包含间隔物衬里，所述间隔物衬里存在于所述栅极间隔物与所述层间介质材料之间、所述栅极间隔物与所述含金属栅极导体之间、以及所述栅极间隔物与所述栅极介质和存在于所述栅极拐角处的所述高k栅极介质两者的上表面之间。
14.如权利要求11所述的半导体结构，其中所述栅极间隔物为低k介质材料，其具有小于4的介电常数。
15.如权利要求11所述的半导体结构，其中所述栅极间隔物包含空隙，其存在于所述栅极间隔物的内部，所述空隙降低所述栅极间隔物的有效介电常数。
16.如权利要求11所述的半导体结构，其中所述栅极介质具有第一高度，存在于所述栅极拐角处的所述高k栅极介质具有第二高度，以及直接位于所述含金属栅极导体下方的所述高k栅极介质具有第三高度，其中所述第一高度基本上等于或大于所述第二高度，而所述第二高度大于所述第三高度。
17.如权利要求11所述的半导体结构，其中所述高k栅极介质包括下列其中一个：TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物、及TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物的硅酸盐或氮化物。
18.如权利要求11所述的半导体结构，其中所述含金属栅极导体为导电金属、导电金属硅化物、及导电金属氮化物其中之一。
19.如权利要求18所述的半导体结构，其中所述导电金属包括导电金属合金。
20.一种半导体结构，包括： 
至少一个金属氧化物半导体场效应晶体管(100)，其位于半导体衬底的表面上，所述至少一个金属氧化物半导体场效应晶体管(100)包括栅极叠层，所述栅极叠层从底部至顶部包括高k栅极介质(28)和含金属栅极导体(30)，所述含金属栅极导体(30)具有栅极拐角(31)，所述栅极拐角(31)位于所述含金属栅极导体(30)的基段处，其中所述含金属栅极导体(30)具有垂直侧壁(102A、102B)，除了在所述栅极拐角处之外所述垂直侧壁缺少所述高k栅极介质(28)；
栅极介质(18)，其横向邻接存在于所述栅极拐角(31)处的所述高k栅极介质(28)；以及
低k栅极间隔物(36)，在其内部包含多个空隙，并且所述低k栅极间隔物横向邻接所述含金属栅极导体(30)，且位于所述栅极介质及存在于所述栅极拐角(31)处的所述高k栅极介质(28)两者的上表面上。
21.如权利要求20所述的半导体结构，还包含层间介质材料，其具有导电性填充的接触过孔，所述接触过孔延伸至包括所述至少一个金属氧化物半导体场效应晶体管的源极区与漏极区的所述半导体衬底的表面。
22.如权利要求21所述的半导体结构，还包含间隔物衬里，所述间隔物衬里存在于所述栅极间隔物与所述层间介质材料之间、所述栅极间隔物与所述含金属栅极导体、以及所述栅极间隔物与所述栅极介质和存在于所述栅极拐角处的所述高k栅极介质两者的上表面之间。
23.如权利要求20所述的半导体结构，其中所述栅极介质具有第一高度，存在于所述栅极拐角处的所述高k栅极介质具有第二高度，以及直接位于所述含金属栅极导体下方的所述高k栅极介质具有第三高度，其中所述第一高度基本上等于或大于所述第二高度，而所述第二高度大于所述第三高度。
24.如权利要求20所述的半导体结构，其中所述高k栅极介质包括下列其中一个：TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物、及TiO2、Al2O3、ZrO2、HfO2、Ta2O5、La2O3、钙钛矿型氧化物的硅酸盐或氮化物。 
25.如权利要求20所述的半导体结构，其中所述含金属栅极导体为导电金属、导电金属硅化物及导电金属氮化物的其中之一。
26.如权利要求25所述的半导体结构，其中所述导电金属包括导电金属合金。
27.如权利要求20所述的半导体结构，其中与直接位于所述含金属栅极导体下方的所述高k栅极介质相比，位于所述栅极拐角处的所述高k栅极介质具有增强的接合。
28.一种形成半导体结构的方法，其包括：
提供结构，所述结构包括位于半导体衬底上的牺牲栅极和栅极介质，所述结构还包括层间介质，所述层间介质位于所述半导体衬底上并通过牺牲间隔物与所述牺牲栅极分隔开；
去除所述牺牲栅极和所述栅极介质的未被所述牺牲间隔物保护的一部分，以形成开口，所述开口暴露出所述半导体衬底的表面；
在所述开口内形成U形高k栅极介质和含金属栅极导体；
去除所述牺牲间隔物以暴露出横向邻接所述含金属栅极导体的侧壁的所述U形高k栅极介质的一部分；
从所述栅极侧壁去除与所述含金属栅极导体的侧壁横向邻接的所述高k栅极介质的基本上所有的暴露部分；以及
在先前包括所述牺牲间隔物和所述U形高k栅极介质的一部分的区域中形成栅极间隔物，从而提供至少一个金属氧化物半导体场效应晶体管，所述至少一个金属氧化物半导体场效应晶体管包括栅极叠层，所述栅极叠层从底部至顶部包括所述高k栅极介质和所述含金属栅极导体，所述含金属栅极导体具有栅极拐角，所述栅极拐角位于所述含金属栅极导体的基段处，其中所述含金属栅极导体具有垂直侧壁，除了在所述栅极拐角处之外所述垂直侧壁缺少所述高k栅极介质，其中所述栅极介质横向邻接存在于所述栅极拐角处的所述高k栅极介质，以及所述栅极间隔物横向邻接所述含金属栅极导体且位于所述栅极介质及存在于所述栅极拐角处的所述高k栅极介质两者的上表面上。 
29.如权利要求28所述的方法，其中所述方法还包括形成所述层间介质，其具有导电性填充的接触过孔，所述接触过孔延伸至包括所述至少一个金属氧化物半导体场效应晶体管的源极区与漏极区的所述半导体衬底的表面。
30.如权利要求29所述的方法，还包含形成间隔物衬里，所述间隔物衬里存在于所述栅极间隔物与所述层间介质之间、所述栅极间隔物与所述含金属栅极导体之间、以及所述栅极间隔物与所述栅极介质和位于所述含金属栅极导体的拐角处的所述高k栅极介质两者的上表面之间。
31.如权利要求29所述的方法，还包括强化所述高k栅极介质位于所述含金属栅极导体的栅极拐角处的一部分，使得与直接位于所述含金属栅极导体下方的所述高k栅极介质相比，增加了位于所述含金属栅极导体的栅极拐角处的所述高k栅极介质中的接合。
32.如权利要求31所述的方法，其中所述强化步骤通过离子注入氧离子和氮离子中的一种或通过热工艺来获得。
33.如权利要求29所述的方法，其中形成所述栅极间隔物包括在所述栅极间隔物的内部区域中形成空隙。 
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