TW200845351A - Semiconductor device, leadframe and manufacturing method of semiconductor device - Google Patents

Semiconductor device, leadframe and manufacturing method of semiconductor device Download PDF

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Publication number
TW200845351A
TW200845351A TW097106850A TW97106850A TW200845351A TW 200845351 A TW200845351 A TW 200845351A TW 097106850 A TW097106850 A TW 097106850A TW 97106850 A TW97106850 A TW 97106850A TW 200845351 A TW200845351 A TW 200845351A
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TW
Taiwan
Prior art keywords
semiconductor device
wire
semiconductor wafer
solder
groove
Prior art date
Application number
TW097106850A
Other languages
English (en)
Other versions
TWI421998B (zh
Inventor
Yasumasa Kasuya
Motoharu Haga
Shoji Yasunaga
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of TW200845351A publication Critical patent/TW200845351A/zh
Application granted granted Critical
Publication of TWI421998B publication Critical patent/TWI421998B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Description

200845351 九、發明說明： 【發明所屬之技術領域】 本發明係關於半導體裝置、導線架及半導體裝置之製造 方法。 【先前技術】
Ik著電子機器之小型化，適用QFN(Q⑽d FW N leaded Package:爲平式四邊無接腳型封裝）之半導體裝置 之需求曰盈提高。 適用QFN之半導體裝置例如係藉MAp(M〇⑷d八叫 Packaging :模製陣列封裝）方式製作。在MAp方式中，利 用封裝樹脂將複數半導體晶片一併封裝在導線架上以後， 切開分成具有“固半導體晶片之半導體裝置之個體。 導線架例如係由銅所構成。此導線架具有格子狀之支持 部。在被支持部所包圍之各矩形狀區域内，形成有矩形狀 之晶粒塾（die pad)、與複數導線。導線配置於晶粒塾之周 圍。導線之基端部連接於支持部，遊端部形成向晶粒塾 延伸之長條形狀。 半導體晶片被晶粒接合（die b〇nding)在各晶粒塾 接(線接合’―— 接八1時^圍之^線之上面。當所有半導體晶片之線 ，將導線架設置於成型模具，利用樹脂將該導 線木上之所有半導I#曰Η />£ 4： t 44. 括心M 併封裝。其後，沿著設定在支 …刀割線將切割鋸由導線架下面側 部及支持部上之封壯& & ^ Μ支持 衣树月曰。猎此，各導線被自支持部切離 129430.doc 200845351 而獲得半導體裝置之個體。 在此半導體裝置中，各導線之下面露出於封裝樹脂之下 面，使各導線之下面接合於安裝基板（布線基板）上之接合 面（land)，藉以達成半導體裝置對安裝基板之安裝。在適 ‘ 帛卿之半導體裝置中，由於導線並未由封裝樹脂之側面 . 延伸，故與適用QFp(Quad Flat Package :扁平式四邊有接 腳型封裝）之半導體裝置相比，可大幅減少安裝面積。 • [專利文獻1 ] 曰本特開2001-257304號公報 【發明内容】 [發明所欲解決之問題] 然而，利用切割鋸將各導線自支持部切離之際，導線材 料之銅會被拉扯而延伸，而在導線之端部有可能產生向下 方延伸之料。產生此種溢料時，溢料會抵接到安裝基板 上之接合面，半導體裝置會因該溢料之部份而由安裝基板 • 翹起，故半導體裝置會以傾斜之狀態被安裝於安裝基板。 此種安裝狀態會因周圍之溫度變化而造成安裝基板之翹曲 之原因，而有發生因此翹曲引起之導線與接合面之連接不 - 良等安裝不良之虞。 ^ 因此’本發明之目的在於可防止溢料引起之安裝不良之 發生之半導體裝置及導線架、以及使用該導線架之半導體 裝置之製造方法。 [解決問題之技術手段] 本發明之一局面之半導體裝置係包含：半導體晶片；及 129430.doc 200845351 I ”八係配置於前述半導體晶片之周圍而向與前述半導 體曰曰片之側面交叉之方向延伸’至少遠離前述半導體晶片 2側之端。卩被接合於安裝基板。在前述導線中，在對前述 女裝基板之接合面及在遠離前述半導體晶片之側之端部開 ^溝係在與厚度方向正交且沿著前述端面之寬度方向之 全寬中形成，在前述溝中埋設由焊料構成之埋設體。 曰在導線中，形成有在對安裝基板之接合面及遠離半導體 晶片之側之端部（外端面）開放之溝。在此溝中，埋設由焊 料構成之埋δ又體。因此，在自導線架切離導線之際，切斷 刀（例如切割鋸）會接觸到導線之外端面及埋設體之端面。 溝/口著見度方向之全寬中形成，故即使產生因埋設體之材 料之焊料被切斷刀拉扯而延伸之溢料，也不會產生因導線 之材料被切斷刀拉扯而延伸之溢料。即使有焊料構成之溢 料存在，該溢料也會被半導體裝置對安裝基板之安裝時之 回流（reflow)所熔化，故不會有發生半導體裝置以傾斜之 狀態被安裝於安裝基板之虞。故半導體裝置不會發生溢料 引起之安裝不良。又，因埋設體係由焊料所構成，故可使 用作為導線與安裝基板之接合劑之焊料濕潤達到埋設體之 多而面’可在導線之端面形成所謂焊料嵌條。因此，容易從 外觀檢查導線與布線基板之接合（焊接）狀態。 本舍明之另一局面之導線架係包含：晶粒墊，其係在一 方側之面裝载有半導體晶片；導線，其係配置於前述晶粒 塾之周圍而向與说述晶粒墊之對向方向延伸，·及支持部， 其係連接前述導線之遠離前述晶粒墊之側之端部。在前述 129430.doc 200845351 ¥線中，在與遠離前述晶粒塾之側之端部之前述一方侧相 反:之面，在與該導線之長側方向正交且與厚度方向正交 之寬度方向之全寬中形成有溝。 利用此導線架，藉由包含下列步驟之製造方法，可製造 可防止溢料引起之安裝不良之發生之半導體裝置：接合步 驟八係將半導體晶片晶粒接合在前述晶粒塾上，以接合 線電性連㈣述半導體晶片與前料線；封裝步驟，μ ^述接合步驟後，以使埋人前述溝之前述焊料由封裝樹 脂露出之方式，藉前述封裝樹脂將前述半導體晶片與前述 導線架同時封裝’·及切割步驟’其係藉使用切割鑛之切 斷’除去前述支持部及前述支持部上之前料襞樹脂。 •酋在導=架之與配置半導體晶片之一方側相反側之面，於 導線之遠離晶粒塾之側之端部形成溝。此溝被焊料所完全 填埋”去支持部及支持部上之封裝樹脂之：二 步驟中，切割鋸之側面會接觸到導線、埋在溝中之焊料及 封裝樹月旨。由於溝沿著導線之寬度方向之全寬中形成’，故 即使產生因埋入溝中之焊料被切割鋸拉扯而延伸之溢料， 導線之材料也不會產生因被切斷刀拉扯而延伸之溢：:即 使有焊料構成之溢料存在，該溢料也會被半導體裝置對安 裝基板之安裝時之回流所炼化，故不會有發生半導體穿置 以傾斜之狀態被安裝於安裝基板之虞。故依據前述之製造 方法，可製造可防止溢料引起之安裝不良之發生之二 裝置。 今體 本發明之上述或其他目的、特徵及效果可由參照附圖之 129430.doc -9 · 200845351 後述之實施型態之說明獲得更明確之瞭解。 【實施方式】 以下，參照附圖詳細說明本發明之實施型態。 圖1係本發明之一實施型態之半導體裝 衣直之圖解的剖面 圖。 半導體裝置1係適用QFN之半導體裝置。半導體裝置1 丫 包含半導體晶片2、支持此半導體晶片2之晶粒墊3、與： 導體晶片2電性連接之複數導線4、&將此等封裝之封^樹 脂5 〇 半導體晶片2係在形成功能元件之側之表面（元件形成 面）朝向上方之狀態下，被晶粒接合於晶粒墊3上。又，在 半導體晶片2之表面，藉使布線層之一部分由表面保護膜 露出而形成複數個墊（未圖示）。各墊係經由細金線之 接合線6與導線4電性連接。 成之 曰曰粒墊3及導線4如後所述，係由金屬薄板所形成。 日日粒墊3-體地包含有平面視呈矩形狀之本體部7與包圍 本體部7之周圍之平面視呈矩形框狀之脫落防止部8。 本體^ 7係使其下面7A由封裝樹脂5之下面5A露出。在 由此封裝樹脂5之下面5A露出之本體部7之下面7A，例如 形成有焊料電鍍層（未圖示）。 /脫洛防止部8係形成薄於本體部7。脫落防止部8之上面 係：本體部7之上面形成同一平面。在與半導體晶片2同時 立^衣士線4之狀恶下，封裝樹脂5會環繞進入脫落防止 之下方’故可謀求防止晶粒墊3由封裝樹月旨5脫落。 129430.doc •10- 200845351 導線4係在與晶粒塾3之各側面正交之各方向之兩側，分 別各設有相同數量^晶粒㈣之各侧面對向之導線罐等 間隔地配置於與該對向之側面平行之方向。 各導線4係在與晶粒墊3之側面正交之方向（與晶粒塾化 對向方向）形成為長條之平面視呈矩形狀。而，各導線锡、 -體地包含本體部9、及由下面_晶粒塾3側之端部㈣ 加工所形成之脫落防止部1 〇。
本體部9係使其下面9A由封裝樹脂5之下面5A露出，長 側方向之端面9B由封裝樹脂5之側面5B露出。在由封裝樹 脂5之下面5A露出之本體部9之下面9A，例如形成有焊料 電鑛層（未圖示）’此下面⑽執行作 板(布線基板)上之接合面之外部端子之功能。另二基 本體4 9之上面係被封裝樹脂5所封裝。本體部9之上面擔 負作為内導線之任務，連接有接合線6。 在本體部9之與脫落防止部1〇側相反側之端部，將在下 面9A及端面9B開放之如形成在與導線4之長側方向正交 且與厚度方向正交之寬度方向(沿著端面5B之方向)之全寬 中。 在溝11，埋設有由焊料構成之埋設體12。 有與本體部9之下面9A形成同一平面之下面12A及與本體 I5之&面9B形成同一平面之端面i 2B。又，埋設體12係 在下面12A之端面12B側之端面，具有使埋設體以之材料 之焊料向下方延伸所形成溢料13。 脫洛防止部1 0係形成薄於本體部9。脫落防止部丨〇之上 129430.doc -11 - 200845351 面係與本體部9之上面形成同一平面。在與半導體晶片2同 時樹脂封裝導線4之狀態下，封裝樹脂5會環繞進入脫落防 止部10之下方，故可謀求防止導線4由封裝樹脂5脫落。 圖2係表示使用於半導體裝置1之製造之導線架之一部分 之底面圖。 半導體裝置1如後所述，係由使用之導線架2丨之map方 式所製造。 $線架21係由對金屬（例如，銅、42合金等）之薄板加工 所形成。此導線架21係一體地包含格子狀之支持部22、配 置於被支持部22所包圍之各矩形區域内之晶粒墊3、及配 置於晶粒墊3之周圍之複數導線4。 各導線4係將與晶粒墊3侧相反側之端部連接於支持部 22。在互相相鄰之晶粒墊3之間，配置於一方之晶粒墊3之 周圍之各導線4與配置於他方之晶粒墊3之周圍之各導線4 係在導線4之長側方向夹著支持部22而相對向，且延伸成 一直線狀。而，夾著支持部22而相對向各導線4之溝^係 藉由與溝11同㈣度及寬度形成在支持部22之溝23而連 I即在夾著支持部22而相對向各導線4之端部間，將 溝11及溝23形成作為向導線4之長側方向延伸之1條溝。 又’在圖2中，為容易瞭解起見，在溝11及溝23上附上交 叉影線。 圖3A〜3E係依序表示半導體裝置〗之製造步驟之圖解的 剖面圖。 在半導體裝置1之製造步驟中，如圖3A所示，準備導線 129430.doc 12 200845351 架21。 又，在圖3A〜3E中，導線架21僅顯示其切剖面。 首先，如圖3B所示，在導線架21之溝u及溝23中，填埋 焊料31。焊料31例如可藉電鍍而形成。又，焊料31也可藉 膏印刷及回流而形成。另外，焊料31也可在將球狀焊料配 置於溝11及溝23後藉施行回流而形成。 其次，如圖3C所示，在導線架21之晶粒墊3上，例如， 經由高熔點焊料（熔點260°C以上之焊料）構成之接合劑（未 圖不）晶粒接合半導體晶片2。接著，將接合線6之一端連 接於半導體晶片2之墊，將接合線6之他端連接（線接合)於 導線4 ^__L巧。 所有之半導體晶片2之線接合完成時，如圖3D所示，將 導線架21安置於成型模具，並將導線架21上之所有之半導 體晶片2與導線架21同時利用封裝樹脂32 一併加以封裝。 而，在由封裝樹脂32露出之導線架21之下面（晶粒墊3之本 體部7之下面7A、導線4之本體部9之下面9A)形成焊料電鍍 層（未圖示）。 其後，如圖3E所示，沿著設定於導線架21之支持部22上 之切割線，將切割鋸33由導線架22之下面側置入，除去支 持部22、支持部22上之封裝樹脂32、以及存在於支持部22 之兩側之特疋1度之區域之導線4之一部分及封裝樹脂 32。即’除去存在於圖2所示之二點鏈線所夹之帶狀區域 之導線架21及封裝樹脂32。藉此，各導線4被自支持部22 切離，埋設於溝11之焊料31成為埋設體12，切離分開之封 129430.doc -13- 200845351 裝樹脂32成為封裝樹脂5而 個體。 獲侍圖1所示之半導體裝置1之
溶化故不會有發生半導體裝置1以傾斜之狀態被安裝於 安衣基板之虞。故半導體裝置丨不會發生溢料丨3引起之安 裝不良。 利用此切割㈣之切斷時（切割時），切割鋸33之側面 s接觸料線4、焊料軸設❸2)及封裝樹脂聊裝樹 脂5)。因此’埋在和之焊料31會被切㈣33之側面拉扯 而延伸’如圖i所示’在埋設體12之下面以之端面KB側 之端部有可能產生溢料13M旦，因溝"係沿著導線4之寬 度方向之全寬中形成’故導線4之材料不會產生因被切斷 刀拉扯而延伸之溢料。即使有焊料構成之溢料13存在，該 溢料13也會被半導體裝置丨對安裝基板之安裝時之回流所 又因埋没體12係由焊料所構成，故可使利用作為導線 4與女裝基板之接合劑之焊料濕潤達到埋設體丨2之端面 12B ’可在導線4之端面形成所謂焊料嵌條。因此，容易從 外觀檢查導線4與布線基板之接合（焊接）狀態。 又，在本實施型態中，在導線架21中，夾著支持部22而 相對向各導線4之溝11係藉由與溝11同樣深度及寬度形成 在支持部22之構23而連通。但，在導線架21中，若形成在 各導線4之溝11達到支持部22之兩側之特定寬度之區域（夾 在圖2所示之二點鏈線間之帶狀區域），則也可不在支持部 22形成構23。即，只要將溝11形成使切割鋸33之側面可接 觸到埋入溝11之焊料3丨之長度，則也可不在支持部22形成 129430.doc -14- 200845351 以上，說明本發明之一 之形離廢$ 7 貝轭生恶，但本發明也可以其他 <尘悲員知。例如， 雖棱到適用QFN之半導體裝置，但， 本發明也可適用於、念m 一 《〈用 S0N(small Outlined Non-leaded
Package ·•無接腳小 外形封裝）等其他種類之無接腳封裝之 +導體裝置。
又，不限於導線之端面與封裝樹脂之側面形成同一平面 斤月刀』獨立型’本發明也可適用於適用導線由封裝樹 脂之側面突出之導線切斷型之無接腳封裝之半導體裝置。 不限於無接腳封裝，本發明也可適用於適用導線 由封裝樹脂突出之具有外導線之封裝之半導體裝置。t 再者，半導體裝置不限於map方式，也可利用個別地封 裝各個半導體晶片之個別封裝法製造。 以上’雖已就本發明之實施型態予以詳細說明，但此等 僅不過係用於說明本發明之技術的内容之具體例，本發明 不應被限定於此等具體例而作解釋，本發明之精神及範圍 僅文到後附之申請專利範圍所限定。 本申請案對應於2007年2月27日向曰本國特許廳提出之 特願2007-47394號，該申請案之所有揭示可經由引用而納 入於此。 【圖式簡單說明】 圖1係本發明之一實施型態之半導體裝置之圖解的剖面 圖2係表示使用於半導體裝置之製造之導線架之一部分 129430.doc -15- 200845351 之底面圖。 圖3A係表示半導體裝置之製造步驟（準備導線架之步驟） 之圖解的剖面圖。 圖3B係表示圖3A之次一步驟（埋設焊料之步驟）之圖解的 剖面圖。 圖 圖3C係表示圖3B之次—步驟（接合步驟）之圖解的剖面
圖 圖3D係表示圖3C之次一步 (封裝步驟）之圖解的剖面 圖3E係表示圖3D之次一 圖0 步驟（切割步驟）之圖解的剖 面
【主要元件符號說明】 1 半導體裝置 2 半導體晶片 3 晶粒塾 4 導線 5 封裝樹脂 6 接合線 9A 下面（接合面） 9B 端面 11 溝 12 埋設體 21 導線架 22 支持部 129430.doc -16· 200845351 23 溝 31 焊料 32 樹脂 33 切割鋸 參 129430.doc - \η .

Claims (1)

  1. 200845351 十、申請專利範圍： 1 · 一種半導體裝置，其係包含： 半導體晶片；及 導線’其係配置於前述半導體晶片之周圍而向與前述 半導體晶片之側面交叉之方向延伸，至少遠離前述半導 體晶片之側之端部被接合於安裝基板；且
    在前述導線中，在對前述安裝基板之接合面及在遠離 前述半導體晶片之側之端部開放之溝係在與厚度方向正 父且沿著前述端面之寬度方向之全寬中形成； 在前述溝中，埋設有由焊料構成之埋設體。 2.如請求们之半導體裝置，其中前述埋設體係包含焊料 延伸而形成之溢料。 3· —種導線架，其係包含：
    墊 曰曰粒墊，其係在一方側之面裝載有半導體晶 導線，其係配置於前述晶粒墊之周圍而向與 之對向方向延伸；及 片； 前述晶粒 支持部，端部，且 其係連接前述導線之 遠離前述晶粒墊 之側之 在刖述導線巾’在與遠離前述 述-方側相反側之面，在㈣唆之具/丨之、部之雨 =方向正交之寬度方向之全寬中形成有溝； ，、 W述溝係被焊料完全填埋。 4· 一種半導體裝置之製 線架製造半導體裝置 造方法，其係利用如請求 之方法，包含： 項3之導 129430.doc 200845351 接合步驟’其係在前述晶粒塾上晶粒接合半導體晶 片’以接合線電性連接前述半導體晶片與前述導線； :裝步驟，其係在前述接合步驟後，以使埋入前述溝 ::::二由封裝樹脂露出之方式’藉前述封裝樹脂將 則达丰導體晶片與前述導線架一起封裝；及 切割步驟，其係藉使用切割鑛之切斷， 部及前述騎部上之前述封裝樹脂。 κ支持
    129430.doc
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